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Merge remote-tracking branch 'ocfs2/linux-next'
[linux-2.6/next.git] / sound / soc / codecs / wm8400.c
blobfbee556cbf35adaba1bbca26e6659cb199590c07
1 /*
2 * wm8400.c -- WM8400 ALSA Soc Audio driver
3 *
4 * Copyright 2008, 2009 Wolfson Microelectronics PLC.
5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 */
13
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/pm.h>
21 #include <linux/platform_device.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/mfd/wm8400-audio.h>
24 #include <linux/mfd/wm8400-private.h>
25 #include <linux/mfd/core.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32
33 #include "wm8400.h"
34
35 /* Fake register for internal state */
36 #define WM8400_INTDRIVBITS (WM8400_REGISTER_COUNT + 1)
37 #define WM8400_INMIXL_PWR 0
38 #define WM8400_AINLMUX_PWR 1
39 #define WM8400_INMIXR_PWR 2
40 #define WM8400_AINRMUX_PWR 3
41
42 static struct regulator_bulk_data power[] = {
43 {
44 .supply = "I2S1VDD",
45 },
46 {
47 .supply = "I2S2VDD",
48 },
49 {
50 .supply = "DCVDD",
51 },
52 {
53 .supply = "AVDD",
54 },
55 {
56 .supply = "FLLVDD",
57 },
58 {
59 .supply = "HPVDD",
60 },
61 {
62 .supply = "SPKVDD",
63 },
64 };
65
66 /* codec private data */
67 struct wm8400_priv {
68 struct snd_soc_codec *codec;
69 struct wm8400 *wm8400;
70 u16 fake_register;
71 unsigned int sysclk;
72 unsigned int pcmclk;
73 struct work_struct work;
74 int fll_in, fll_out;
75 };
76
77 static inline unsigned int wm8400_read(struct snd_soc_codec *codec,
78 unsigned int reg)
79 {
80 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
81
82 if (reg == WM8400_INTDRIVBITS)
83 return wm8400->fake_register;
84 else
85 return wm8400_reg_read(wm8400->wm8400, reg);
86 }
87
88 /*
89 * write to the wm8400 register space
90 */
91 static int wm8400_write(struct snd_soc_codec *codec, unsigned int reg,
92 unsigned int value)
93 {
94 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
95
96 if (reg == WM8400_INTDRIVBITS) {
97 wm8400->fake_register = value;
98 return 0;
99 } else
100 return wm8400_set_bits(wm8400->wm8400, reg, 0xffff, value);
101 }
102
103 static void wm8400_codec_reset(struct snd_soc_codec *codec)
104 {
105 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
106
107 wm8400_reset_codec_reg_cache(wm8400->wm8400);
108 }
109
110 static const DECLARE_TLV_DB_SCALE(rec_mix_tlv, -1500, 600, 0);
111
112 static const DECLARE_TLV_DB_SCALE(in_pga_tlv, -1650, 3000, 0);
113
114 static const DECLARE_TLV_DB_SCALE(out_mix_tlv, -2100, 0, 0);
115
116 static const DECLARE_TLV_DB_SCALE(out_pga_tlv, -7300, 600, 0);
117
118 static const DECLARE_TLV_DB_SCALE(out_omix_tlv, -600, 0, 0);
119
120 static const DECLARE_TLV_DB_SCALE(out_dac_tlv, -7163, 0, 0);
121
122 static const DECLARE_TLV_DB_SCALE(in_adc_tlv, -7163, 1763, 0);
123
124 static const DECLARE_TLV_DB_SCALE(out_sidetone_tlv, -3600, 0, 0);
125
126 static int wm8400_outpga_put_volsw_vu(struct snd_kcontrol *kcontrol,
127 struct snd_ctl_elem_value *ucontrol)
128 {
129 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
130 struct soc_mixer_control *mc =
131 (struct soc_mixer_control *)kcontrol->private_value;
132 int reg = mc->reg;
133 int ret;
134 u16 val;
135
136 ret = snd_soc_put_volsw(kcontrol, ucontrol);
137 if (ret < 0)
138 return ret;
139
140 /* now hit the volume update bits (always bit 8) */
141 val = wm8400_read(codec, reg);
142 return wm8400_write(codec, reg, val | 0x0100);
143 }
144
145 #define WM8400_OUTPGA_SINGLE_R_TLV(xname, reg, shift, max, invert, tlv_array) \
146 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
147 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
148 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
149 .tlv.p = (tlv_array), \
150 .info = snd_soc_info_volsw, \
151 .get = snd_soc_get_volsw, .put = wm8400_outpga_put_volsw_vu, \
152 .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert) }
153
154
155 static const char *wm8400_digital_sidetone[] =
156 {"None", "Left ADC", "Right ADC", "Reserved"};
157
158 static const struct soc_enum wm8400_left_digital_sidetone_enum =
159 SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE,
160 WM8400_ADC_TO_DACL_SHIFT, 2, wm8400_digital_sidetone);
161
162 static const struct soc_enum wm8400_right_digital_sidetone_enum =
163 SOC_ENUM_SINGLE(WM8400_DIGITAL_SIDE_TONE,
164 WM8400_ADC_TO_DACR_SHIFT, 2, wm8400_digital_sidetone);
165
166 static const char *wm8400_adcmode[] =
167 {"Hi-fi mode", "Voice mode 1", "Voice mode 2", "Voice mode 3"};
168
169 static const struct soc_enum wm8400_right_adcmode_enum =
170 SOC_ENUM_SINGLE(WM8400_ADC_CTRL, WM8400_ADC_HPF_CUT_SHIFT, 3, wm8400_adcmode);
171
172 static const struct snd_kcontrol_new wm8400_snd_controls[] = {
173 /* INMIXL */
174 SOC_SINGLE("LIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L12MNBST_SHIFT,
175 1, 0),
176 SOC_SINGLE("LIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_L34MNBST_SHIFT,
177 1, 0),
178 /* INMIXR */
179 SOC_SINGLE("RIN12 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R12MNBST_SHIFT,
180 1, 0),
181 SOC_SINGLE("RIN34 PGA Boost", WM8400_INPUT_MIXER3, WM8400_R34MNBST_SHIFT,
182 1, 0),
183
184 /* LOMIX */
185 SOC_SINGLE_TLV("LOMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER3,
186 WM8400_LLI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
187 SOC_SINGLE_TLV("LOMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
188 WM8400_LR12LOVOL_SHIFT, 7, 0, out_mix_tlv),
189 SOC_SINGLE_TLV("LOMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER3,
190 WM8400_LL12LOVOL_SHIFT, 7, 0, out_mix_tlv),
191 SOC_SINGLE_TLV("LOMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER5,
192 WM8400_LRI3LOVOL_SHIFT, 7, 0, out_mix_tlv),
193 SOC_SINGLE_TLV("LOMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
194 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
195 SOC_SINGLE_TLV("LOMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER5,
196 WM8400_LRBLOVOL_SHIFT, 7, 0, out_mix_tlv),
197
198 /* ROMIX */
199 SOC_SINGLE_TLV("ROMIX RIN3 Bypass Volume", WM8400_OUTPUT_MIXER4,
200 WM8400_RRI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
201 SOC_SINGLE_TLV("ROMIX LIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
202 WM8400_RL12ROVOL_SHIFT, 7, 0, out_mix_tlv),
203 SOC_SINGLE_TLV("ROMIX RIN12 PGA Bypass Volume", WM8400_OUTPUT_MIXER4,
204 WM8400_RR12ROVOL_SHIFT, 7, 0, out_mix_tlv),
205 SOC_SINGLE_TLV("ROMIX LIN3 Bypass Volume", WM8400_OUTPUT_MIXER6,
206 WM8400_RLI3ROVOL_SHIFT, 7, 0, out_mix_tlv),
207 SOC_SINGLE_TLV("ROMIX AINLMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
208 WM8400_RLBROVOL_SHIFT, 7, 0, out_mix_tlv),
209 SOC_SINGLE_TLV("ROMIX AINRMUX Bypass Volume", WM8400_OUTPUT_MIXER6,
210 WM8400_RRBROVOL_SHIFT, 7, 0, out_mix_tlv),
211
212 /* LOUT */
213 WM8400_OUTPGA_SINGLE_R_TLV("LOUT Volume", WM8400_LEFT_OUTPUT_VOLUME,
214 WM8400_LOUTVOL_SHIFT, WM8400_LOUTVOL_MASK, 0, out_pga_tlv),
215 SOC_SINGLE("LOUT ZC", WM8400_LEFT_OUTPUT_VOLUME, WM8400_LOZC_SHIFT, 1, 0),
216
217 /* ROUT */
218 WM8400_OUTPGA_SINGLE_R_TLV("ROUT Volume", WM8400_RIGHT_OUTPUT_VOLUME,
219 WM8400_ROUTVOL_SHIFT, WM8400_ROUTVOL_MASK, 0, out_pga_tlv),
220 SOC_SINGLE("ROUT ZC", WM8400_RIGHT_OUTPUT_VOLUME, WM8400_ROZC_SHIFT, 1, 0),
221
222 /* LOPGA */
223 WM8400_OUTPGA_SINGLE_R_TLV("LOPGA Volume", WM8400_LEFT_OPGA_VOLUME,
224 WM8400_LOPGAVOL_SHIFT, WM8400_LOPGAVOL_MASK, 0, out_pga_tlv),
225 SOC_SINGLE("LOPGA ZC Switch", WM8400_LEFT_OPGA_VOLUME,
226 WM8400_LOPGAZC_SHIFT, 1, 0),
227
228 /* ROPGA */
229 WM8400_OUTPGA_SINGLE_R_TLV("ROPGA Volume", WM8400_RIGHT_OPGA_VOLUME,
230 WM8400_ROPGAVOL_SHIFT, WM8400_ROPGAVOL_MASK, 0, out_pga_tlv),
231 SOC_SINGLE("ROPGA ZC Switch", WM8400_RIGHT_OPGA_VOLUME,
232 WM8400_ROPGAZC_SHIFT, 1, 0),
233
234 SOC_SINGLE("LON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
235 WM8400_LONMUTE_SHIFT, 1, 0),
236 SOC_SINGLE("LOP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
237 WM8400_LOPMUTE_SHIFT, 1, 0),
238 SOC_SINGLE("LOP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
239 WM8400_LOATTN_SHIFT, 1, 0),
240 SOC_SINGLE("RON Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
241 WM8400_RONMUTE_SHIFT, 1, 0),
242 SOC_SINGLE("ROP Mute Switch", WM8400_LINE_OUTPUTS_VOLUME,
243 WM8400_ROPMUTE_SHIFT, 1, 0),
244 SOC_SINGLE("ROP Attenuation Switch", WM8400_LINE_OUTPUTS_VOLUME,
245 WM8400_ROATTN_SHIFT, 1, 0),
246
247 SOC_SINGLE("OUT3 Mute Switch", WM8400_OUT3_4_VOLUME,
248 WM8400_OUT3MUTE_SHIFT, 1, 0),
249 SOC_SINGLE("OUT3 Attenuation Switch", WM8400_OUT3_4_VOLUME,
250 WM8400_OUT3ATTN_SHIFT, 1, 0),
251
252 SOC_SINGLE("OUT4 Mute Switch", WM8400_OUT3_4_VOLUME,
253 WM8400_OUT4MUTE_SHIFT, 1, 0),
254 SOC_SINGLE("OUT4 Attenuation Switch", WM8400_OUT3_4_VOLUME,
255 WM8400_OUT4ATTN_SHIFT, 1, 0),
256
257 SOC_SINGLE("Speaker Mode Switch", WM8400_CLASSD1,
258 WM8400_CDMODE_SHIFT, 1, 0),
259
260 SOC_SINGLE("Speaker Output Attenuation Volume", WM8400_SPEAKER_VOLUME,
261 WM8400_SPKATTN_SHIFT, WM8400_SPKATTN_MASK, 0),
262 SOC_SINGLE("Speaker DC Boost Volume", WM8400_CLASSD3,
263 WM8400_DCGAIN_SHIFT, 6, 0),
264 SOC_SINGLE("Speaker AC Boost Volume", WM8400_CLASSD3,
265 WM8400_ACGAIN_SHIFT, 6, 0),
266
267 WM8400_OUTPGA_SINGLE_R_TLV("Left DAC Digital Volume",
268 WM8400_LEFT_DAC_DIGITAL_VOLUME, WM8400_DACL_VOL_SHIFT,
269 127, 0, out_dac_tlv),
270
271 WM8400_OUTPGA_SINGLE_R_TLV("Right DAC Digital Volume",
272 WM8400_RIGHT_DAC_DIGITAL_VOLUME, WM8400_DACR_VOL_SHIFT,
273 127, 0, out_dac_tlv),
274
275 SOC_ENUM("Left Digital Sidetone", wm8400_left_digital_sidetone_enum),
276 SOC_ENUM("Right Digital Sidetone", wm8400_right_digital_sidetone_enum),
277
278 SOC_SINGLE_TLV("Left Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
279 WM8400_ADCL_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
280 SOC_SINGLE_TLV("Right Digital Sidetone Volume", WM8400_DIGITAL_SIDE_TONE,
281 WM8400_ADCR_DAC_SVOL_SHIFT, 15, 0, out_sidetone_tlv),
282
283 SOC_SINGLE("ADC Digital High Pass Filter Switch", WM8400_ADC_CTRL,
284 WM8400_ADC_HPF_ENA_SHIFT, 1, 0),
285
286 SOC_ENUM("ADC HPF Mode", wm8400_right_adcmode_enum),
287
288 WM8400_OUTPGA_SINGLE_R_TLV("Left ADC Digital Volume",
289 WM8400_LEFT_ADC_DIGITAL_VOLUME,
290 WM8400_ADCL_VOL_SHIFT,
291 WM8400_ADCL_VOL_MASK,
292 0,
293 in_adc_tlv),
294
295 WM8400_OUTPGA_SINGLE_R_TLV("Right ADC Digital Volume",
296 WM8400_RIGHT_ADC_DIGITAL_VOLUME,
297 WM8400_ADCR_VOL_SHIFT,
298 WM8400_ADCR_VOL_MASK,
299 0,
300 in_adc_tlv),
301
302 WM8400_OUTPGA_SINGLE_R_TLV("LIN12 Volume",
303 WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
304 WM8400_LIN12VOL_SHIFT,
305 WM8400_LIN12VOL_MASK,
306 0,
307 in_pga_tlv),
308
309 SOC_SINGLE("LIN12 ZC Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
310 WM8400_LI12ZC_SHIFT, 1, 0),
311
312 SOC_SINGLE("LIN12 Mute Switch", WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
313 WM8400_LI12MUTE_SHIFT, 1, 0),
314
315 WM8400_OUTPGA_SINGLE_R_TLV("LIN34 Volume",
316 WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
317 WM8400_LIN34VOL_SHIFT,
318 WM8400_LIN34VOL_MASK,
319 0,
320 in_pga_tlv),
321
322 SOC_SINGLE("LIN34 ZC Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
323 WM8400_LI34ZC_SHIFT, 1, 0),
324
325 SOC_SINGLE("LIN34 Mute Switch", WM8400_LEFT_LINE_INPUT_3_4_VOLUME,
326 WM8400_LI34MUTE_SHIFT, 1, 0),
327
328 WM8400_OUTPGA_SINGLE_R_TLV("RIN12 Volume",
329 WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
330 WM8400_RIN12VOL_SHIFT,
331 WM8400_RIN12VOL_MASK,
332 0,
333 in_pga_tlv),
334
335 SOC_SINGLE("RIN12 ZC Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
336 WM8400_RI12ZC_SHIFT, 1, 0),
337
338 SOC_SINGLE("RIN12 Mute Switch", WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
339 WM8400_RI12MUTE_SHIFT, 1, 0),
340
341 WM8400_OUTPGA_SINGLE_R_TLV("RIN34 Volume",
342 WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
343 WM8400_RIN34VOL_SHIFT,
344 WM8400_RIN34VOL_MASK,
345 0,
346 in_pga_tlv),
347
348 SOC_SINGLE("RIN34 ZC Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
349 WM8400_RI34ZC_SHIFT, 1, 0),
350
351 SOC_SINGLE("RIN34 Mute Switch", WM8400_RIGHT_LINE_INPUT_3_4_VOLUME,
352 WM8400_RI34MUTE_SHIFT, 1, 0),
353
354 };
355
356 /* add non dapm controls */
357 static int wm8400_add_controls(struct snd_soc_codec *codec)
358 {
359 return snd_soc_add_controls(codec, wm8400_snd_controls,
360 ARRAY_SIZE(wm8400_snd_controls));
361 }
362
363 /*
364 * _DAPM_ Controls
365 */
366
367 static int inmixer_event (struct snd_soc_dapm_widget *w,
368 struct snd_kcontrol *kcontrol, int event)
369 {
370 u16 reg, fakepower;
371
372 reg = wm8400_read(w->codec, WM8400_POWER_MANAGEMENT_2);
373 fakepower = wm8400_read(w->codec, WM8400_INTDRIVBITS);
374
375 if (fakepower & ((1 << WM8400_INMIXL_PWR) |
376 (1 << WM8400_AINLMUX_PWR))) {
377 reg |= WM8400_AINL_ENA;
378 } else {
379 reg &= ~WM8400_AINL_ENA;
380 }
381
382 if (fakepower & ((1 << WM8400_INMIXR_PWR) |
383 (1 << WM8400_AINRMUX_PWR))) {
384 reg |= WM8400_AINR_ENA;
385 } else {
386 reg &= ~WM8400_AINL_ENA;
387 }
388 wm8400_write(w->codec, WM8400_POWER_MANAGEMENT_2, reg);
389
390 return 0;
391 }
392
393 static int outmixer_event (struct snd_soc_dapm_widget *w,
394 struct snd_kcontrol * kcontrol, int event)
395 {
396 struct soc_mixer_control *mc =
397 (struct soc_mixer_control *)kcontrol->private_value;
398 u32 reg_shift = mc->shift;
399 int ret = 0;
400 u16 reg;
401
402 switch (reg_shift) {
403 case WM8400_SPEAKER_MIXER | (WM8400_LDSPK << 8) :
404 reg = wm8400_read(w->codec, WM8400_OUTPUT_MIXER1);
405 if (reg & WM8400_LDLO) {
406 printk(KERN_WARNING
407 "Cannot set as Output Mixer 1 LDLO Set\n");
408 ret = -1;
409 }
410 break;
411 case WM8400_SPEAKER_MIXER | (WM8400_RDSPK << 8):
412 reg = wm8400_read(w->codec, WM8400_OUTPUT_MIXER2);
413 if (reg & WM8400_RDRO) {
414 printk(KERN_WARNING
415 "Cannot set as Output Mixer 2 RDRO Set\n");
416 ret = -1;
417 }
418 break;
419 case WM8400_OUTPUT_MIXER1 | (WM8400_LDLO << 8):
420 reg = wm8400_read(w->codec, WM8400_SPEAKER_MIXER);
421 if (reg & WM8400_LDSPK) {
422 printk(KERN_WARNING
423 "Cannot set as Speaker Mixer LDSPK Set\n");
424 ret = -1;
425 }
426 break;
427 case WM8400_OUTPUT_MIXER2 | (WM8400_RDRO << 8):
428 reg = wm8400_read(w->codec, WM8400_SPEAKER_MIXER);
429 if (reg & WM8400_RDSPK) {
430 printk(KERN_WARNING
431 "Cannot set as Speaker Mixer RDSPK Set\n");
432 ret = -1;
433 }
434 break;
435 }
436
437 return ret;
438 }
439
440 /* INMIX dB values */
441 static const unsigned int in_mix_tlv[] = {
442 TLV_DB_RANGE_HEAD(1),
443 0,7, TLV_DB_SCALE_ITEM(-1200, 600, 0),
444 };
445
446 /* Left In PGA Connections */
447 static const struct snd_kcontrol_new wm8400_dapm_lin12_pga_controls[] = {
448 SOC_DAPM_SINGLE("LIN1 Switch", WM8400_INPUT_MIXER2, WM8400_LMN1_SHIFT, 1, 0),
449 SOC_DAPM_SINGLE("LIN2 Switch", WM8400_INPUT_MIXER2, WM8400_LMP2_SHIFT, 1, 0),
450 };
451
452 static const struct snd_kcontrol_new wm8400_dapm_lin34_pga_controls[] = {
453 SOC_DAPM_SINGLE("LIN3 Switch", WM8400_INPUT_MIXER2, WM8400_LMN3_SHIFT, 1, 0),
454 SOC_DAPM_SINGLE("LIN4 Switch", WM8400_INPUT_MIXER2, WM8400_LMP4_SHIFT, 1, 0),
455 };
456
457 /* Right In PGA Connections */
458 static const struct snd_kcontrol_new wm8400_dapm_rin12_pga_controls[] = {
459 SOC_DAPM_SINGLE("RIN1 Switch", WM8400_INPUT_MIXER2, WM8400_RMN1_SHIFT, 1, 0),
460 SOC_DAPM_SINGLE("RIN2 Switch", WM8400_INPUT_MIXER2, WM8400_RMP2_SHIFT, 1, 0),
461 };
462
463 static const struct snd_kcontrol_new wm8400_dapm_rin34_pga_controls[] = {
464 SOC_DAPM_SINGLE("RIN3 Switch", WM8400_INPUT_MIXER2, WM8400_RMN3_SHIFT, 1, 0),
465 SOC_DAPM_SINGLE("RIN4 Switch", WM8400_INPUT_MIXER2, WM8400_RMP4_SHIFT, 1, 0),
466 };
467
468 /* INMIXL */
469 static const struct snd_kcontrol_new wm8400_dapm_inmixl_controls[] = {
470 SOC_DAPM_SINGLE_TLV("Record Left Volume", WM8400_INPUT_MIXER3,
471 WM8400_LDBVOL_SHIFT, WM8400_LDBVOL_MASK, 0, in_mix_tlv),
472 SOC_DAPM_SINGLE_TLV("LIN2 Volume", WM8400_INPUT_MIXER5, WM8400_LI2BVOL_SHIFT,
473 7, 0, in_mix_tlv),
474 SOC_DAPM_SINGLE("LINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
475 1, 0),
476 SOC_DAPM_SINGLE("LINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
477 1, 0),
478 };
479
480 /* INMIXR */
481 static const struct snd_kcontrol_new wm8400_dapm_inmixr_controls[] = {
482 SOC_DAPM_SINGLE_TLV("Record Right Volume", WM8400_INPUT_MIXER4,
483 WM8400_RDBVOL_SHIFT, WM8400_RDBVOL_MASK, 0, in_mix_tlv),
484 SOC_DAPM_SINGLE_TLV("RIN2 Volume", WM8400_INPUT_MIXER6, WM8400_RI2BVOL_SHIFT,
485 7, 0, in_mix_tlv),
486 SOC_DAPM_SINGLE("RINPGA12 Switch", WM8400_INPUT_MIXER3, WM8400_L12MNB_SHIFT,
487 1, 0),
488 SOC_DAPM_SINGLE("RINPGA34 Switch", WM8400_INPUT_MIXER3, WM8400_L34MNB_SHIFT,
489 1, 0),
490 };
491
492 /* AINLMUX */
493 static const char *wm8400_ainlmux[] =
494 {"INMIXL Mix", "RXVOICE Mix", "DIFFINL Mix"};
495
496 static const struct soc_enum wm8400_ainlmux_enum =
497 SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINLMODE_SHIFT,
498 ARRAY_SIZE(wm8400_ainlmux), wm8400_ainlmux);
499
500 static const struct snd_kcontrol_new wm8400_dapm_ainlmux_controls =
501 SOC_DAPM_ENUM("Route", wm8400_ainlmux_enum);
502
503 /* DIFFINL */
504
505 /* AINRMUX */
506 static const char *wm8400_ainrmux[] =
507 {"INMIXR Mix", "RXVOICE Mix", "DIFFINR Mix"};
508
509 static const struct soc_enum wm8400_ainrmux_enum =
510 SOC_ENUM_SINGLE( WM8400_INPUT_MIXER1, WM8400_AINRMODE_SHIFT,
511 ARRAY_SIZE(wm8400_ainrmux), wm8400_ainrmux);
512
513 static const struct snd_kcontrol_new wm8400_dapm_ainrmux_controls =
514 SOC_DAPM_ENUM("Route", wm8400_ainrmux_enum);
515
516 /* RXVOICE */
517 static const struct snd_kcontrol_new wm8400_dapm_rxvoice_controls[] = {
518 SOC_DAPM_SINGLE_TLV("LIN4/RXN", WM8400_INPUT_MIXER5, WM8400_LR4BVOL_SHIFT,
519 WM8400_LR4BVOL_MASK, 0, in_mix_tlv),
520 SOC_DAPM_SINGLE_TLV("RIN4/RXP", WM8400_INPUT_MIXER6, WM8400_RL4BVOL_SHIFT,
521 WM8400_RL4BVOL_MASK, 0, in_mix_tlv),
522 };
523
524 /* LOMIX */
525 static const struct snd_kcontrol_new wm8400_dapm_lomix_controls[] = {
526 SOC_DAPM_SINGLE("LOMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
527 WM8400_LRBLO_SHIFT, 1, 0),
528 SOC_DAPM_SINGLE("LOMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER1,
529 WM8400_LLBLO_SHIFT, 1, 0),
530 SOC_DAPM_SINGLE("LOMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
531 WM8400_LRI3LO_SHIFT, 1, 0),
532 SOC_DAPM_SINGLE("LOMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER1,
533 WM8400_LLI3LO_SHIFT, 1, 0),
534 SOC_DAPM_SINGLE("LOMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
535 WM8400_LR12LO_SHIFT, 1, 0),
536 SOC_DAPM_SINGLE("LOMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER1,
537 WM8400_LL12LO_SHIFT, 1, 0),
538 SOC_DAPM_SINGLE("LOMIX Left DAC Switch", WM8400_OUTPUT_MIXER1,
539 WM8400_LDLO_SHIFT, 1, 0),
540 };
541
542 /* ROMIX */
543 static const struct snd_kcontrol_new wm8400_dapm_romix_controls[] = {
544 SOC_DAPM_SINGLE("ROMIX Left ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
545 WM8400_RLBRO_SHIFT, 1, 0),
546 SOC_DAPM_SINGLE("ROMIX Right ADC Bypass Switch", WM8400_OUTPUT_MIXER2,
547 WM8400_RRBRO_SHIFT, 1, 0),
548 SOC_DAPM_SINGLE("ROMIX LIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
549 WM8400_RLI3RO_SHIFT, 1, 0),
550 SOC_DAPM_SINGLE("ROMIX RIN3 Bypass Switch", WM8400_OUTPUT_MIXER2,
551 WM8400_RRI3RO_SHIFT, 1, 0),
552 SOC_DAPM_SINGLE("ROMIX LIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
553 WM8400_RL12RO_SHIFT, 1, 0),
554 SOC_DAPM_SINGLE("ROMIX RIN12 PGA Bypass Switch", WM8400_OUTPUT_MIXER2,
555 WM8400_RR12RO_SHIFT, 1, 0),
556 SOC_DAPM_SINGLE("ROMIX Right DAC Switch", WM8400_OUTPUT_MIXER2,
557 WM8400_RDRO_SHIFT, 1, 0),
558 };
559
560 /* LONMIX */
561 static const struct snd_kcontrol_new wm8400_dapm_lonmix_controls[] = {
562 SOC_DAPM_SINGLE("LONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
563 WM8400_LLOPGALON_SHIFT, 1, 0),
564 SOC_DAPM_SINGLE("LONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER1,
565 WM8400_LROPGALON_SHIFT, 1, 0),
566 SOC_DAPM_SINGLE("LONMIX Inverted LOP Switch", WM8400_LINE_MIXER1,
567 WM8400_LOPLON_SHIFT, 1, 0),
568 };
569
570 /* LOPMIX */
571 static const struct snd_kcontrol_new wm8400_dapm_lopmix_controls[] = {
572 SOC_DAPM_SINGLE("LOPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER1,
573 WM8400_LR12LOP_SHIFT, 1, 0),
574 SOC_DAPM_SINGLE("LOPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER1,
575 WM8400_LL12LOP_SHIFT, 1, 0),
576 SOC_DAPM_SINGLE("LOPMIX Left Mixer PGA Switch", WM8400_LINE_MIXER1,
577 WM8400_LLOPGALOP_SHIFT, 1, 0),
578 };
579
580 /* RONMIX */
581 static const struct snd_kcontrol_new wm8400_dapm_ronmix_controls[] = {
582 SOC_DAPM_SINGLE("RONMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
583 WM8400_RROPGARON_SHIFT, 1, 0),
584 SOC_DAPM_SINGLE("RONMIX Left Mixer PGA Switch", WM8400_LINE_MIXER2,
585 WM8400_RLOPGARON_SHIFT, 1, 0),
586 SOC_DAPM_SINGLE("RONMIX Inverted ROP Switch", WM8400_LINE_MIXER2,
587 WM8400_ROPRON_SHIFT, 1, 0),
588 };
589
590 /* ROPMIX */
591 static const struct snd_kcontrol_new wm8400_dapm_ropmix_controls[] = {
592 SOC_DAPM_SINGLE("ROPMIX Left Mic Bypass Switch", WM8400_LINE_MIXER2,
593 WM8400_RL12ROP_SHIFT, 1, 0),
594 SOC_DAPM_SINGLE("ROPMIX Right Mic Bypass Switch", WM8400_LINE_MIXER2,
595 WM8400_RR12ROP_SHIFT, 1, 0),
596 SOC_DAPM_SINGLE("ROPMIX Right Mixer PGA Switch", WM8400_LINE_MIXER2,
597 WM8400_RROPGAROP_SHIFT, 1, 0),
598 };
599
600 /* OUT3MIX */
601 static const struct snd_kcontrol_new wm8400_dapm_out3mix_controls[] = {
602 SOC_DAPM_SINGLE("OUT3MIX LIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
603 WM8400_LI4O3_SHIFT, 1, 0),
604 SOC_DAPM_SINGLE("OUT3MIX Left Out PGA Switch", WM8400_OUT3_4_MIXER,
605 WM8400_LPGAO3_SHIFT, 1, 0),
606 };
607
608 /* OUT4MIX */
609 static const struct snd_kcontrol_new wm8400_dapm_out4mix_controls[] = {
610 SOC_DAPM_SINGLE("OUT4MIX Right Out PGA Switch", WM8400_OUT3_4_MIXER,
611 WM8400_RPGAO4_SHIFT, 1, 0),
612 SOC_DAPM_SINGLE("OUT4MIX RIN4/RXP Bypass Switch", WM8400_OUT3_4_MIXER,
613 WM8400_RI4O4_SHIFT, 1, 0),
614 };
615
616 /* SPKMIX */
617 static const struct snd_kcontrol_new wm8400_dapm_spkmix_controls[] = {
618 SOC_DAPM_SINGLE("SPKMIX LIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
619 WM8400_LI2SPK_SHIFT, 1, 0),
620 SOC_DAPM_SINGLE("SPKMIX LADC Bypass Switch", WM8400_SPEAKER_MIXER,
621 WM8400_LB2SPK_SHIFT, 1, 0),
622 SOC_DAPM_SINGLE("SPKMIX Left Mixer PGA Switch", WM8400_SPEAKER_MIXER,
623 WM8400_LOPGASPK_SHIFT, 1, 0),
624 SOC_DAPM_SINGLE("SPKMIX Left DAC Switch", WM8400_SPEAKER_MIXER,
625 WM8400_LDSPK_SHIFT, 1, 0),
626 SOC_DAPM_SINGLE("SPKMIX Right DAC Switch", WM8400_SPEAKER_MIXER,
627 WM8400_RDSPK_SHIFT, 1, 0),
628 SOC_DAPM_SINGLE("SPKMIX Right Mixer PGA Switch", WM8400_SPEAKER_MIXER,
629 WM8400_ROPGASPK_SHIFT, 1, 0),
630 SOC_DAPM_SINGLE("SPKMIX RADC Bypass Switch", WM8400_SPEAKER_MIXER,
631 WM8400_RL12ROP_SHIFT, 1, 0),
632 SOC_DAPM_SINGLE("SPKMIX RIN2 Bypass Switch", WM8400_SPEAKER_MIXER,
633 WM8400_RI2SPK_SHIFT, 1, 0),
634 };
635
636 static const struct snd_soc_dapm_widget wm8400_dapm_widgets[] = {
637 /* Input Side */
638 /* Input Lines */
639 SND_SOC_DAPM_INPUT("LIN1"),
640 SND_SOC_DAPM_INPUT("LIN2"),
641 SND_SOC_DAPM_INPUT("LIN3"),
642 SND_SOC_DAPM_INPUT("LIN4/RXN"),
643 SND_SOC_DAPM_INPUT("RIN3"),
644 SND_SOC_DAPM_INPUT("RIN4/RXP"),
645 SND_SOC_DAPM_INPUT("RIN1"),
646 SND_SOC_DAPM_INPUT("RIN2"),
647 SND_SOC_DAPM_INPUT("Internal ADC Source"),
648
649 /* DACs */
650 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", WM8400_POWER_MANAGEMENT_2,
651 WM8400_ADCL_ENA_SHIFT, 0),
652 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", WM8400_POWER_MANAGEMENT_2,
653 WM8400_ADCR_ENA_SHIFT, 0),
654
655 /* Input PGAs */
656 SND_SOC_DAPM_MIXER("LIN12 PGA", WM8400_POWER_MANAGEMENT_2,
657 WM8400_LIN12_ENA_SHIFT,
658 0, &wm8400_dapm_lin12_pga_controls[0],
659 ARRAY_SIZE(wm8400_dapm_lin12_pga_controls)),
660 SND_SOC_DAPM_MIXER("LIN34 PGA", WM8400_POWER_MANAGEMENT_2,
661 WM8400_LIN34_ENA_SHIFT,
662 0, &wm8400_dapm_lin34_pga_controls[0],
663 ARRAY_SIZE(wm8400_dapm_lin34_pga_controls)),
664 SND_SOC_DAPM_MIXER("RIN12 PGA", WM8400_POWER_MANAGEMENT_2,
665 WM8400_RIN12_ENA_SHIFT,
666 0, &wm8400_dapm_rin12_pga_controls[0],
667 ARRAY_SIZE(wm8400_dapm_rin12_pga_controls)),
668 SND_SOC_DAPM_MIXER("RIN34 PGA", WM8400_POWER_MANAGEMENT_2,
669 WM8400_RIN34_ENA_SHIFT,
670 0, &wm8400_dapm_rin34_pga_controls[0],
671 ARRAY_SIZE(wm8400_dapm_rin34_pga_controls)),
672
673 /* INMIXL */
674 SND_SOC_DAPM_MIXER_E("INMIXL", WM8400_INTDRIVBITS, WM8400_INMIXL_PWR, 0,
675 &wm8400_dapm_inmixl_controls[0],
676 ARRAY_SIZE(wm8400_dapm_inmixl_controls),
677 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
678
679 /* AINLMUX */
680 SND_SOC_DAPM_MUX_E("AILNMUX", WM8400_INTDRIVBITS, WM8400_AINLMUX_PWR, 0,
681 &wm8400_dapm_ainlmux_controls, inmixer_event,
682 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
683
684 /* INMIXR */
685 SND_SOC_DAPM_MIXER_E("INMIXR", WM8400_INTDRIVBITS, WM8400_INMIXR_PWR, 0,
686 &wm8400_dapm_inmixr_controls[0],
687 ARRAY_SIZE(wm8400_dapm_inmixr_controls),
688 inmixer_event, SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
689
690 /* AINRMUX */
691 SND_SOC_DAPM_MUX_E("AIRNMUX", WM8400_INTDRIVBITS, WM8400_AINRMUX_PWR, 0,
692 &wm8400_dapm_ainrmux_controls, inmixer_event,
693 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
694
695 /* Output Side */
696 /* DACs */
697 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", WM8400_POWER_MANAGEMENT_3,
698 WM8400_DACL_ENA_SHIFT, 0),
699 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", WM8400_POWER_MANAGEMENT_3,
700 WM8400_DACR_ENA_SHIFT, 0),
701
702 /* LOMIX */
703 SND_SOC_DAPM_MIXER_E("LOMIX", WM8400_POWER_MANAGEMENT_3,
704 WM8400_LOMIX_ENA_SHIFT,
705 0, &wm8400_dapm_lomix_controls[0],
706 ARRAY_SIZE(wm8400_dapm_lomix_controls),
707 outmixer_event, SND_SOC_DAPM_PRE_REG),
708
709 /* LONMIX */
710 SND_SOC_DAPM_MIXER("LONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LON_ENA_SHIFT,
711 0, &wm8400_dapm_lonmix_controls[0],
712 ARRAY_SIZE(wm8400_dapm_lonmix_controls)),
713
714 /* LOPMIX */
715 SND_SOC_DAPM_MIXER("LOPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_LOP_ENA_SHIFT,
716 0, &wm8400_dapm_lopmix_controls[0],
717 ARRAY_SIZE(wm8400_dapm_lopmix_controls)),
718
719 /* OUT3MIX */
720 SND_SOC_DAPM_MIXER("OUT3MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT3_ENA_SHIFT,
721 0, &wm8400_dapm_out3mix_controls[0],
722 ARRAY_SIZE(wm8400_dapm_out3mix_controls)),
723
724 /* SPKMIX */
725 SND_SOC_DAPM_MIXER_E("SPKMIX", WM8400_POWER_MANAGEMENT_1, WM8400_SPK_ENA_SHIFT,
726 0, &wm8400_dapm_spkmix_controls[0],
727 ARRAY_SIZE(wm8400_dapm_spkmix_controls), outmixer_event,
728 SND_SOC_DAPM_PRE_REG),
729
730 /* OUT4MIX */
731 SND_SOC_DAPM_MIXER("OUT4MIX", WM8400_POWER_MANAGEMENT_1, WM8400_OUT4_ENA_SHIFT,
732 0, &wm8400_dapm_out4mix_controls[0],
733 ARRAY_SIZE(wm8400_dapm_out4mix_controls)),
734
735 /* ROPMIX */
736 SND_SOC_DAPM_MIXER("ROPMIX", WM8400_POWER_MANAGEMENT_3, WM8400_ROP_ENA_SHIFT,
737 0, &wm8400_dapm_ropmix_controls[0],
738 ARRAY_SIZE(wm8400_dapm_ropmix_controls)),
739
740 /* RONMIX */
741 SND_SOC_DAPM_MIXER("RONMIX", WM8400_POWER_MANAGEMENT_3, WM8400_RON_ENA_SHIFT,
742 0, &wm8400_dapm_ronmix_controls[0],
743 ARRAY_SIZE(wm8400_dapm_ronmix_controls)),
744
745 /* ROMIX */
746 SND_SOC_DAPM_MIXER_E("ROMIX", WM8400_POWER_MANAGEMENT_3,
747 WM8400_ROMIX_ENA_SHIFT,
748 0, &wm8400_dapm_romix_controls[0],
749 ARRAY_SIZE(wm8400_dapm_romix_controls),
750 outmixer_event, SND_SOC_DAPM_PRE_REG),
751
752 /* LOUT PGA */
753 SND_SOC_DAPM_PGA("LOUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_LOUT_ENA_SHIFT,
754 0, NULL, 0),
755
756 /* ROUT PGA */
757 SND_SOC_DAPM_PGA("ROUT PGA", WM8400_POWER_MANAGEMENT_1, WM8400_ROUT_ENA_SHIFT,
758 0, NULL, 0),
759
760 /* LOPGA */
761 SND_SOC_DAPM_PGA("LOPGA", WM8400_POWER_MANAGEMENT_3, WM8400_LOPGA_ENA_SHIFT, 0,
762 NULL, 0),
763
764 /* ROPGA */
765 SND_SOC_DAPM_PGA("ROPGA", WM8400_POWER_MANAGEMENT_3, WM8400_ROPGA_ENA_SHIFT, 0,
766 NULL, 0),
767
768 /* MICBIAS */
769 SND_SOC_DAPM_MICBIAS("MICBIAS", WM8400_POWER_MANAGEMENT_1,
770 WM8400_MIC1BIAS_ENA_SHIFT, 0),
771
772 SND_SOC_DAPM_OUTPUT("LON"),
773 SND_SOC_DAPM_OUTPUT("LOP"),
774 SND_SOC_DAPM_OUTPUT("OUT3"),
775 SND_SOC_DAPM_OUTPUT("LOUT"),
776 SND_SOC_DAPM_OUTPUT("SPKN"),
777 SND_SOC_DAPM_OUTPUT("SPKP"),
778 SND_SOC_DAPM_OUTPUT("ROUT"),
779 SND_SOC_DAPM_OUTPUT("OUT4"),
780 SND_SOC_DAPM_OUTPUT("ROP"),
781 SND_SOC_DAPM_OUTPUT("RON"),
782
783 SND_SOC_DAPM_OUTPUT("Internal DAC Sink"),
784 };
785
786 static const struct snd_soc_dapm_route audio_map[] = {
787 /* Make DACs turn on when playing even if not mixed into any outputs */
788 {"Internal DAC Sink", NULL, "Left DAC"},
789 {"Internal DAC Sink", NULL, "Right DAC"},
790
791 /* Make ADCs turn on when recording
792 * even if not mixed from any inputs */
793 {"Left ADC", NULL, "Internal ADC Source"},
794 {"Right ADC", NULL, "Internal ADC Source"},
795
796 /* Input Side */
797 /* LIN12 PGA */
798 {"LIN12 PGA", "LIN1 Switch", "LIN1"},
799 {"LIN12 PGA", "LIN2 Switch", "LIN2"},
800 /* LIN34 PGA */
801 {"LIN34 PGA", "LIN3 Switch", "LIN3"},
802 {"LIN34 PGA", "LIN4 Switch", "LIN4/RXN"},
803 /* INMIXL */
804 {"INMIXL", "Record Left Volume", "LOMIX"},
805 {"INMIXL", "LIN2 Volume", "LIN2"},
806 {"INMIXL", "LINPGA12 Switch", "LIN12 PGA"},
807 {"INMIXL", "LINPGA34 Switch", "LIN34 PGA"},
808 /* AILNMUX */
809 {"AILNMUX", "INMIXL Mix", "INMIXL"},
810 {"AILNMUX", "DIFFINL Mix", "LIN12 PGA"},
811 {"AILNMUX", "DIFFINL Mix", "LIN34 PGA"},
812 {"AILNMUX", "RXVOICE Mix", "LIN4/RXN"},
813 {"AILNMUX", "RXVOICE Mix", "RIN4/RXP"},
814 /* ADC */
815 {"Left ADC", NULL, "AILNMUX"},
816
817 /* RIN12 PGA */
818 {"RIN12 PGA", "RIN1 Switch", "RIN1"},
819 {"RIN12 PGA", "RIN2 Switch", "RIN2"},
820 /* RIN34 PGA */
821 {"RIN34 PGA", "RIN3 Switch", "RIN3"},
822 {"RIN34 PGA", "RIN4 Switch", "RIN4/RXP"},
823 /* INMIXL */
824 {"INMIXR", "Record Right Volume", "ROMIX"},
825 {"INMIXR", "RIN2 Volume", "RIN2"},
826 {"INMIXR", "RINPGA12 Switch", "RIN12 PGA"},
827 {"INMIXR", "RINPGA34 Switch", "RIN34 PGA"},
828 /* AIRNMUX */
829 {"AIRNMUX", "INMIXR Mix", "INMIXR"},
830 {"AIRNMUX", "DIFFINR Mix", "RIN12 PGA"},
831 {"AIRNMUX", "DIFFINR Mix", "RIN34 PGA"},
832 {"AIRNMUX", "RXVOICE Mix", "LIN4/RXN"},
833 {"AIRNMUX", "RXVOICE Mix", "RIN4/RXP"},
834 /* ADC */
835 {"Right ADC", NULL, "AIRNMUX"},
836
837 /* LOMIX */
838 {"LOMIX", "LOMIX RIN3 Bypass Switch", "RIN3"},
839 {"LOMIX", "LOMIX LIN3 Bypass Switch", "LIN3"},
840 {"LOMIX", "LOMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
841 {"LOMIX", "LOMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
842 {"LOMIX", "LOMIX Right ADC Bypass Switch", "AIRNMUX"},
843 {"LOMIX", "LOMIX Left ADC Bypass Switch", "AILNMUX"},
844 {"LOMIX", "LOMIX Left DAC Switch", "Left DAC"},
845
846 /* ROMIX */
847 {"ROMIX", "ROMIX RIN3 Bypass Switch", "RIN3"},
848 {"ROMIX", "ROMIX LIN3 Bypass Switch", "LIN3"},
849 {"ROMIX", "ROMIX LIN12 PGA Bypass Switch", "LIN12 PGA"},
850 {"ROMIX", "ROMIX RIN12 PGA Bypass Switch", "RIN12 PGA"},
851 {"ROMIX", "ROMIX Right ADC Bypass Switch", "AIRNMUX"},
852 {"ROMIX", "ROMIX Left ADC Bypass Switch", "AILNMUX"},
853 {"ROMIX", "ROMIX Right DAC Switch", "Right DAC"},
854
855 /* SPKMIX */
856 {"SPKMIX", "SPKMIX LIN2 Bypass Switch", "LIN2"},
857 {"SPKMIX", "SPKMIX RIN2 Bypass Switch", "RIN2"},
858 {"SPKMIX", "SPKMIX LADC Bypass Switch", "AILNMUX"},
859 {"SPKMIX", "SPKMIX RADC Bypass Switch", "AIRNMUX"},
860 {"SPKMIX", "SPKMIX Left Mixer PGA Switch", "LOPGA"},
861 {"SPKMIX", "SPKMIX Right Mixer PGA Switch", "ROPGA"},
862 {"SPKMIX", "SPKMIX Right DAC Switch", "Right DAC"},
863 {"SPKMIX", "SPKMIX Left DAC Switch", "Right DAC"},
864
865 /* LONMIX */
866 {"LONMIX", "LONMIX Left Mixer PGA Switch", "LOPGA"},
867 {"LONMIX", "LONMIX Right Mixer PGA Switch", "ROPGA"},
868 {"LONMIX", "LONMIX Inverted LOP Switch", "LOPMIX"},
869
870 /* LOPMIX */
871 {"LOPMIX", "LOPMIX Right Mic Bypass Switch", "RIN12 PGA"},
872 {"LOPMIX", "LOPMIX Left Mic Bypass Switch", "LIN12 PGA"},
873 {"LOPMIX", "LOPMIX Left Mixer PGA Switch", "LOPGA"},
874
875 /* OUT3MIX */
876 {"OUT3MIX", "OUT3MIX LIN4/RXP Bypass Switch", "LIN4/RXN"},
877 {"OUT3MIX", "OUT3MIX Left Out PGA Switch", "LOPGA"},
878
879 /* OUT4MIX */
880 {"OUT4MIX", "OUT4MIX Right Out PGA Switch", "ROPGA"},
881 {"OUT4MIX", "OUT4MIX RIN4/RXP Bypass Switch", "RIN4/RXP"},
882
883 /* RONMIX */
884 {"RONMIX", "RONMIX Right Mixer PGA Switch", "ROPGA"},
885 {"RONMIX", "RONMIX Left Mixer PGA Switch", "LOPGA"},
886 {"RONMIX", "RONMIX Inverted ROP Switch", "ROPMIX"},
887
888 /* ROPMIX */
889 {"ROPMIX", "ROPMIX Left Mic Bypass Switch", "LIN12 PGA"},
890 {"ROPMIX", "ROPMIX Right Mic Bypass Switch", "RIN12 PGA"},
891 {"ROPMIX", "ROPMIX Right Mixer PGA Switch", "ROPGA"},
892
893 /* Out Mixer PGAs */
894 {"LOPGA", NULL, "LOMIX"},
895 {"ROPGA", NULL, "ROMIX"},
896
897 {"LOUT PGA", NULL, "LOMIX"},
898 {"ROUT PGA", NULL, "ROMIX"},
899
900 /* Output Pins */
901 {"LON", NULL, "LONMIX"},
902 {"LOP", NULL, "LOPMIX"},
903 {"OUT3", NULL, "OUT3MIX"},
904 {"LOUT", NULL, "LOUT PGA"},
905 {"SPKN", NULL, "SPKMIX"},
906 {"ROUT", NULL, "ROUT PGA"},
907 {"OUT4", NULL, "OUT4MIX"},
908 {"ROP", NULL, "ROPMIX"},
909 {"RON", NULL, "RONMIX"},
910 };
911
912 static int wm8400_add_widgets(struct snd_soc_codec *codec)
913 {
914 struct snd_soc_dapm_context *dapm = &codec->dapm;
915
916 snd_soc_dapm_new_controls(dapm, wm8400_dapm_widgets,
917 ARRAY_SIZE(wm8400_dapm_widgets));
918 snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
919
920 return 0;
921 }
922
923 /*
924 * Clock after FLL and dividers
925 */
926 static int wm8400_set_dai_sysclk(struct snd_soc_dai *codec_dai,
927 int clk_id, unsigned int freq, int dir)
928 {
929 struct snd_soc_codec *codec = codec_dai->codec;
930 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
931
932 wm8400->sysclk = freq;
933 return 0;
934 }
935
936 struct fll_factors {
937 u16 n;
938 u16 k;
939 u16 outdiv;
940 u16 fratio;
941 u16 freq_ref;
942 };
943
944 #define FIXED_FLL_SIZE ((1 << 16) * 10)
945
946 static int fll_factors(struct wm8400_priv *wm8400, struct fll_factors *factors,
947 unsigned int Fref, unsigned int Fout)
948 {
949 u64 Kpart;
950 unsigned int K, Nmod, target;
951
952 factors->outdiv = 2;
953 while (Fout * factors->outdiv < 90000000 ||
954 Fout * factors->outdiv > 100000000) {
955 factors->outdiv *= 2;
956 if (factors->outdiv > 32) {
957 dev_err(wm8400->wm8400->dev,
958 "Unsupported FLL output frequency %uHz\n",
959 Fout);
960 return -EINVAL;
961 }
962 }
963 target = Fout * factors->outdiv;
964 factors->outdiv = factors->outdiv >> 2;
965
966 if (Fref < 48000)
967 factors->freq_ref = 1;
968 else
969 factors->freq_ref = 0;
970
971 if (Fref < 1000000)
972 factors->fratio = 9;
973 else
974 factors->fratio = 0;
975
976 /* Ensure we have a fractional part */
977 do {
978 if (Fref < 1000000)
979 factors->fratio--;
980 else
981 factors->fratio++;
982
983 if (factors->fratio < 1 || factors->fratio > 8) {
984 dev_err(wm8400->wm8400->dev,
985 "Unable to calculate FRATIO\n");
986 return -EINVAL;
987 }
988
989 factors->n = target / (Fref * factors->fratio);
990 Nmod = target % (Fref * factors->fratio);
991 } while (Nmod == 0);
992
993 /* Calculate fractional part - scale up so we can round. */
994 Kpart = FIXED_FLL_SIZE * (long long)Nmod;
995
996 do_div(Kpart, (Fref * factors->fratio));
997
998 K = Kpart & 0xFFFFFFFF;
999
1000 if ((K % 10) >= 5)
1001 K += 5;
1002
1003 /* Move down to proper range now rounding is done */
1004 factors->k = K / 10;
1005
1006 dev_dbg(wm8400->wm8400->dev,
1007 "FLL: Fref=%u Fout=%u N=%x K=%x, FRATIO=%x OUTDIV=%x\n",
1008 Fref, Fout,
1009 factors->n, factors->k, factors->fratio, factors->outdiv);
1010
1011 return 0;
1012 }
1013
1014 static int wm8400_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
1015 int source, unsigned int freq_in,
1016 unsigned int freq_out)
1017 {
1018 struct snd_soc_codec *codec = codec_dai->codec;
1019 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
1020 struct fll_factors factors;
1021 int ret;
1022 u16 reg;
1023
1024 if (freq_in == wm8400->fll_in && freq_out == wm8400->fll_out)
1025 return 0;
1026
1027 if (freq_out) {
1028 ret = fll_factors(wm8400, &factors, freq_in, freq_out);
1029 if (ret != 0)
1030 return ret;
1031 } else {
1032 /* Bodge GCC 4.4.0 uninitialised variable warning - it
1033 * doesn't seem capable of working out that we exit if
1034 * freq_out is 0 before any of the uses. */
1035 memset(&factors, 0, sizeof(factors));
1036 }
1037
1038 wm8400->fll_out = freq_out;
1039 wm8400->fll_in = freq_in;
1040
1041 /* We *must* disable the FLL before any changes */
1042 reg = wm8400_read(codec, WM8400_POWER_MANAGEMENT_2);
1043 reg &= ~WM8400_FLL_ENA;
1044 wm8400_write(codec, WM8400_POWER_MANAGEMENT_2, reg);
1045
1046 reg = wm8400_read(codec, WM8400_FLL_CONTROL_1);
1047 reg &= ~WM8400_FLL_OSC_ENA;
1048 wm8400_write(codec, WM8400_FLL_CONTROL_1, reg);
1049
1050 if (!freq_out)
1051 return 0;
1052
1053 reg &= ~(WM8400_FLL_REF_FREQ | WM8400_FLL_FRATIO_MASK);
1054 reg |= WM8400_FLL_FRAC | factors.fratio;
1055 reg |= factors.freq_ref << WM8400_FLL_REF_FREQ_SHIFT;
1056 wm8400_write(codec, WM8400_FLL_CONTROL_1, reg);
1057
1058 wm8400_write(codec, WM8400_FLL_CONTROL_2, factors.k);
1059 wm8400_write(codec, WM8400_FLL_CONTROL_3, factors.n);
1060
1061 reg = wm8400_read(codec, WM8400_FLL_CONTROL_4);
1062 reg &= WM8400_FLL_OUTDIV_MASK;
1063 reg |= factors.outdiv;
1064 wm8400_write(codec, WM8400_FLL_CONTROL_4, reg);
1065
1066 return 0;
1067 }
1068
1069 /*
1070 * Sets ADC and Voice DAC format.
1071 */
1072 static int wm8400_set_dai_fmt(struct snd_soc_dai *codec_dai,
1073 unsigned int fmt)
1074 {
1075 struct snd_soc_codec *codec = codec_dai->codec;
1076 u16 audio1, audio3;
1077
1078 audio1 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_1);
1079 audio3 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_3);
1080
1081 /* set master/slave audio interface */
1082 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1083 case SND_SOC_DAIFMT_CBS_CFS:
1084 audio3 &= ~WM8400_AIF_MSTR1;
1085 break;
1086 case SND_SOC_DAIFMT_CBM_CFM:
1087 audio3 |= WM8400_AIF_MSTR1;
1088 break;
1089 default:
1090 return -EINVAL;
1091 }
1092
1093 audio1 &= ~WM8400_AIF_FMT_MASK;
1094
1095 /* interface format */
1096 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1097 case SND_SOC_DAIFMT_I2S:
1098 audio1 |= WM8400_AIF_FMT_I2S;
1099 audio1 &= ~WM8400_AIF_LRCLK_INV;
1100 break;
1101 case SND_SOC_DAIFMT_RIGHT_J:
1102 audio1 |= WM8400_AIF_FMT_RIGHTJ;
1103 audio1 &= ~WM8400_AIF_LRCLK_INV;
1104 break;
1105 case SND_SOC_DAIFMT_LEFT_J:
1106 audio1 |= WM8400_AIF_FMT_LEFTJ;
1107 audio1 &= ~WM8400_AIF_LRCLK_INV;
1108 break;
1109 case SND_SOC_DAIFMT_DSP_A:
1110 audio1 |= WM8400_AIF_FMT_DSP;
1111 audio1 &= ~WM8400_AIF_LRCLK_INV;
1112 break;
1113 case SND_SOC_DAIFMT_DSP_B:
1114 audio1 |= WM8400_AIF_FMT_DSP | WM8400_AIF_LRCLK_INV;
1115 break;
1116 default:
1117 return -EINVAL;
1118 }
1119
1120 wm8400_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1121 wm8400_write(codec, WM8400_AUDIO_INTERFACE_3, audio3);
1122 return 0;
1123 }
1124
1125 static int wm8400_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
1126 int div_id, int div)
1127 {
1128 struct snd_soc_codec *codec = codec_dai->codec;
1129 u16 reg;
1130
1131 switch (div_id) {
1132 case WM8400_MCLK_DIV:
1133 reg = wm8400_read(codec, WM8400_CLOCKING_2) &
1134 ~WM8400_MCLK_DIV_MASK;
1135 wm8400_write(codec, WM8400_CLOCKING_2, reg | div);
1136 break;
1137 case WM8400_DACCLK_DIV:
1138 reg = wm8400_read(codec, WM8400_CLOCKING_2) &
1139 ~WM8400_DAC_CLKDIV_MASK;
1140 wm8400_write(codec, WM8400_CLOCKING_2, reg | div);
1141 break;
1142 case WM8400_ADCCLK_DIV:
1143 reg = wm8400_read(codec, WM8400_CLOCKING_2) &
1144 ~WM8400_ADC_CLKDIV_MASK;
1145 wm8400_write(codec, WM8400_CLOCKING_2, reg | div);
1146 break;
1147 case WM8400_BCLK_DIV:
1148 reg = wm8400_read(codec, WM8400_CLOCKING_1) &
1149 ~WM8400_BCLK_DIV_MASK;
1150 wm8400_write(codec, WM8400_CLOCKING_1, reg | div);
1151 break;
1152 default:
1153 return -EINVAL;
1154 }
1155
1156 return 0;
1157 }
1158
1159 /*
1160 * Set PCM DAI bit size and sample rate.
1161 */
1162 static int wm8400_hw_params(struct snd_pcm_substream *substream,
1163 struct snd_pcm_hw_params *params,
1164 struct snd_soc_dai *dai)
1165 {
1166 struct snd_soc_pcm_runtime *rtd = substream->private_data;
1167 struct snd_soc_codec *codec = rtd->codec;
1168 u16 audio1 = wm8400_read(codec, WM8400_AUDIO_INTERFACE_1);
1169
1170 audio1 &= ~WM8400_AIF_WL_MASK;
1171 /* bit size */
1172 switch (params_format(params)) {
1173 case SNDRV_PCM_FORMAT_S16_LE:
1174 break;
1175 case SNDRV_PCM_FORMAT_S20_3LE:
1176 audio1 |= WM8400_AIF_WL_20BITS;
1177 break;
1178 case SNDRV_PCM_FORMAT_S24_LE:
1179 audio1 |= WM8400_AIF_WL_24BITS;
1180 break;
1181 case SNDRV_PCM_FORMAT_S32_LE:
1182 audio1 |= WM8400_AIF_WL_32BITS;
1183 break;
1184 }
1185
1186 wm8400_write(codec, WM8400_AUDIO_INTERFACE_1, audio1);
1187 return 0;
1188 }
1189
1190 static int wm8400_mute(struct snd_soc_dai *dai, int mute)
1191 {
1192 struct snd_soc_codec *codec = dai->codec;
1193 u16 val = wm8400_read(codec, WM8400_DAC_CTRL) & ~WM8400_DAC_MUTE;
1194
1195 if (mute)
1196 wm8400_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1197 else
1198 wm8400_write(codec, WM8400_DAC_CTRL, val);
1199
1200 return 0;
1201 }
1202
1203 /* TODO: set bias for best performance at standby */
1204 static int wm8400_set_bias_level(struct snd_soc_codec *codec,
1205 enum snd_soc_bias_level level)
1206 {
1207 struct wm8400_priv *wm8400 = snd_soc_codec_get_drvdata(codec);
1208 u16 val;
1209 int ret;
1210
1211 switch (level) {
1212 case SND_SOC_BIAS_ON:
1213 break;
1214
1215 case SND_SOC_BIAS_PREPARE:
1216 /* VMID=2*50k */
1217 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1) &
1218 ~WM8400_VMID_MODE_MASK;
1219 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x2);
1220 break;
1221
1222 case SND_SOC_BIAS_STANDBY:
1223 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1224 ret = regulator_bulk_enable(ARRAY_SIZE(power),
1225 &power[0]);
1226 if (ret != 0) {
1227 dev_err(wm8400->wm8400->dev,
1228 "Failed to enable regulators: %d\n",
1229 ret);
1230 return ret;
1231 }
1232
1233 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1,
1234 WM8400_CODEC_ENA | WM8400_SYSCLK_ENA);
1235
1236 /* Enable POBCTRL, SOFT_ST, VMIDTOG and BUFDCOPEN */
1237 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1238 WM8400_BUFDCOPEN | WM8400_POBCTRL);
1239
1240 msleep(50);
1241
1242 /* Enable VREF & VMID at 2x50k */
1243 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1);
1244 val |= 0x2 | WM8400_VREF_ENA;
1245 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1246
1247 /* Enable BUFIOEN */
1248 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1249 WM8400_BUFDCOPEN | WM8400_POBCTRL |
1250 WM8400_BUFIOEN);
1251
1252 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1253 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_BUFIOEN);
1254 }
1255
1256 /* VMID=2*300k */
1257 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1) &
1258 ~WM8400_VMID_MODE_MASK;
1259 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val | 0x4);
1260 break;
1261
1262 case SND_SOC_BIAS_OFF:
1263 /* Enable POBCTRL and SOFT_ST */
1264 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1265 WM8400_POBCTRL | WM8400_BUFIOEN);
1266
1267 /* Enable POBCTRL, SOFT_ST and BUFDCOPEN */
1268 wm8400_write(codec, WM8400_ANTIPOP2, WM8400_SOFTST |
1269 WM8400_BUFDCOPEN | WM8400_POBCTRL |
1270 WM8400_BUFIOEN);
1271
1272 /* mute DAC */
1273 val = wm8400_read(codec, WM8400_DAC_CTRL);
1274 wm8400_write(codec, WM8400_DAC_CTRL, val | WM8400_DAC_MUTE);
1275
1276 /* Enable any disabled outputs */
1277 val = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1);
1278 val |= WM8400_SPK_ENA | WM8400_OUT3_ENA |
1279 WM8400_OUT4_ENA | WM8400_LOUT_ENA |
1280 WM8400_ROUT_ENA;
1281 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1282
1283 /* Disable VMID */
1284 val &= ~WM8400_VMID_MODE_MASK;
1285 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1286
1287 msleep(300);
1288
1289 /* Enable all output discharge bits */
1290 wm8400_write(codec, WM8400_ANTIPOP1, WM8400_DIS_LLINE |
1291 WM8400_DIS_RLINE | WM8400_DIS_OUT3 |
1292 WM8400_DIS_OUT4 | WM8400_DIS_LOUT |
1293 WM8400_DIS_ROUT);
1294
1295 /* Disable VREF */
1296 val &= ~WM8400_VREF_ENA;
1297 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, val);
1298
1299 /* disable POBCTRL, SOFT_ST and BUFDCOPEN */
1300 wm8400_write(codec, WM8400_ANTIPOP2, 0x0);
1301
1302 ret = regulator_bulk_disable(ARRAY_SIZE(power),
1303 &power[0]);
1304 if (ret != 0)
1305 return ret;
1306
1307 break;
1308 }
1309
1310 codec->dapm.bias_level = level;
1311 return 0;
1312 }
1313
1314 #define WM8400_RATES SNDRV_PCM_RATE_8000_96000
1315
1316 #define WM8400_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
1317 SNDRV_PCM_FMTBIT_S24_LE)
1318
1319 static struct snd_soc_dai_ops wm8400_dai_ops = {
1320 .hw_params = wm8400_hw_params,
1321 .digital_mute = wm8400_mute,
1322 .set_fmt = wm8400_set_dai_fmt,
1323 .set_clkdiv = wm8400_set_dai_clkdiv,
1324 .set_sysclk = wm8400_set_dai_sysclk,
1325 .set_pll = wm8400_set_dai_pll,
1326 };
1327
1328 /*
1329 * The WM8400 supports 2 different and mutually exclusive DAI
1330 * configurations.
1331 *
1332 * 1. ADC/DAC on Primary Interface
1333 * 2. ADC on Primary Interface/DAC on secondary
1334 */
1335 static struct snd_soc_dai_driver wm8400_dai = {
1336 /* ADC/DAC on primary */
1337 .name = "wm8400-hifi",
1338 .playback = {
1339 .stream_name = "Playback",
1340 .channels_min = 1,
1341 .channels_max = 2,
1342 .rates = WM8400_RATES,
1343 .formats = WM8400_FORMATS,
1344 },
1345 .capture = {
1346 .stream_name = "Capture",
1347 .channels_min = 1,
1348 .channels_max = 2,
1349 .rates = WM8400_RATES,
1350 .formats = WM8400_FORMATS,
1351 },
1352 .ops = &wm8400_dai_ops,
1353 };
1354
1355 static int wm8400_suspend(struct snd_soc_codec *codec, pm_message_t state)
1356 {
1357 wm8400_set_bias_level(codec, SND_SOC_BIAS_OFF);
1358
1359 return 0;
1360 }
1361
1362 static int wm8400_resume(struct snd_soc_codec *codec)
1363 {
1364 wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1365
1366 return 0;
1367 }
1368
1369 static void wm8400_probe_deferred(struct work_struct *work)
1370 {
1371 struct wm8400_priv *priv = container_of(work, struct wm8400_priv,
1372 work);
1373 struct snd_soc_codec *codec = priv->codec;
1374
1375 /* charge output caps */
1376 wm8400_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1377 }
1378
1379 static int wm8400_codec_probe(struct snd_soc_codec *codec)
1380 {
1381 struct wm8400 *wm8400 = dev_get_platdata(codec->dev);
1382 struct wm8400_priv *priv;
1383 int ret;
1384 u16 reg;
1385
1386 priv = kzalloc(sizeof(struct wm8400_priv), GFP_KERNEL);
1387 if (priv == NULL)
1388 return -ENOMEM;
1389
1390 snd_soc_codec_set_drvdata(codec, priv);
1391 codec->control_data = priv->wm8400 = wm8400;
1392 priv->codec = codec;
1393
1394 ret = regulator_bulk_get(wm8400->dev,
1395 ARRAY_SIZE(power), &power[0]);
1396 if (ret != 0) {
1397 dev_err(codec->dev, "Failed to get regulators: %d\n", ret);
1398 goto err;
1399 }
1400
1401 INIT_WORK(&priv->work, wm8400_probe_deferred);
1402
1403 wm8400_codec_reset(codec);
1404
1405 reg = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1);
1406 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1, reg | WM8400_CODEC_ENA);
1407
1408 /* Latch volume update bits */
1409 reg = wm8400_read(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME);
1410 wm8400_write(codec, WM8400_LEFT_LINE_INPUT_1_2_VOLUME,
1411 reg & WM8400_IPVU);
1412 reg = wm8400_read(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME);
1413 wm8400_write(codec, WM8400_RIGHT_LINE_INPUT_1_2_VOLUME,
1414 reg & WM8400_IPVU);
1415
1416 wm8400_write(codec, WM8400_LEFT_OUTPUT_VOLUME, 0x50 | (1<<8));
1417 wm8400_write(codec, WM8400_RIGHT_OUTPUT_VOLUME, 0x50 | (1<<8));
1418
1419 if (!schedule_work(&priv->work)) {
1420 ret = -EINVAL;
1421 goto err_regulator;
1422 }
1423 wm8400_add_controls(codec);
1424 wm8400_add_widgets(codec);
1425 return 0;
1426
1427 err_regulator:
1428 regulator_bulk_free(ARRAY_SIZE(power), power);
1429 err:
1430 kfree(priv);
1431 return ret;
1432 }
1433
1434 static int wm8400_codec_remove(struct snd_soc_codec *codec)
1435 {
1436 struct wm8400_priv *priv = snd_soc_codec_get_drvdata(codec);
1437 u16 reg;
1438
1439 reg = wm8400_read(codec, WM8400_POWER_MANAGEMENT_1);
1440 wm8400_write(codec, WM8400_POWER_MANAGEMENT_1,
1441 reg & (~WM8400_CODEC_ENA));
1442
1443 regulator_bulk_free(ARRAY_SIZE(power), power);
1444 kfree(priv);
1445
1446 return 0;
1447 }
1448
1449 static struct snd_soc_codec_driver soc_codec_dev_wm8400 = {
1450 .probe = wm8400_codec_probe,
1451 .remove = wm8400_codec_remove,
1452 .suspend = wm8400_suspend,
1453 .resume = wm8400_resume,
1454 .read = wm8400_read,
1455 .write = wm8400_write,
1456 .set_bias_level = wm8400_set_bias_level,
1457 };
1458
1459 static int __devinit wm8400_probe(struct platform_device *pdev)
1460 {
1461 return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8400,
1462 &wm8400_dai, 1);
1463 }
1464
1465 static int __devexit wm8400_remove(struct platform_device *pdev)
1466 {
1467 snd_soc_unregister_codec(&pdev->dev);
1468 return 0;
1469 }
1470
1471 static struct platform_driver wm8400_codec_driver = {
1472 .driver = {
1473 .name = "wm8400-codec",
1474 .owner = THIS_MODULE,
1475 },
1476 .probe = wm8400_probe,
1477 .remove = __devexit_p(wm8400_remove),
1478 };
1479
1480 static __init int wm8400_init(void)
1481 {
1482 return platform_driver_register(&wm8400_codec_driver);
1483 }
1484 module_init(wm8400_init);
1485
1486 static __exit void wm8400_exit(void)
1487 {
1488 platform_driver_unregister(&wm8400_codec_driver);
1489 }
1490 module_exit(wm8400_exit);
1491
1492 MODULE_DESCRIPTION("ASoC WM8400 driver");
1493 MODULE_AUTHOR("Mark Brown");
1494 MODULE_LICENSE("GPL");
1495 MODULE_ALIAS("platform:wm8400-codec");
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