xen: cleancache shim to Xen Transcendent Memory
[linux-2.6/next.git] / arch / ia64 / kernel / cyclone.c
blob1b811c61bdc618107d05bf4bc10ebf0067b86df8
1 #include <linux/module.h>
2 #include <linux/smp.h>
3 #include <linux/time.h>
4 #include <linux/errno.h>
5 #include <linux/timex.h>
6 #include <linux/clocksource.h>
7 #include <asm/io.h>
9 /* IBM Summit (EXA) Cyclone counter code*/
10 #define CYCLONE_CBAR_ADDR 0xFEB00CD0
11 #define CYCLONE_PMCC_OFFSET 0x51A0
12 #define CYCLONE_MPMC_OFFSET 0x51D0
13 #define CYCLONE_MPCS_OFFSET 0x51A8
14 #define CYCLONE_TIMER_FREQ 100000000
16 int use_cyclone;
17 void __init cyclone_setup(void)
19 use_cyclone = 1;
22 static void __iomem *cyclone_mc;
24 static cycle_t read_cyclone(struct clocksource *cs)
26 return (cycle_t)readq((void __iomem *)cyclone_mc);
29 static struct clocksource clocksource_cyclone = {
30 .name = "cyclone",
31 .rating = 300,
32 .read = read_cyclone,
33 .mask = (1LL << 40) - 1,
34 .mult = 0, /*to be calculated*/
35 .shift = 16,
36 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
39 int __init init_cyclone_clock(void)
41 u64 __iomem *reg;
42 u64 base; /* saved cyclone base address */
43 u64 offset; /* offset from pageaddr to cyclone_timer register */
44 int i;
45 u32 __iomem *cyclone_timer; /* Cyclone MPMC0 register */
47 if (!use_cyclone)
48 return 0;
50 printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
52 /* find base address */
53 offset = (CYCLONE_CBAR_ADDR);
54 reg = ioremap_nocache(offset, sizeof(u64));
55 if(!reg){
56 printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
57 " register.\n");
58 use_cyclone = 0;
59 return -ENODEV;
61 base = readq(reg);
62 iounmap(reg);
63 if(!base){
64 printk(KERN_ERR "Summit chipset: Could not find valid CBAR"
65 " value.\n");
66 use_cyclone = 0;
67 return -ENODEV;
70 /* setup PMCC */
71 offset = (base + CYCLONE_PMCC_OFFSET);
72 reg = ioremap_nocache(offset, sizeof(u64));
73 if(!reg){
74 printk(KERN_ERR "Summit chipset: Could not find valid PMCC"
75 " register.\n");
76 use_cyclone = 0;
77 return -ENODEV;
79 writel(0x00000001,reg);
80 iounmap(reg);
82 /* setup MPCS */
83 offset = (base + CYCLONE_MPCS_OFFSET);
84 reg = ioremap_nocache(offset, sizeof(u64));
85 if(!reg){
86 printk(KERN_ERR "Summit chipset: Could not find valid MPCS"
87 " register.\n");
88 use_cyclone = 0;
89 return -ENODEV;
91 writel(0x00000001,reg);
92 iounmap(reg);
94 /* map in cyclone_timer */
95 offset = (base + CYCLONE_MPMC_OFFSET);
96 cyclone_timer = ioremap_nocache(offset, sizeof(u32));
97 if(!cyclone_timer){
98 printk(KERN_ERR "Summit chipset: Could not find valid MPMC"
99 " register.\n");
100 use_cyclone = 0;
101 return -ENODEV;
104 /*quick test to make sure its ticking*/
105 for(i=0; i<3; i++){
106 u32 old = readl(cyclone_timer);
107 int stall = 100;
108 while(stall--) barrier();
109 if(readl(cyclone_timer) == old){
110 printk(KERN_ERR "Summit chipset: Counter not counting!"
111 " DISABLED\n");
112 iounmap(cyclone_timer);
113 cyclone_timer = NULL;
114 use_cyclone = 0;
115 return -ENODEV;
118 /* initialize last tick */
119 cyclone_mc = cyclone_timer;
120 clocksource_cyclone.fsys_mmio = cyclone_timer;
121 clocksource_cyclone.mult = clocksource_hz2mult(CYCLONE_TIMER_FREQ,
122 clocksource_cyclone.shift);
123 clocksource_register(&clocksource_cyclone);
125 return 0;
128 __initcall(init_cyclone_clock);