2 * Renesas Technology Corp. R0P7785LC0011RL Support.
4 * Copyright (C) 2008 Yoshihiro Shimoda
5 * Copyright (C) 2009 Paul Mundt
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
11 #include <linux/init.h>
12 #include <linux/platform_device.h>
13 #include <linux/sm501.h>
14 #include <linux/sm501-regs.h>
16 #include <linux/mtd/physmap.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/i2c.h>
20 #include <linux/i2c-pca-platform.h>
21 #include <linux/i2c-algo-pca.h>
22 #include <linux/usb/r8a66597.h>
23 #include <linux/irq.h>
25 #include <linux/clk.h>
26 #include <linux/errno.h>
27 #include <mach/sh7785lcr.h>
28 #include <cpu/sh7785.h>
29 #include <asm/heartbeat.h>
30 #include <asm/clock.h>
33 * NOTE: This board has 2 physical memory maps.
34 * Please look at include/asm-sh/sh7785lcr.h or hardware manual.
36 static struct resource heartbeat_resource
= {
39 .flags
= IORESOURCE_MEM
| IORESOURCE_MEM_8BIT
,
42 static struct platform_device heartbeat_device
= {
46 .resource
= &heartbeat_resource
,
49 static struct mtd_partition nor_flash_partitions
[] = {
57 .offset
= MTDPART_OFS_APPEND
,
62 .offset
= MTDPART_OFS_APPEND
,
63 .size
= 4 * 1024 * 1024,
67 .offset
= MTDPART_OFS_APPEND
,
68 .size
= MTDPART_SIZ_FULL
,
72 static struct physmap_flash_data nor_flash_data
= {
74 .parts
= nor_flash_partitions
,
75 .nr_parts
= ARRAY_SIZE(nor_flash_partitions
),
78 static struct resource nor_flash_resources
[] = {
80 .start
= NOR_FLASH_ADDR
,
81 .end
= NOR_FLASH_ADDR
+ NOR_FLASH_SIZE
- 1,
82 .flags
= IORESOURCE_MEM
,
86 static struct platform_device nor_flash_device
= {
87 .name
= "physmap-flash",
89 .platform_data
= &nor_flash_data
,
91 .num_resources
= ARRAY_SIZE(nor_flash_resources
),
92 .resource
= nor_flash_resources
,
95 static struct r8a66597_platdata r8a66597_data
= {
96 .xtal
= R8A66597_PLATDATA_XTAL_12MHZ
,
100 static struct resource r8a66597_usb_host_resources
[] = {
102 .start
= R8A66597_ADDR
,
103 .end
= R8A66597_ADDR
+ R8A66597_SIZE
- 1,
104 .flags
= IORESOURCE_MEM
,
109 .flags
= IORESOURCE_IRQ
| IRQF_TRIGGER_LOW
,
113 static struct platform_device r8a66597_usb_host_device
= {
114 .name
= "r8a66597_hcd",
118 .coherent_dma_mask
= 0xffffffff,
119 .platform_data
= &r8a66597_data
,
121 .num_resources
= ARRAY_SIZE(r8a66597_usb_host_resources
),
122 .resource
= r8a66597_usb_host_resources
,
125 static struct resource sm501_resources
[] = {
127 .start
= SM107_MEM_ADDR
,
128 .end
= SM107_MEM_ADDR
+ SM107_MEM_SIZE
- 1,
129 .flags
= IORESOURCE_MEM
,
132 .start
= SM107_REG_ADDR
,
133 .end
= SM107_REG_ADDR
+ SM107_REG_SIZE
- 1,
134 .flags
= IORESOURCE_MEM
,
138 .flags
= IORESOURCE_IRQ
,
142 static struct fb_videomode sm501_default_mode_crt
= {
143 .pixclock
= 35714, /* 28MHz */
152 .sync
= FB_SYNC_HOR_HIGH_ACT
| FB_SYNC_VERT_HIGH_ACT
,
155 static struct fb_videomode sm501_default_mode_pnl
= {
156 .pixclock
= 40000, /* 25MHz */
168 static struct sm501_platdata_fbsub sm501_pdata_fbsub_pnl
= {
170 .def_mode
= &sm501_default_mode_pnl
,
171 .flags
= SM501FB_FLAG_USE_INIT_MODE
|
172 SM501FB_FLAG_USE_HWCURSOR
|
173 SM501FB_FLAG_USE_HWACCEL
|
174 SM501FB_FLAG_DISABLE_AT_EXIT
|
175 SM501FB_FLAG_PANEL_NO_VBIASEN
,
178 static struct sm501_platdata_fbsub sm501_pdata_fbsub_crt
= {
180 .def_mode
= &sm501_default_mode_crt
,
181 .flags
= SM501FB_FLAG_USE_INIT_MODE
|
182 SM501FB_FLAG_USE_HWCURSOR
|
183 SM501FB_FLAG_USE_HWACCEL
|
184 SM501FB_FLAG_DISABLE_AT_EXIT
,
187 static struct sm501_platdata_fb sm501_fb_pdata
= {
188 .fb_route
= SM501_FB_OWN
,
189 .fb_crt
= &sm501_pdata_fbsub_crt
,
190 .fb_pnl
= &sm501_pdata_fbsub_pnl
,
193 static struct sm501_initdata sm501_initdata
= {
199 .mclk
= 84 * 1000000,
200 .m1xclk
= 112 * 1000000,
203 static struct sm501_platdata sm501_platform_data
= {
204 .init
= &sm501_initdata
,
205 .fb
= &sm501_fb_pdata
,
208 static struct platform_device sm501_device
= {
212 .platform_data
= &sm501_platform_data
,
214 .num_resources
= ARRAY_SIZE(sm501_resources
),
215 .resource
= sm501_resources
,
218 static struct resource i2c_proto_resources
[] = {
220 .start
= PCA9564_PROTO_32BIT_ADDR
,
221 .end
= PCA9564_PROTO_32BIT_ADDR
+ PCA9564_SIZE
- 1,
222 .flags
= IORESOURCE_MEM
| IORESOURCE_MEM_8BIT
,
227 .flags
= IORESOURCE_IRQ
,
231 static struct resource i2c_resources
[] = {
233 .start
= PCA9564_ADDR
,
234 .end
= PCA9564_ADDR
+ PCA9564_SIZE
- 1,
235 .flags
= IORESOURCE_MEM
| IORESOURCE_MEM_8BIT
,
240 .flags
= IORESOURCE_IRQ
,
244 static struct i2c_pca9564_pf_platform_data i2c_platform_data
= {
246 .i2c_clock_speed
= I2C_PCA_CON_330kHz
,
250 static struct platform_device i2c_device
= {
251 .name
= "i2c-pca-platform",
254 .platform_data
= &i2c_platform_data
,
256 .num_resources
= ARRAY_SIZE(i2c_resources
),
257 .resource
= i2c_resources
,
260 static struct platform_device
*sh7785lcr_devices
[] __initdata
= {
263 &r8a66597_usb_host_device
,
268 static struct i2c_board_info __initdata sh7785lcr_i2c_devices
[] = {
270 I2C_BOARD_INFO("r2025sd", 0x32),
274 static int __init
sh7785lcr_devices_setup(void)
276 i2c_register_board_info(0, sh7785lcr_i2c_devices
,
277 ARRAY_SIZE(sh7785lcr_i2c_devices
));
279 if (mach_is_sh7785lcr_pt()) {
280 i2c_device
.resource
= i2c_proto_resources
;
281 i2c_device
.num_resources
= ARRAY_SIZE(i2c_proto_resources
);
284 return platform_add_devices(sh7785lcr_devices
,
285 ARRAY_SIZE(sh7785lcr_devices
));
287 device_initcall(sh7785lcr_devices_setup
);
289 /* Initialize IRQ setting */
290 void __init
init_sh7785lcr_IRQ(void)
292 plat_irq_setup_pins(IRQ_MODE_IRQ7654
);
293 plat_irq_setup_pins(IRQ_MODE_IRQ3210
);
296 static int sh7785lcr_clk_init(void)
301 clk
= clk_get(NULL
, "extal");
302 if (!clk
|| IS_ERR(clk
))
304 ret
= clk_set_rate(clk
, 33333333);
310 static void sh7785lcr_power_off(void)
314 p
= ioremap(PLD_POFCR
, PLD_POFCR
+ 1);
316 printk(KERN_ERR
"%s: ioremap error.\n", __func__
);
326 /* Initialize the board */
327 static void __init
sh7785lcr_setup(char **cmdline_p
)
329 void __iomem
*sm501_reg
;
331 printk(KERN_INFO
"Renesas Technology Corp. R0P7785LC0011RL support.\n");
333 pm_power_off
= sh7785lcr_power_off
;
335 /* sm501 DRAM configuration */
336 sm501_reg
= ioremap_nocache(SM107_REG_ADDR
, SM501_DRAM_CONTROL
);
338 printk(KERN_ERR
"%s: ioremap error.\n", __func__
);
342 writel(0x000307c2, sm501_reg
+ SM501_DRAM_CONTROL
);
346 /* Return the board specific boot mode pin configuration */
347 static int sh7785lcr_mode_pins(void)
351 /* These are the factory default settings of S1 and S2.
352 * If you change these dip switches then you will need to
353 * adjust the values below as well.
355 value
|= MODE_PIN4
; /* Clock Mode 16 */
356 value
|= MODE_PIN5
; /* 32-bit Area0 bus width */
357 value
|= MODE_PIN6
; /* 32-bit Area0 bus width */
358 value
|= MODE_PIN7
; /* Area 0 SRAM interface [fixed] */
359 value
|= MODE_PIN8
; /* Little Endian */
360 value
|= MODE_PIN9
; /* Master Mode */
361 value
|= MODE_PIN14
; /* No PLL step-up */
369 static struct sh_machine_vector mv_sh7785lcr __initmv
= {
370 .mv_name
= "SH7785LCR",
371 .mv_setup
= sh7785lcr_setup
,
372 .mv_clk_init
= sh7785lcr_clk_init
,
373 .mv_init_irq
= init_sh7785lcr_IRQ
,
374 .mv_mode_pins
= sh7785lcr_mode_pins
,