2 * Microchip ENC28J60 ethernet driver (MAC + PHY)
4 * Copyright (C) 2007 Eurek srl
5 * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
6 * based on enc28j60.c written by David Anders for 2.4 kernel version
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/fcntl.h>
20 #include <linux/interrupt.h>
21 #include <linux/slab.h>
22 #include <linux/string.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/ethtool.h>
28 #include <linux/tcp.h>
29 #include <linux/skbuff.h>
30 #include <linux/delay.h>
31 #include <linux/spi/spi.h>
33 #include "enc28j60_hw.h"
35 #define DRV_NAME "enc28j60"
36 #define DRV_VERSION "1.01"
40 #define ENC28J60_MSG_DEFAULT \
41 (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
43 /* Buffer size required for the largest SPI transfer (i.e., reading a
45 #define SPI_TRANSFER_BUF_LEN (4 + MAX_FRAMELEN)
47 #define TX_TIMEOUT (4 * HZ)
49 /* Max TX retries in case of collision as suggested by errata datasheet */
50 #define MAX_TX_RETRYCOUNT 16
58 /* Driver local data */
60 struct net_device
*netdev
;
61 struct spi_device
*spi
;
63 struct sk_buff
*tx_skb
;
64 struct work_struct tx_work
;
65 struct work_struct irq_work
;
66 struct work_struct setrx_work
;
67 struct work_struct restart_work
;
68 u8 bank
; /* current register bank selected */
69 u16 next_pk_ptr
; /* next packet pointer within FIFO */
70 u16 max_pk_counter
; /* statistics: max packet counter */
76 u8 spi_transfer_buf
[SPI_TRANSFER_BUF_LEN
];
79 /* use ethtool to change the level for any given device */
86 * wait for the SPI transfer and copy received data to destination
89 spi_read_buf(struct enc28j60_net
*priv
, int len
, u8
*data
)
91 u8
*rx_buf
= priv
->spi_transfer_buf
+ 4;
92 u8
*tx_buf
= priv
->spi_transfer_buf
;
93 struct spi_transfer t
= {
96 .len
= SPI_OPLEN
+ len
,
98 struct spi_message msg
;
101 tx_buf
[0] = ENC28J60_READ_BUF_MEM
;
102 tx_buf
[1] = tx_buf
[2] = tx_buf
[3] = 0; /* don't care */
104 spi_message_init(&msg
);
105 spi_message_add_tail(&t
, &msg
);
106 ret
= spi_sync(priv
->spi
, &msg
);
108 memcpy(data
, &rx_buf
[SPI_OPLEN
], len
);
111 if (ret
&& netif_msg_drv(priv
))
112 printk(KERN_DEBUG DRV_NAME
": %s() failed: ret = %d\n",
121 static int spi_write_buf(struct enc28j60_net
*priv
, int len
,
126 if (len
> SPI_TRANSFER_BUF_LEN
- 1 || len
<= 0)
129 priv
->spi_transfer_buf
[0] = ENC28J60_WRITE_BUF_MEM
;
130 memcpy(&priv
->spi_transfer_buf
[1], data
, len
);
131 ret
= spi_write(priv
->spi
, priv
->spi_transfer_buf
, len
+ 1);
132 if (ret
&& netif_msg_drv(priv
))
133 printk(KERN_DEBUG DRV_NAME
": %s() failed: ret = %d\n",
140 * basic SPI read operation
142 static u8
spi_read_op(struct enc28j60_net
*priv
, u8 op
,
149 int slen
= SPI_OPLEN
;
151 /* do dummy read if needed */
152 if (addr
& SPRD_MASK
)
155 tx_buf
[0] = op
| (addr
& ADDR_MASK
);
156 ret
= spi_write_then_read(priv
->spi
, tx_buf
, 1, rx_buf
, slen
);
158 printk(KERN_DEBUG DRV_NAME
": %s() failed: ret = %d\n",
161 val
= rx_buf
[slen
- 1];
167 * basic SPI write operation
169 static int spi_write_op(struct enc28j60_net
*priv
, u8 op
,
174 priv
->spi_transfer_buf
[0] = op
| (addr
& ADDR_MASK
);
175 priv
->spi_transfer_buf
[1] = val
;
176 ret
= spi_write(priv
->spi
, priv
->spi_transfer_buf
, 2);
177 if (ret
&& netif_msg_drv(priv
))
178 printk(KERN_DEBUG DRV_NAME
": %s() failed: ret = %d\n",
183 static void enc28j60_soft_reset(struct enc28j60_net
*priv
)
185 if (netif_msg_hw(priv
))
186 printk(KERN_DEBUG DRV_NAME
": %s() enter\n", __func__
);
188 spi_write_op(priv
, ENC28J60_SOFT_RESET
, 0, ENC28J60_SOFT_RESET
);
189 /* Errata workaround #1, CLKRDY check is unreliable,
190 * delay at least 1 mS instead */
195 * select the current register bank if necessary
197 static void enc28j60_set_bank(struct enc28j60_net
*priv
, u8 addr
)
199 u8 b
= (addr
& BANK_MASK
) >> 5;
201 /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
202 * are present in all banks, no need to switch bank
204 if (addr
>= EIE
&& addr
<= ECON1
)
207 /* Clear or set each bank selection bit as needed */
208 if ((b
& ECON1_BSEL0
) != (priv
->bank
& ECON1_BSEL0
)) {
210 spi_write_op(priv
, ENC28J60_BIT_FIELD_SET
, ECON1
,
213 spi_write_op(priv
, ENC28J60_BIT_FIELD_CLR
, ECON1
,
216 if ((b
& ECON1_BSEL1
) != (priv
->bank
& ECON1_BSEL1
)) {
218 spi_write_op(priv
, ENC28J60_BIT_FIELD_SET
, ECON1
,
221 spi_write_op(priv
, ENC28J60_BIT_FIELD_CLR
, ECON1
,
228 * Register access routines through the SPI bus.
229 * Every register access comes in two flavours:
230 * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
231 * atomically more than one register
232 * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
234 * Some registers can be accessed through the bit field clear and
235 * bit field set to avoid a read modify write cycle.
239 * Register bit field Set
241 static void nolock_reg_bfset(struct enc28j60_net
*priv
,
244 enc28j60_set_bank(priv
, addr
);
245 spi_write_op(priv
, ENC28J60_BIT_FIELD_SET
, addr
, mask
);
248 static void locked_reg_bfset(struct enc28j60_net
*priv
,
251 mutex_lock(&priv
->lock
);
252 nolock_reg_bfset(priv
, addr
, mask
);
253 mutex_unlock(&priv
->lock
);
257 * Register bit field Clear
259 static void nolock_reg_bfclr(struct enc28j60_net
*priv
,
262 enc28j60_set_bank(priv
, addr
);
263 spi_write_op(priv
, ENC28J60_BIT_FIELD_CLR
, addr
, mask
);
266 static void locked_reg_bfclr(struct enc28j60_net
*priv
,
269 mutex_lock(&priv
->lock
);
270 nolock_reg_bfclr(priv
, addr
, mask
);
271 mutex_unlock(&priv
->lock
);
277 static int nolock_regb_read(struct enc28j60_net
*priv
,
280 enc28j60_set_bank(priv
, address
);
281 return spi_read_op(priv
, ENC28J60_READ_CTRL_REG
, address
);
284 static int locked_regb_read(struct enc28j60_net
*priv
,
289 mutex_lock(&priv
->lock
);
290 ret
= nolock_regb_read(priv
, address
);
291 mutex_unlock(&priv
->lock
);
299 static int nolock_regw_read(struct enc28j60_net
*priv
,
304 enc28j60_set_bank(priv
, address
);
305 rl
= spi_read_op(priv
, ENC28J60_READ_CTRL_REG
, address
);
306 rh
= spi_read_op(priv
, ENC28J60_READ_CTRL_REG
, address
+ 1);
308 return (rh
<< 8) | rl
;
311 static int locked_regw_read(struct enc28j60_net
*priv
,
316 mutex_lock(&priv
->lock
);
317 ret
= nolock_regw_read(priv
, address
);
318 mutex_unlock(&priv
->lock
);
324 * Register byte write
326 static void nolock_regb_write(struct enc28j60_net
*priv
,
329 enc28j60_set_bank(priv
, address
);
330 spi_write_op(priv
, ENC28J60_WRITE_CTRL_REG
, address
, data
);
333 static void locked_regb_write(struct enc28j60_net
*priv
,
336 mutex_lock(&priv
->lock
);
337 nolock_regb_write(priv
, address
, data
);
338 mutex_unlock(&priv
->lock
);
342 * Register word write
344 static void nolock_regw_write(struct enc28j60_net
*priv
,
345 u8 address
, u16 data
)
347 enc28j60_set_bank(priv
, address
);
348 spi_write_op(priv
, ENC28J60_WRITE_CTRL_REG
, address
, (u8
) data
);
349 spi_write_op(priv
, ENC28J60_WRITE_CTRL_REG
, address
+ 1,
353 static void locked_regw_write(struct enc28j60_net
*priv
,
354 u8 address
, u16 data
)
356 mutex_lock(&priv
->lock
);
357 nolock_regw_write(priv
, address
, data
);
358 mutex_unlock(&priv
->lock
);
363 * Select the starting address and execute a SPI buffer read
365 static void enc28j60_mem_read(struct enc28j60_net
*priv
,
366 u16 addr
, int len
, u8
*data
)
368 mutex_lock(&priv
->lock
);
369 nolock_regw_write(priv
, ERDPTL
, addr
);
370 #ifdef CONFIG_ENC28J60_WRITEVERIFY
371 if (netif_msg_drv(priv
)) {
373 reg
= nolock_regw_read(priv
, ERDPTL
);
375 printk(KERN_DEBUG DRV_NAME
": %s() error writing ERDPT "
376 "(0x%04x - 0x%04x)\n", __func__
, reg
, addr
);
379 spi_read_buf(priv
, len
, data
);
380 mutex_unlock(&priv
->lock
);
384 * Write packet to enc28j60 TX buffer memory
387 enc28j60_packet_write(struct enc28j60_net
*priv
, int len
, const u8
*data
)
389 mutex_lock(&priv
->lock
);
390 /* Set the write pointer to start of transmit buffer area */
391 nolock_regw_write(priv
, EWRPTL
, TXSTART_INIT
);
392 #ifdef CONFIG_ENC28J60_WRITEVERIFY
393 if (netif_msg_drv(priv
)) {
395 reg
= nolock_regw_read(priv
, EWRPTL
);
396 if (reg
!= TXSTART_INIT
)
397 printk(KERN_DEBUG DRV_NAME
398 ": %s() ERWPT:0x%04x != 0x%04x\n",
399 __func__
, reg
, TXSTART_INIT
);
402 /* Set the TXND pointer to correspond to the packet size given */
403 nolock_regw_write(priv
, ETXNDL
, TXSTART_INIT
+ len
);
404 /* write per-packet control byte */
405 spi_write_op(priv
, ENC28J60_WRITE_BUF_MEM
, 0, 0x00);
406 if (netif_msg_hw(priv
))
407 printk(KERN_DEBUG DRV_NAME
408 ": %s() after control byte ERWPT:0x%04x\n",
409 __func__
, nolock_regw_read(priv
, EWRPTL
));
410 /* copy the packet into the transmit buffer */
411 spi_write_buf(priv
, len
, data
);
412 if (netif_msg_hw(priv
))
413 printk(KERN_DEBUG DRV_NAME
414 ": %s() after write packet ERWPT:0x%04x, len=%d\n",
415 __func__
, nolock_regw_read(priv
, EWRPTL
), len
);
416 mutex_unlock(&priv
->lock
);
419 static unsigned long msec20_to_jiffies
;
421 static int poll_ready(struct enc28j60_net
*priv
, u8 reg
, u8 mask
, u8 val
)
423 unsigned long timeout
= jiffies
+ msec20_to_jiffies
;
425 /* 20 msec timeout read */
426 while ((nolock_regb_read(priv
, reg
) & mask
) != val
) {
427 if (time_after(jiffies
, timeout
)) {
428 if (netif_msg_drv(priv
))
429 dev_dbg(&priv
->spi
->dev
,
430 "reg %02x ready timeout!\n", reg
);
439 * Wait until the PHY operation is complete.
441 static int wait_phy_ready(struct enc28j60_net
*priv
)
443 return poll_ready(priv
, MISTAT
, MISTAT_BUSY
, 0) ? 0 : 1;
448 * PHY registers are not accessed directly, but through the MII
450 static u16
enc28j60_phy_read(struct enc28j60_net
*priv
, u8 address
)
454 mutex_lock(&priv
->lock
);
455 /* set the PHY register address */
456 nolock_regb_write(priv
, MIREGADR
, address
);
457 /* start the register read operation */
458 nolock_regb_write(priv
, MICMD
, MICMD_MIIRD
);
459 /* wait until the PHY read completes */
460 wait_phy_ready(priv
);
462 nolock_regb_write(priv
, MICMD
, 0x00);
463 /* return the data */
464 ret
= nolock_regw_read(priv
, MIRDL
);
465 mutex_unlock(&priv
->lock
);
470 static int enc28j60_phy_write(struct enc28j60_net
*priv
, u8 address
, u16 data
)
474 mutex_lock(&priv
->lock
);
475 /* set the PHY register address */
476 nolock_regb_write(priv
, MIREGADR
, address
);
477 /* write the PHY data */
478 nolock_regw_write(priv
, MIWRL
, data
);
479 /* wait until the PHY write completes and return */
480 ret
= wait_phy_ready(priv
);
481 mutex_unlock(&priv
->lock
);
487 * Program the hardware MAC address from dev->dev_addr.
489 static int enc28j60_set_hw_macaddr(struct net_device
*ndev
)
492 struct enc28j60_net
*priv
= netdev_priv(ndev
);
494 mutex_lock(&priv
->lock
);
495 if (!priv
->hw_enable
) {
496 if (netif_msg_drv(priv
))
497 printk(KERN_INFO DRV_NAME
498 ": %s: Setting MAC address to %pM\n",
499 ndev
->name
, ndev
->dev_addr
);
500 /* NOTE: MAC address in ENC28J60 is byte-backward */
501 nolock_regb_write(priv
, MAADR5
, ndev
->dev_addr
[0]);
502 nolock_regb_write(priv
, MAADR4
, ndev
->dev_addr
[1]);
503 nolock_regb_write(priv
, MAADR3
, ndev
->dev_addr
[2]);
504 nolock_regb_write(priv
, MAADR2
, ndev
->dev_addr
[3]);
505 nolock_regb_write(priv
, MAADR1
, ndev
->dev_addr
[4]);
506 nolock_regb_write(priv
, MAADR0
, ndev
->dev_addr
[5]);
509 if (netif_msg_drv(priv
))
510 printk(KERN_DEBUG DRV_NAME
511 ": %s() Hardware must be disabled to set "
512 "Mac address\n", __func__
);
515 mutex_unlock(&priv
->lock
);
520 * Store the new hardware address in dev->dev_addr, and update the MAC.
522 static int enc28j60_set_mac_address(struct net_device
*dev
, void *addr
)
524 struct sockaddr
*address
= addr
;
526 if (netif_running(dev
))
528 if (!is_valid_ether_addr(address
->sa_data
))
529 return -EADDRNOTAVAIL
;
531 memcpy(dev
->dev_addr
, address
->sa_data
, dev
->addr_len
);
532 return enc28j60_set_hw_macaddr(dev
);
536 * Debug routine to dump useful register contents
538 static void enc28j60_dump_regs(struct enc28j60_net
*priv
, const char *msg
)
540 mutex_lock(&priv
->lock
);
541 printk(KERN_DEBUG DRV_NAME
" %s\n"
543 "Cntrl: ECON1 ECON2 ESTAT EIR EIE\n"
544 " 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n"
545 "MAC : MACON1 MACON3 MACON4\n"
546 " 0x%02x 0x%02x 0x%02x\n"
547 "Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
548 " 0x%04x 0x%04x 0x%04x 0x%04x "
549 "0x%02x 0x%02x 0x%04x\n"
550 "Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n"
551 " 0x%04x 0x%04x 0x%02x 0x%02x 0x%02x\n",
552 msg
, nolock_regb_read(priv
, EREVID
),
553 nolock_regb_read(priv
, ECON1
), nolock_regb_read(priv
, ECON2
),
554 nolock_regb_read(priv
, ESTAT
), nolock_regb_read(priv
, EIR
),
555 nolock_regb_read(priv
, EIE
), nolock_regb_read(priv
, MACON1
),
556 nolock_regb_read(priv
, MACON3
), nolock_regb_read(priv
, MACON4
),
557 nolock_regw_read(priv
, ERXSTL
), nolock_regw_read(priv
, ERXNDL
),
558 nolock_regw_read(priv
, ERXWRPTL
),
559 nolock_regw_read(priv
, ERXRDPTL
),
560 nolock_regb_read(priv
, ERXFCON
),
561 nolock_regb_read(priv
, EPKTCNT
),
562 nolock_regw_read(priv
, MAMXFLL
), nolock_regw_read(priv
, ETXSTL
),
563 nolock_regw_read(priv
, ETXNDL
),
564 nolock_regb_read(priv
, MACLCON1
),
565 nolock_regb_read(priv
, MACLCON2
),
566 nolock_regb_read(priv
, MAPHSUP
));
567 mutex_unlock(&priv
->lock
);
571 * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
573 static u16
erxrdpt_workaround(u16 next_packet_ptr
, u16 start
, u16 end
)
577 if ((next_packet_ptr
- 1 < start
) || (next_packet_ptr
- 1 > end
))
580 erxrdpt
= next_packet_ptr
- 1;
586 * Calculate wrap around when reading beyond the end of the RX buffer
588 static u16
rx_packet_start(u16 ptr
)
590 if (ptr
+ RSV_SIZE
> RXEND_INIT
)
591 return (ptr
+ RSV_SIZE
) - (RXEND_INIT
- RXSTART_INIT
+ 1);
593 return ptr
+ RSV_SIZE
;
596 static void nolock_rxfifo_init(struct enc28j60_net
*priv
, u16 start
, u16 end
)
600 if (start
> 0x1FFF || end
> 0x1FFF || start
> end
) {
601 if (netif_msg_drv(priv
))
602 printk(KERN_ERR DRV_NAME
": %s(%d, %d) RXFIFO "
603 "bad parameters!\n", __func__
, start
, end
);
606 /* set receive buffer start + end */
607 priv
->next_pk_ptr
= start
;
608 nolock_regw_write(priv
, ERXSTL
, start
);
609 erxrdpt
= erxrdpt_workaround(priv
->next_pk_ptr
, start
, end
);
610 nolock_regw_write(priv
, ERXRDPTL
, erxrdpt
);
611 nolock_regw_write(priv
, ERXNDL
, end
);
614 static void nolock_txfifo_init(struct enc28j60_net
*priv
, u16 start
, u16 end
)
616 if (start
> 0x1FFF || end
> 0x1FFF || start
> end
) {
617 if (netif_msg_drv(priv
))
618 printk(KERN_ERR DRV_NAME
": %s(%d, %d) TXFIFO "
619 "bad parameters!\n", __func__
, start
, end
);
622 /* set transmit buffer start + end */
623 nolock_regw_write(priv
, ETXSTL
, start
);
624 nolock_regw_write(priv
, ETXNDL
, end
);
628 * Low power mode shrinks power consumption about 100x, so we'd like
629 * the chip to be in that mode whenever it's inactive. (However, we
630 * can't stay in lowpower mode during suspend with WOL active.)
632 static void enc28j60_lowpower(struct enc28j60_net
*priv
, bool is_low
)
634 if (netif_msg_drv(priv
))
635 dev_dbg(&priv
->spi
->dev
, "%s power...\n",
636 is_low
? "low" : "high");
638 mutex_lock(&priv
->lock
);
640 nolock_reg_bfclr(priv
, ECON1
, ECON1_RXEN
);
641 poll_ready(priv
, ESTAT
, ESTAT_RXBUSY
, 0);
642 poll_ready(priv
, ECON1
, ECON1_TXRTS
, 0);
643 /* ECON2_VRPS was set during initialization */
644 nolock_reg_bfset(priv
, ECON2
, ECON2_PWRSV
);
646 nolock_reg_bfclr(priv
, ECON2
, ECON2_PWRSV
);
647 poll_ready(priv
, ESTAT
, ESTAT_CLKRDY
, ESTAT_CLKRDY
);
648 /* caller sets ECON1_RXEN */
650 mutex_unlock(&priv
->lock
);
653 static int enc28j60_hw_init(struct enc28j60_net
*priv
)
657 if (netif_msg_drv(priv
))
658 printk(KERN_DEBUG DRV_NAME
": %s() - %s\n", __func__
,
659 priv
->full_duplex
? "FullDuplex" : "HalfDuplex");
661 mutex_lock(&priv
->lock
);
662 /* first reset the chip */
663 enc28j60_soft_reset(priv
);
665 spi_write_op(priv
, ENC28J60_WRITE_CTRL_REG
, ECON1
, 0x00);
667 priv
->hw_enable
= false;
668 priv
->tx_retry_count
= 0;
669 priv
->max_pk_counter
= 0;
670 priv
->rxfilter
= RXFILTER_NORMAL
;
671 /* enable address auto increment and voltage regulator powersave */
672 nolock_regb_write(priv
, ECON2
, ECON2_AUTOINC
| ECON2_VRPS
);
674 nolock_rxfifo_init(priv
, RXSTART_INIT
, RXEND_INIT
);
675 nolock_txfifo_init(priv
, TXSTART_INIT
, TXEND_INIT
);
676 mutex_unlock(&priv
->lock
);
680 * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
683 reg
= locked_regb_read(priv
, EREVID
);
684 if (netif_msg_drv(priv
))
685 printk(KERN_INFO DRV_NAME
": chip RevID: 0x%02x\n", reg
);
686 if (reg
== 0x00 || reg
== 0xff) {
687 if (netif_msg_drv(priv
))
688 printk(KERN_DEBUG DRV_NAME
": %s() Invalid RevId %d\n",
693 /* default filter mode: (unicast OR broadcast) AND crc valid */
694 locked_regb_write(priv
, ERXFCON
,
695 ERXFCON_UCEN
| ERXFCON_CRCEN
| ERXFCON_BCEN
);
697 /* enable MAC receive */
698 locked_regb_write(priv
, MACON1
,
699 MACON1_MARXEN
| MACON1_TXPAUS
| MACON1_RXPAUS
);
700 /* enable automatic padding and CRC operations */
701 if (priv
->full_duplex
) {
702 locked_regb_write(priv
, MACON3
,
703 MACON3_PADCFG0
| MACON3_TXCRCEN
|
704 MACON3_FRMLNEN
| MACON3_FULDPX
);
705 /* set inter-frame gap (non-back-to-back) */
706 locked_regb_write(priv
, MAIPGL
, 0x12);
707 /* set inter-frame gap (back-to-back) */
708 locked_regb_write(priv
, MABBIPG
, 0x15);
710 locked_regb_write(priv
, MACON3
,
711 MACON3_PADCFG0
| MACON3_TXCRCEN
|
713 locked_regb_write(priv
, MACON4
, 1 << 6); /* DEFER bit */
714 /* set inter-frame gap (non-back-to-back) */
715 locked_regw_write(priv
, MAIPGL
, 0x0C12);
716 /* set inter-frame gap (back-to-back) */
717 locked_regb_write(priv
, MABBIPG
, 0x12);
722 * Set the maximum packet size which the controller will accept
724 locked_regw_write(priv
, MAMXFLL
, MAX_FRAMELEN
);
727 if (!enc28j60_phy_write(priv
, PHLCON
, ENC28J60_LAMPS_MODE
))
730 if (priv
->full_duplex
) {
731 if (!enc28j60_phy_write(priv
, PHCON1
, PHCON1_PDPXMD
))
733 if (!enc28j60_phy_write(priv
, PHCON2
, 0x00))
736 if (!enc28j60_phy_write(priv
, PHCON1
, 0x00))
738 if (!enc28j60_phy_write(priv
, PHCON2
, PHCON2_HDLDIS
))
741 if (netif_msg_hw(priv
))
742 enc28j60_dump_regs(priv
, "Hw initialized.");
747 static void enc28j60_hw_enable(struct enc28j60_net
*priv
)
749 /* enable interrupts */
750 if (netif_msg_hw(priv
))
751 printk(KERN_DEBUG DRV_NAME
": %s() enabling interrupts.\n",
754 enc28j60_phy_write(priv
, PHIE
, PHIE_PGEIE
| PHIE_PLNKIE
);
756 mutex_lock(&priv
->lock
);
757 nolock_reg_bfclr(priv
, EIR
, EIR_DMAIF
| EIR_LINKIF
|
758 EIR_TXIF
| EIR_TXERIF
| EIR_RXERIF
| EIR_PKTIF
);
759 nolock_regb_write(priv
, EIE
, EIE_INTIE
| EIE_PKTIE
| EIE_LINKIE
|
760 EIE_TXIE
| EIE_TXERIE
| EIE_RXERIE
);
762 /* enable receive logic */
763 nolock_reg_bfset(priv
, ECON1
, ECON1_RXEN
);
764 priv
->hw_enable
= true;
765 mutex_unlock(&priv
->lock
);
768 static void enc28j60_hw_disable(struct enc28j60_net
*priv
)
770 mutex_lock(&priv
->lock
);
771 /* disable interrutps and packet reception */
772 nolock_regb_write(priv
, EIE
, 0x00);
773 nolock_reg_bfclr(priv
, ECON1
, ECON1_RXEN
);
774 priv
->hw_enable
= false;
775 mutex_unlock(&priv
->lock
);
779 enc28j60_setlink(struct net_device
*ndev
, u8 autoneg
, u16 speed
, u8 duplex
)
781 struct enc28j60_net
*priv
= netdev_priv(ndev
);
784 if (!priv
->hw_enable
) {
785 /* link is in low power mode now; duplex setting
786 * will take effect on next enc28j60_hw_init().
788 if (autoneg
== AUTONEG_DISABLE
&& speed
== SPEED_10
)
789 priv
->full_duplex
= (duplex
== DUPLEX_FULL
);
791 if (netif_msg_link(priv
))
793 "unsupported link setting\n");
797 if (netif_msg_link(priv
))
798 dev_warn(&ndev
->dev
, "Warning: hw must be disabled "
799 "to set link mode\n");
806 * Read the Transmit Status Vector
808 static void enc28j60_read_tsv(struct enc28j60_net
*priv
, u8 tsv
[TSV_SIZE
])
812 endptr
= locked_regw_read(priv
, ETXNDL
);
813 if (netif_msg_hw(priv
))
814 printk(KERN_DEBUG DRV_NAME
": reading TSV at addr:0x%04x\n",
816 enc28j60_mem_read(priv
, endptr
+ 1, sizeof(tsv
), tsv
);
819 static void enc28j60_dump_tsv(struct enc28j60_net
*priv
, const char *msg
,
824 printk(KERN_DEBUG DRV_NAME
": %s - TSV:\n", msg
);
833 printk(KERN_DEBUG DRV_NAME
": ByteCount: %d, CollisionCount: %d,"
834 " TotByteOnWire: %d\n", tmp1
, tsv
[2] & 0x0f, tmp2
);
835 printk(KERN_DEBUG DRV_NAME
": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
836 " LenOutOfRange: %d\n", TSV_GETBIT(tsv
, TSV_TXDONE
),
837 TSV_GETBIT(tsv
, TSV_TXCRCERROR
),
838 TSV_GETBIT(tsv
, TSV_TXLENCHKERROR
),
839 TSV_GETBIT(tsv
, TSV_TXLENOUTOFRANGE
));
840 printk(KERN_DEBUG DRV_NAME
": Multicast: %d, Broadcast: %d, "
841 "PacketDefer: %d, ExDefer: %d\n",
842 TSV_GETBIT(tsv
, TSV_TXMULTICAST
),
843 TSV_GETBIT(tsv
, TSV_TXBROADCAST
),
844 TSV_GETBIT(tsv
, TSV_TXPACKETDEFER
),
845 TSV_GETBIT(tsv
, TSV_TXEXDEFER
));
846 printk(KERN_DEBUG DRV_NAME
": ExCollision: %d, LateCollision: %d, "
847 "Giant: %d, Underrun: %d\n",
848 TSV_GETBIT(tsv
, TSV_TXEXCOLLISION
),
849 TSV_GETBIT(tsv
, TSV_TXLATECOLLISION
),
850 TSV_GETBIT(tsv
, TSV_TXGIANT
), TSV_GETBIT(tsv
, TSV_TXUNDERRUN
));
851 printk(KERN_DEBUG DRV_NAME
": ControlFrame: %d, PauseFrame: %d, "
852 "BackPressApp: %d, VLanTagFrame: %d\n",
853 TSV_GETBIT(tsv
, TSV_TXCONTROLFRAME
),
854 TSV_GETBIT(tsv
, TSV_TXPAUSEFRAME
),
855 TSV_GETBIT(tsv
, TSV_BACKPRESSUREAPP
),
856 TSV_GETBIT(tsv
, TSV_TXVLANTAGFRAME
));
860 * Receive Status vector
862 static void enc28j60_dump_rsv(struct enc28j60_net
*priv
, const char *msg
,
863 u16 pk_ptr
, int len
, u16 sts
)
865 printk(KERN_DEBUG DRV_NAME
": %s - NextPk: 0x%04x - RSV:\n",
867 printk(KERN_DEBUG DRV_NAME
": ByteCount: %d, DribbleNibble: %d\n", len
,
868 RSV_GETBIT(sts
, RSV_DRIBBLENIBBLE
));
869 printk(KERN_DEBUG DRV_NAME
": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
870 " LenOutOfRange: %d\n", RSV_GETBIT(sts
, RSV_RXOK
),
871 RSV_GETBIT(sts
, RSV_CRCERROR
),
872 RSV_GETBIT(sts
, RSV_LENCHECKERR
),
873 RSV_GETBIT(sts
, RSV_LENOUTOFRANGE
));
874 printk(KERN_DEBUG DRV_NAME
": Multicast: %d, Broadcast: %d, "
875 "LongDropEvent: %d, CarrierEvent: %d\n",
876 RSV_GETBIT(sts
, RSV_RXMULTICAST
),
877 RSV_GETBIT(sts
, RSV_RXBROADCAST
),
878 RSV_GETBIT(sts
, RSV_RXLONGEVDROPEV
),
879 RSV_GETBIT(sts
, RSV_CARRIEREV
));
880 printk(KERN_DEBUG DRV_NAME
": ControlFrame: %d, PauseFrame: %d,"
881 " UnknownOp: %d, VLanTagFrame: %d\n",
882 RSV_GETBIT(sts
, RSV_RXCONTROLFRAME
),
883 RSV_GETBIT(sts
, RSV_RXPAUSEFRAME
),
884 RSV_GETBIT(sts
, RSV_RXUNKNOWNOPCODE
),
885 RSV_GETBIT(sts
, RSV_RXTYPEVLAN
));
888 static void dump_packet(const char *msg
, int len
, const char *data
)
890 printk(KERN_DEBUG DRV_NAME
": %s - packet len:%d\n", msg
, len
);
891 print_hex_dump(KERN_DEBUG
, "pk data: ", DUMP_PREFIX_OFFSET
, 16, 1,
896 * Hardware receive function.
897 * Read the buffer memory, update the FIFO pointer to free the buffer,
898 * check the status vector and decrement the packet counter.
900 static void enc28j60_hw_rx(struct net_device
*ndev
)
902 struct enc28j60_net
*priv
= netdev_priv(ndev
);
903 struct sk_buff
*skb
= NULL
;
904 u16 erxrdpt
, next_packet
, rxstat
;
908 if (netif_msg_rx_status(priv
))
909 printk(KERN_DEBUG DRV_NAME
": RX pk_addr:0x%04x\n",
912 if (unlikely(priv
->next_pk_ptr
> RXEND_INIT
)) {
913 if (netif_msg_rx_err(priv
))
915 "%s() Invalid packet address!! 0x%04x\n",
916 __func__
, priv
->next_pk_ptr
);
917 /* packet address corrupted: reset RX logic */
918 mutex_lock(&priv
->lock
);
919 nolock_reg_bfclr(priv
, ECON1
, ECON1_RXEN
);
920 nolock_reg_bfset(priv
, ECON1
, ECON1_RXRST
);
921 nolock_reg_bfclr(priv
, ECON1
, ECON1_RXRST
);
922 nolock_rxfifo_init(priv
, RXSTART_INIT
, RXEND_INIT
);
923 nolock_reg_bfclr(priv
, EIR
, EIR_RXERIF
);
924 nolock_reg_bfset(priv
, ECON1
, ECON1_RXEN
);
925 mutex_unlock(&priv
->lock
);
926 ndev
->stats
.rx_errors
++;
929 /* Read next packet pointer and rx status vector */
930 enc28j60_mem_read(priv
, priv
->next_pk_ptr
, sizeof(rsv
), rsv
);
932 next_packet
= rsv
[1];
934 next_packet
|= rsv
[0];
944 if (netif_msg_rx_status(priv
))
945 enc28j60_dump_rsv(priv
, __func__
, next_packet
, len
, rxstat
);
947 if (!RSV_GETBIT(rxstat
, RSV_RXOK
) || len
> MAX_FRAMELEN
) {
948 if (netif_msg_rx_err(priv
))
949 dev_err(&ndev
->dev
, "Rx Error (%04x)\n", rxstat
);
950 ndev
->stats
.rx_errors
++;
951 if (RSV_GETBIT(rxstat
, RSV_CRCERROR
))
952 ndev
->stats
.rx_crc_errors
++;
953 if (RSV_GETBIT(rxstat
, RSV_LENCHECKERR
))
954 ndev
->stats
.rx_frame_errors
++;
955 if (len
> MAX_FRAMELEN
)
956 ndev
->stats
.rx_over_errors
++;
958 skb
= dev_alloc_skb(len
+ NET_IP_ALIGN
);
960 if (netif_msg_rx_err(priv
))
962 "out of memory for Rx'd frame\n");
963 ndev
->stats
.rx_dropped
++;
966 skb_reserve(skb
, NET_IP_ALIGN
);
967 /* copy the packet from the receive buffer */
968 enc28j60_mem_read(priv
,
969 rx_packet_start(priv
->next_pk_ptr
),
970 len
, skb_put(skb
, len
));
971 if (netif_msg_pktdata(priv
))
972 dump_packet(__func__
, skb
->len
, skb
->data
);
973 skb
->protocol
= eth_type_trans(skb
, ndev
);
974 /* update statistics */
975 ndev
->stats
.rx_packets
++;
976 ndev
->stats
.rx_bytes
+= len
;
981 * Move the RX read pointer to the start of the next
983 * This frees the memory we just read out
985 erxrdpt
= erxrdpt_workaround(next_packet
, RXSTART_INIT
, RXEND_INIT
);
986 if (netif_msg_hw(priv
))
987 printk(KERN_DEBUG DRV_NAME
": %s() ERXRDPT:0x%04x\n",
990 mutex_lock(&priv
->lock
);
991 nolock_regw_write(priv
, ERXRDPTL
, erxrdpt
);
992 #ifdef CONFIG_ENC28J60_WRITEVERIFY
993 if (netif_msg_drv(priv
)) {
995 reg
= nolock_regw_read(priv
, ERXRDPTL
);
997 printk(KERN_DEBUG DRV_NAME
": %s() ERXRDPT verify "
998 "error (0x%04x - 0x%04x)\n", __func__
,
1002 priv
->next_pk_ptr
= next_packet
;
1003 /* we are done with this packet, decrement the packet counter */
1004 nolock_reg_bfset(priv
, ECON2
, ECON2_PKTDEC
);
1005 mutex_unlock(&priv
->lock
);
1009 * Calculate free space in RxFIFO
1011 static int enc28j60_get_free_rxfifo(struct enc28j60_net
*priv
)
1013 int epkcnt
, erxst
, erxnd
, erxwr
, erxrd
;
1016 mutex_lock(&priv
->lock
);
1017 epkcnt
= nolock_regb_read(priv
, EPKTCNT
);
1021 erxst
= nolock_regw_read(priv
, ERXSTL
);
1022 erxnd
= nolock_regw_read(priv
, ERXNDL
);
1023 erxwr
= nolock_regw_read(priv
, ERXWRPTL
);
1024 erxrd
= nolock_regw_read(priv
, ERXRDPTL
);
1027 free_space
= (erxnd
- erxst
) - (erxwr
- erxrd
);
1028 else if (erxwr
== erxrd
)
1029 free_space
= (erxnd
- erxst
);
1031 free_space
= erxrd
- erxwr
- 1;
1033 mutex_unlock(&priv
->lock
);
1034 if (netif_msg_rx_status(priv
))
1035 printk(KERN_DEBUG DRV_NAME
": %s() free_space = %d\n",
1036 __func__
, free_space
);
1041 * Access the PHY to determine link status
1043 static void enc28j60_check_link_status(struct net_device
*ndev
)
1045 struct enc28j60_net
*priv
= netdev_priv(ndev
);
1049 reg
= enc28j60_phy_read(priv
, PHSTAT2
);
1050 if (netif_msg_hw(priv
))
1051 printk(KERN_DEBUG DRV_NAME
": %s() PHSTAT1: %04x, "
1052 "PHSTAT2: %04x\n", __func__
,
1053 enc28j60_phy_read(priv
, PHSTAT1
), reg
);
1054 duplex
= reg
& PHSTAT2_DPXSTAT
;
1056 if (reg
& PHSTAT2_LSTAT
) {
1057 netif_carrier_on(ndev
);
1058 if (netif_msg_ifup(priv
))
1059 dev_info(&ndev
->dev
, "link up - %s\n",
1060 duplex
? "Full duplex" : "Half duplex");
1062 if (netif_msg_ifdown(priv
))
1063 dev_info(&ndev
->dev
, "link down\n");
1064 netif_carrier_off(ndev
);
1068 static void enc28j60_tx_clear(struct net_device
*ndev
, bool err
)
1070 struct enc28j60_net
*priv
= netdev_priv(ndev
);
1073 ndev
->stats
.tx_errors
++;
1075 ndev
->stats
.tx_packets
++;
1079 ndev
->stats
.tx_bytes
+= priv
->tx_skb
->len
;
1080 dev_kfree_skb(priv
->tx_skb
);
1081 priv
->tx_skb
= NULL
;
1083 locked_reg_bfclr(priv
, ECON1
, ECON1_TXRTS
);
1084 netif_wake_queue(ndev
);
1089 * ignore PKTIF because is unreliable! (look at the errata datasheet)
1090 * check EPKTCNT is the suggested workaround.
1091 * We don't need to clear interrupt flag, automatically done when
1092 * enc28j60_hw_rx() decrements the packet counter.
1093 * Returns how many packet processed.
1095 static int enc28j60_rx_interrupt(struct net_device
*ndev
)
1097 struct enc28j60_net
*priv
= netdev_priv(ndev
);
1098 int pk_counter
, ret
;
1100 pk_counter
= locked_regb_read(priv
, EPKTCNT
);
1101 if (pk_counter
&& netif_msg_intr(priv
))
1102 printk(KERN_DEBUG DRV_NAME
": intRX, pk_cnt: %d\n", pk_counter
);
1103 if (pk_counter
> priv
->max_pk_counter
) {
1104 /* update statistics */
1105 priv
->max_pk_counter
= pk_counter
;
1106 if (netif_msg_rx_status(priv
) && priv
->max_pk_counter
> 1)
1107 printk(KERN_DEBUG DRV_NAME
": RX max_pk_cnt: %d\n",
1108 priv
->max_pk_counter
);
1111 while (pk_counter
-- > 0)
1112 enc28j60_hw_rx(ndev
);
1117 static void enc28j60_irq_work_handler(struct work_struct
*work
)
1119 struct enc28j60_net
*priv
=
1120 container_of(work
, struct enc28j60_net
, irq_work
);
1121 struct net_device
*ndev
= priv
->netdev
;
1124 if (netif_msg_intr(priv
))
1125 printk(KERN_DEBUG DRV_NAME
": %s() enter\n", __func__
);
1126 /* disable further interrupts */
1127 locked_reg_bfclr(priv
, EIE
, EIE_INTIE
);
1131 intflags
= locked_regb_read(priv
, EIR
);
1132 /* DMA interrupt handler (not currently used) */
1133 if ((intflags
& EIR_DMAIF
) != 0) {
1135 if (netif_msg_intr(priv
))
1136 printk(KERN_DEBUG DRV_NAME
1137 ": intDMA(%d)\n", loop
);
1138 locked_reg_bfclr(priv
, EIR
, EIR_DMAIF
);
1140 /* LINK changed handler */
1141 if ((intflags
& EIR_LINKIF
) != 0) {
1143 if (netif_msg_intr(priv
))
1144 printk(KERN_DEBUG DRV_NAME
1145 ": intLINK(%d)\n", loop
);
1146 enc28j60_check_link_status(ndev
);
1147 /* read PHIR to clear the flag */
1148 enc28j60_phy_read(priv
, PHIR
);
1150 /* TX complete handler */
1151 if ((intflags
& EIR_TXIF
) != 0) {
1154 if (netif_msg_intr(priv
))
1155 printk(KERN_DEBUG DRV_NAME
1156 ": intTX(%d)\n", loop
);
1157 priv
->tx_retry_count
= 0;
1158 if (locked_regb_read(priv
, ESTAT
) & ESTAT_TXABRT
) {
1159 if (netif_msg_tx_err(priv
))
1161 "Tx Error (aborted)\n");
1164 if (netif_msg_tx_done(priv
)) {
1166 enc28j60_read_tsv(priv
, tsv
);
1167 enc28j60_dump_tsv(priv
, "Tx Done", tsv
);
1169 enc28j60_tx_clear(ndev
, err
);
1170 locked_reg_bfclr(priv
, EIR
, EIR_TXIF
);
1172 /* TX Error handler */
1173 if ((intflags
& EIR_TXERIF
) != 0) {
1177 if (netif_msg_intr(priv
))
1178 printk(KERN_DEBUG DRV_NAME
1179 ": intTXErr(%d)\n", loop
);
1180 locked_reg_bfclr(priv
, ECON1
, ECON1_TXRTS
);
1181 enc28j60_read_tsv(priv
, tsv
);
1182 if (netif_msg_tx_err(priv
))
1183 enc28j60_dump_tsv(priv
, "Tx Error", tsv
);
1184 /* Reset TX logic */
1185 mutex_lock(&priv
->lock
);
1186 nolock_reg_bfset(priv
, ECON1
, ECON1_TXRST
);
1187 nolock_reg_bfclr(priv
, ECON1
, ECON1_TXRST
);
1188 nolock_txfifo_init(priv
, TXSTART_INIT
, TXEND_INIT
);
1189 mutex_unlock(&priv
->lock
);
1190 /* Transmit Late collision check for retransmit */
1191 if (TSV_GETBIT(tsv
, TSV_TXLATECOLLISION
)) {
1192 if (netif_msg_tx_err(priv
))
1193 printk(KERN_DEBUG DRV_NAME
1194 ": LateCollision TXErr (%d)\n",
1195 priv
->tx_retry_count
);
1196 if (priv
->tx_retry_count
++ < MAX_TX_RETRYCOUNT
)
1197 locked_reg_bfset(priv
, ECON1
,
1200 enc28j60_tx_clear(ndev
, true);
1202 enc28j60_tx_clear(ndev
, true);
1203 locked_reg_bfclr(priv
, EIR
, EIR_TXERIF
);
1205 /* RX Error handler */
1206 if ((intflags
& EIR_RXERIF
) != 0) {
1208 if (netif_msg_intr(priv
))
1209 printk(KERN_DEBUG DRV_NAME
1210 ": intRXErr(%d)\n", loop
);
1211 /* Check free FIFO space to flag RX overrun */
1212 if (enc28j60_get_free_rxfifo(priv
) <= 0) {
1213 if (netif_msg_rx_err(priv
))
1214 printk(KERN_DEBUG DRV_NAME
1216 ndev
->stats
.rx_dropped
++;
1218 locked_reg_bfclr(priv
, EIR
, EIR_RXERIF
);
1221 if (enc28j60_rx_interrupt(ndev
))
1225 /* re-enable interrupts */
1226 locked_reg_bfset(priv
, EIE
, EIE_INTIE
);
1227 if (netif_msg_intr(priv
))
1228 printk(KERN_DEBUG DRV_NAME
": %s() exit\n", __func__
);
1232 * Hardware transmit function.
1233 * Fill the buffer memory and send the contents of the transmit buffer
1236 static void enc28j60_hw_tx(struct enc28j60_net
*priv
)
1238 if (netif_msg_tx_queued(priv
))
1239 printk(KERN_DEBUG DRV_NAME
1240 ": Tx Packet Len:%d\n", priv
->tx_skb
->len
);
1242 if (netif_msg_pktdata(priv
))
1243 dump_packet(__func__
,
1244 priv
->tx_skb
->len
, priv
->tx_skb
->data
);
1245 enc28j60_packet_write(priv
, priv
->tx_skb
->len
, priv
->tx_skb
->data
);
1247 #ifdef CONFIG_ENC28J60_WRITEVERIFY
1248 /* readback and verify written data */
1249 if (netif_msg_drv(priv
)) {
1251 u8 test_buf
[64]; /* limit the test to the first 64 bytes */
1254 test_len
= priv
->tx_skb
->len
;
1255 if (test_len
> sizeof(test_buf
))
1256 test_len
= sizeof(test_buf
);
1258 /* + 1 to skip control byte */
1259 enc28j60_mem_read(priv
, TXSTART_INIT
+ 1, test_len
, test_buf
);
1261 for (k
= 0; k
< test_len
; k
++) {
1262 if (priv
->tx_skb
->data
[k
] != test_buf
[k
]) {
1263 printk(KERN_DEBUG DRV_NAME
1264 ": Error, %d location differ: "
1265 "0x%02x-0x%02x\n", k
,
1266 priv
->tx_skb
->data
[k
], test_buf
[k
]);
1271 printk(KERN_DEBUG DRV_NAME
": Tx write buffer, "
1275 /* set TX request flag */
1276 locked_reg_bfset(priv
, ECON1
, ECON1_TXRTS
);
1279 static int enc28j60_send_packet(struct sk_buff
*skb
, struct net_device
*dev
)
1281 struct enc28j60_net
*priv
= netdev_priv(dev
);
1283 if (netif_msg_tx_queued(priv
))
1284 printk(KERN_DEBUG DRV_NAME
": %s() enter\n", __func__
);
1286 /* If some error occurs while trying to transmit this
1287 * packet, you should return '1' from this function.
1288 * In such a case you _may not_ do anything to the
1289 * SKB, it is still owned by the network queueing
1290 * layer when an error is returned. This means you
1291 * may not modify any SKB fields, you may not free
1294 netif_stop_queue(dev
);
1296 /* save the timestamp */
1297 priv
->netdev
->trans_start
= jiffies
;
1298 /* Remember the skb for deferred processing */
1300 schedule_work(&priv
->tx_work
);
1302 return NETDEV_TX_OK
;
1305 static void enc28j60_tx_work_handler(struct work_struct
*work
)
1307 struct enc28j60_net
*priv
=
1308 container_of(work
, struct enc28j60_net
, tx_work
);
1310 /* actual delivery of data */
1311 enc28j60_hw_tx(priv
);
1314 static irqreturn_t
enc28j60_irq(int irq
, void *dev_id
)
1316 struct enc28j60_net
*priv
= dev_id
;
1319 * Can't do anything in interrupt context because we need to
1320 * block (spi_sync() is blocking) so fire of the interrupt
1321 * handling workqueue.
1322 * Remember that we access enc28j60 registers through SPI bus
1323 * via spi_sync() call.
1325 schedule_work(&priv
->irq_work
);
1330 static void enc28j60_tx_timeout(struct net_device
*ndev
)
1332 struct enc28j60_net
*priv
= netdev_priv(ndev
);
1334 if (netif_msg_timer(priv
))
1335 dev_err(&ndev
->dev
, DRV_NAME
" tx timeout\n");
1337 ndev
->stats
.tx_errors
++;
1338 /* can't restart safely under softirq */
1339 schedule_work(&priv
->restart_work
);
1343 * Open/initialize the board. This is called (in the current kernel)
1344 * sometime after booting when the 'ifconfig' program is run.
1346 * This routine should set everything up anew at each open, even
1347 * registers that "should" only need to be set once at boot, so that
1348 * there is non-reboot way to recover if something goes wrong.
1350 static int enc28j60_net_open(struct net_device
*dev
)
1352 struct enc28j60_net
*priv
= netdev_priv(dev
);
1354 if (netif_msg_drv(priv
))
1355 printk(KERN_DEBUG DRV_NAME
": %s() enter\n", __func__
);
1357 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1358 if (netif_msg_ifup(priv
))
1359 dev_err(&dev
->dev
, "invalid MAC address %pM\n",
1361 return -EADDRNOTAVAIL
;
1363 /* Reset the hardware here (and take it out of low power mode) */
1364 enc28j60_lowpower(priv
, false);
1365 enc28j60_hw_disable(priv
);
1366 if (!enc28j60_hw_init(priv
)) {
1367 if (netif_msg_ifup(priv
))
1368 dev_err(&dev
->dev
, "hw_reset() failed\n");
1371 /* Update the MAC address (in case user has changed it) */
1372 enc28j60_set_hw_macaddr(dev
);
1373 /* Enable interrupts */
1374 enc28j60_hw_enable(priv
);
1375 /* check link status */
1376 enc28j60_check_link_status(dev
);
1377 /* We are now ready to accept transmit requests from
1378 * the queueing layer of the networking.
1380 netif_start_queue(dev
);
1385 /* The inverse routine to net_open(). */
1386 static int enc28j60_net_close(struct net_device
*dev
)
1388 struct enc28j60_net
*priv
= netdev_priv(dev
);
1390 if (netif_msg_drv(priv
))
1391 printk(KERN_DEBUG DRV_NAME
": %s() enter\n", __func__
);
1393 enc28j60_hw_disable(priv
);
1394 enc28j60_lowpower(priv
, true);
1395 netif_stop_queue(dev
);
1401 * Set or clear the multicast filter for this adapter
1402 * num_addrs == -1 Promiscuous mode, receive all packets
1403 * num_addrs == 0 Normal mode, filter out multicast packets
1404 * num_addrs > 0 Multicast mode, receive normal and MC packets
1406 static void enc28j60_set_multicast_list(struct net_device
*dev
)
1408 struct enc28j60_net
*priv
= netdev_priv(dev
);
1409 int oldfilter
= priv
->rxfilter
;
1411 if (dev
->flags
& IFF_PROMISC
) {
1412 if (netif_msg_link(priv
))
1413 dev_info(&dev
->dev
, "promiscuous mode\n");
1414 priv
->rxfilter
= RXFILTER_PROMISC
;
1415 } else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
) {
1416 if (netif_msg_link(priv
))
1417 dev_info(&dev
->dev
, "%smulticast mode\n",
1418 (dev
->flags
& IFF_ALLMULTI
) ? "all-" : "");
1419 priv
->rxfilter
= RXFILTER_MULTI
;
1421 if (netif_msg_link(priv
))
1422 dev_info(&dev
->dev
, "normal mode\n");
1423 priv
->rxfilter
= RXFILTER_NORMAL
;
1426 if (oldfilter
!= priv
->rxfilter
)
1427 schedule_work(&priv
->setrx_work
);
1430 static void enc28j60_setrx_work_handler(struct work_struct
*work
)
1432 struct enc28j60_net
*priv
=
1433 container_of(work
, struct enc28j60_net
, setrx_work
);
1435 if (priv
->rxfilter
== RXFILTER_PROMISC
) {
1436 if (netif_msg_drv(priv
))
1437 printk(KERN_DEBUG DRV_NAME
": promiscuous mode\n");
1438 locked_regb_write(priv
, ERXFCON
, 0x00);
1439 } else if (priv
->rxfilter
== RXFILTER_MULTI
) {
1440 if (netif_msg_drv(priv
))
1441 printk(KERN_DEBUG DRV_NAME
": multicast mode\n");
1442 locked_regb_write(priv
, ERXFCON
,
1443 ERXFCON_UCEN
| ERXFCON_CRCEN
|
1444 ERXFCON_BCEN
| ERXFCON_MCEN
);
1446 if (netif_msg_drv(priv
))
1447 printk(KERN_DEBUG DRV_NAME
": normal mode\n");
1448 locked_regb_write(priv
, ERXFCON
,
1449 ERXFCON_UCEN
| ERXFCON_CRCEN
|
1454 static void enc28j60_restart_work_handler(struct work_struct
*work
)
1456 struct enc28j60_net
*priv
=
1457 container_of(work
, struct enc28j60_net
, restart_work
);
1458 struct net_device
*ndev
= priv
->netdev
;
1462 if (netif_running(ndev
)) {
1463 enc28j60_net_close(ndev
);
1464 ret
= enc28j60_net_open(ndev
);
1465 if (unlikely(ret
)) {
1466 dev_info(&ndev
->dev
, " could not restart %d\n", ret
);
1473 /* ......................... ETHTOOL SUPPORT ........................... */
1476 enc28j60_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1478 strlcpy(info
->driver
, DRV_NAME
, sizeof(info
->driver
));
1479 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
1480 strlcpy(info
->bus_info
,
1481 dev_name(dev
->dev
.parent
), sizeof(info
->bus_info
));
1485 enc28j60_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1487 struct enc28j60_net
*priv
= netdev_priv(dev
);
1489 cmd
->transceiver
= XCVR_INTERNAL
;
1490 cmd
->supported
= SUPPORTED_10baseT_Half
1491 | SUPPORTED_10baseT_Full
1493 cmd
->speed
= SPEED_10
;
1494 cmd
->duplex
= priv
->full_duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
1495 cmd
->port
= PORT_TP
;
1496 cmd
->autoneg
= AUTONEG_DISABLE
;
1502 enc28j60_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1504 return enc28j60_setlink(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
1507 static u32
enc28j60_get_msglevel(struct net_device
*dev
)
1509 struct enc28j60_net
*priv
= netdev_priv(dev
);
1510 return priv
->msg_enable
;
1513 static void enc28j60_set_msglevel(struct net_device
*dev
, u32 val
)
1515 struct enc28j60_net
*priv
= netdev_priv(dev
);
1516 priv
->msg_enable
= val
;
1519 static const struct ethtool_ops enc28j60_ethtool_ops
= {
1520 .get_settings
= enc28j60_get_settings
,
1521 .set_settings
= enc28j60_set_settings
,
1522 .get_drvinfo
= enc28j60_get_drvinfo
,
1523 .get_msglevel
= enc28j60_get_msglevel
,
1524 .set_msglevel
= enc28j60_set_msglevel
,
1527 static int enc28j60_chipset_init(struct net_device
*dev
)
1529 struct enc28j60_net
*priv
= netdev_priv(dev
);
1531 return enc28j60_hw_init(priv
);
1534 static const struct net_device_ops enc28j60_netdev_ops
= {
1535 .ndo_open
= enc28j60_net_open
,
1536 .ndo_stop
= enc28j60_net_close
,
1537 .ndo_start_xmit
= enc28j60_send_packet
,
1538 .ndo_set_multicast_list
= enc28j60_set_multicast_list
,
1539 .ndo_set_mac_address
= enc28j60_set_mac_address
,
1540 .ndo_tx_timeout
= enc28j60_tx_timeout
,
1541 .ndo_change_mtu
= eth_change_mtu
,
1542 .ndo_validate_addr
= eth_validate_addr
,
1545 static int __devinit
enc28j60_probe(struct spi_device
*spi
)
1547 struct net_device
*dev
;
1548 struct enc28j60_net
*priv
;
1551 if (netif_msg_drv(&debug
))
1552 dev_info(&spi
->dev
, DRV_NAME
" Ethernet driver %s loaded\n",
1555 dev
= alloc_etherdev(sizeof(struct enc28j60_net
));
1557 if (netif_msg_drv(&debug
))
1558 dev_err(&spi
->dev
, DRV_NAME
1559 ": unable to alloc new ethernet\n");
1563 priv
= netdev_priv(dev
);
1565 priv
->netdev
= dev
; /* priv to netdev reference */
1566 priv
->spi
= spi
; /* priv to spi reference */
1567 priv
->msg_enable
= netif_msg_init(debug
.msg_enable
,
1568 ENC28J60_MSG_DEFAULT
);
1569 mutex_init(&priv
->lock
);
1570 INIT_WORK(&priv
->tx_work
, enc28j60_tx_work_handler
);
1571 INIT_WORK(&priv
->setrx_work
, enc28j60_setrx_work_handler
);
1572 INIT_WORK(&priv
->irq_work
, enc28j60_irq_work_handler
);
1573 INIT_WORK(&priv
->restart_work
, enc28j60_restart_work_handler
);
1574 dev_set_drvdata(&spi
->dev
, priv
); /* spi to priv reference */
1575 SET_NETDEV_DEV(dev
, &spi
->dev
);
1577 if (!enc28j60_chipset_init(dev
)) {
1578 if (netif_msg_probe(priv
))
1579 dev_info(&spi
->dev
, DRV_NAME
" chip not found\n");
1583 random_ether_addr(dev
->dev_addr
);
1584 enc28j60_set_hw_macaddr(dev
);
1586 /* Board setup must set the relevant edge trigger type;
1587 * level triggers won't currently work.
1589 ret
= request_irq(spi
->irq
, enc28j60_irq
, 0, DRV_NAME
, priv
);
1591 if (netif_msg_probe(priv
))
1592 dev_err(&spi
->dev
, DRV_NAME
": request irq %d failed "
1593 "(ret = %d)\n", spi
->irq
, ret
);
1597 dev
->if_port
= IF_PORT_10BASET
;
1598 dev
->irq
= spi
->irq
;
1599 dev
->netdev_ops
= &enc28j60_netdev_ops
;
1600 dev
->watchdog_timeo
= TX_TIMEOUT
;
1601 SET_ETHTOOL_OPS(dev
, &enc28j60_ethtool_ops
);
1603 enc28j60_lowpower(priv
, true);
1605 ret
= register_netdev(dev
);
1607 if (netif_msg_probe(priv
))
1608 dev_err(&spi
->dev
, "register netdev " DRV_NAME
1609 " failed (ret = %d)\n", ret
);
1610 goto error_register
;
1612 dev_info(&dev
->dev
, DRV_NAME
" driver registered\n");
1617 free_irq(spi
->irq
, priv
);
1624 static int __devexit
enc28j60_remove(struct spi_device
*spi
)
1626 struct enc28j60_net
*priv
= dev_get_drvdata(&spi
->dev
);
1628 if (netif_msg_drv(priv
))
1629 printk(KERN_DEBUG DRV_NAME
": remove\n");
1631 unregister_netdev(priv
->netdev
);
1632 free_irq(spi
->irq
, priv
);
1633 free_netdev(priv
->netdev
);
1638 static struct spi_driver enc28j60_driver
= {
1641 .owner
= THIS_MODULE
,
1643 .probe
= enc28j60_probe
,
1644 .remove
= __devexit_p(enc28j60_remove
),
1647 static int __init
enc28j60_init(void)
1649 msec20_to_jiffies
= msecs_to_jiffies(20);
1651 return spi_register_driver(&enc28j60_driver
);
1654 module_init(enc28j60_init
);
1656 static void __exit
enc28j60_exit(void)
1658 spi_unregister_driver(&enc28j60_driver
);
1661 module_exit(enc28j60_exit
);
1663 MODULE_DESCRIPTION(DRV_NAME
" ethernet driver");
1664 MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1665 MODULE_LICENSE("GPL");
1666 module_param_named(debug
, debug
.msg_enable
, int, 0);
1667 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., ffff=all)");