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ath5k: fix values for bus error bits in ISR2
[linux-2.6/next.git] / drivers / spi / omap2_mcspi.c
blobeee4b6e0af2ccaa6ce592217ee11287a6c5aab41
1 /*
2 * OMAP2 McSPI controller driver
3 *
4 * Copyright (C) 2005, 2006 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com> and
6 * Juha Yrjölä <juha.yrjola@nokia.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/err.h>
33 #include <linux/clk.h>
34 #include <linux/io.h>
35
36 #include <linux/spi/spi.h>
37
38 #include <mach/dma.h>
39 #include <mach/clock.h>
40
41
42 #define OMAP2_MCSPI_MAX_FREQ 48000000
43
44 #define OMAP2_MCSPI_REVISION 0x00
45 #define OMAP2_MCSPI_SYSCONFIG 0x10
46 #define OMAP2_MCSPI_SYSSTATUS 0x14
47 #define OMAP2_MCSPI_IRQSTATUS 0x18
48 #define OMAP2_MCSPI_IRQENABLE 0x1c
49 #define OMAP2_MCSPI_WAKEUPENABLE 0x20
50 #define OMAP2_MCSPI_SYST 0x24
51 #define OMAP2_MCSPI_MODULCTRL 0x28
52
53 /* per-channel banks, 0x14 bytes each, first is: */
54 #define OMAP2_MCSPI_CHCONF0 0x2c
55 #define OMAP2_MCSPI_CHSTAT0 0x30
56 #define OMAP2_MCSPI_CHCTRL0 0x34
57 #define OMAP2_MCSPI_TX0 0x38
58 #define OMAP2_MCSPI_RX0 0x3c
59
60 /* per-register bitmasks: */
61
62 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE (1 << 0)
63 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
64
65 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
66
67 #define OMAP2_MCSPI_MODULCTRL_SINGLE (1 << 0)
68 #define OMAP2_MCSPI_MODULCTRL_MS (1 << 2)
69 #define OMAP2_MCSPI_MODULCTRL_STEST (1 << 3)
70
71 #define OMAP2_MCSPI_CHCONF_PHA (1 << 0)
72 #define OMAP2_MCSPI_CHCONF_POL (1 << 1)
73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK (0x0f << 2)
74 #define OMAP2_MCSPI_CHCONF_EPOL (1 << 6)
75 #define OMAP2_MCSPI_CHCONF_WL_MASK (0x1f << 7)
76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY (0x01 << 12)
77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY (0x02 << 12)
78 #define OMAP2_MCSPI_CHCONF_TRM_MASK (0x03 << 12)
79 #define OMAP2_MCSPI_CHCONF_DMAW (1 << 14)
80 #define OMAP2_MCSPI_CHCONF_DMAR (1 << 15)
81 #define OMAP2_MCSPI_CHCONF_DPE0 (1 << 16)
82 #define OMAP2_MCSPI_CHCONF_DPE1 (1 << 17)
83 #define OMAP2_MCSPI_CHCONF_IS (1 << 18)
84 #define OMAP2_MCSPI_CHCONF_TURBO (1 << 19)
85 #define OMAP2_MCSPI_CHCONF_FORCE (1 << 20)
86
87 #define OMAP2_MCSPI_CHSTAT_RXS (1 << 0)
88 #define OMAP2_MCSPI_CHSTAT_TXS (1 << 1)
89 #define OMAP2_MCSPI_CHSTAT_EOT (1 << 2)
90
91 #define OMAP2_MCSPI_CHCTRL_EN (1 << 0)
92
93
94 /* We have 2 DMA channels per CS, one for RX and one for TX */
95 struct omap2_mcspi_dma {
96 int dma_tx_channel;
97 int dma_rx_channel;
98
99 int dma_tx_sync_dev;
100 int dma_rx_sync_dev;
101
102 struct completion dma_tx_completion;
103 struct completion dma_rx_completion;
104 };
105
106 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
107 * cache operations; better heuristics consider wordsize and bitrate.
108 */
109 #define DMA_MIN_BYTES 8
110
111
112 struct omap2_mcspi {
113 struct work_struct work;
114 /* lock protects queue and registers */
115 spinlock_t lock;
116 struct list_head msg_queue;
117 struct spi_master *master;
118 struct clk *ick;
119 struct clk *fck;
120 /* Virtual base address of the controller */
121 void __iomem *base;
122 unsigned long phys;
123 /* SPI1 has 4 channels, while SPI2 has 2 */
124 struct omap2_mcspi_dma *dma_channels;
125 };
126
127 struct omap2_mcspi_cs {
128 void __iomem *base;
129 unsigned long phys;
130 int word_len;
131 };
132
133 static struct workqueue_struct *omap2_mcspi_wq;
134
135 #define MOD_REG_BIT(val, mask, set) do { \
136 if (set) \
137 val |= mask; \
138 else \
139 val &= ~mask; \
140 } while (0)
141
142 static inline void mcspi_write_reg(struct spi_master *master,
143 int idx, u32 val)
144 {
145 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
146
147 __raw_writel(val, mcspi->base + idx);
148 }
149
150 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
151 {
152 struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
153
154 return __raw_readl(mcspi->base + idx);
155 }
156
157 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
158 int idx, u32 val)
159 {
160 struct omap2_mcspi_cs *cs = spi->controller_state;
161
162 __raw_writel(val, cs->base + idx);
163 }
164
165 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
166 {
167 struct omap2_mcspi_cs *cs = spi->controller_state;
168
169 return __raw_readl(cs->base + idx);
170 }
171
172 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
173 int is_read, int enable)
174 {
175 u32 l, rw;
176
177 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
178
179 if (is_read) /* 1 is read, 0 write */
180 rw = OMAP2_MCSPI_CHCONF_DMAR;
181 else
182 rw = OMAP2_MCSPI_CHCONF_DMAW;
183
184 MOD_REG_BIT(l, rw, enable);
185 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
186 }
187
188 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
189 {
190 u32 l;
191
192 l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
193 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
194 }
195
196 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
197 {
198 u32 l;
199
200 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
201 MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
202 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
203 }
204
205 static void omap2_mcspi_set_master_mode(struct spi_master *master)
206 {
207 u32 l;
208
209 /* setup when switching from (reset default) slave mode
210 * to single-channel master mode
211 */
212 l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
213 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
214 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
215 MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
216 mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
217 }
218
219 static unsigned
220 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
221 {
222 struct omap2_mcspi *mcspi;
223 struct omap2_mcspi_cs *cs = spi->controller_state;
224 struct omap2_mcspi_dma *mcspi_dma;
225 unsigned int count, c;
226 unsigned long base, tx_reg, rx_reg;
227 int word_len, data_type, element_count;
228 u8 * rx;
229 const u8 * tx;
230
231 mcspi = spi_master_get_devdata(spi->master);
232 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
233
234 count = xfer->len;
235 c = count;
236 word_len = cs->word_len;
237
238 base = cs->phys;
239 tx_reg = base + OMAP2_MCSPI_TX0;
240 rx_reg = base + OMAP2_MCSPI_RX0;
241 rx = xfer->rx_buf;
242 tx = xfer->tx_buf;
243
244 if (word_len <= 8) {
245 data_type = OMAP_DMA_DATA_TYPE_S8;
246 element_count = count;
247 } else if (word_len <= 16) {
248 data_type = OMAP_DMA_DATA_TYPE_S16;
249 element_count = count >> 1;
250 } else /* word_len <= 32 */ {
251 data_type = OMAP_DMA_DATA_TYPE_S32;
252 element_count = count >> 2;
253 }
254
255 if (tx != NULL) {
256 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
257 data_type, element_count, 1,
258 OMAP_DMA_SYNC_ELEMENT,
259 mcspi_dma->dma_tx_sync_dev, 0);
260
261 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
262 OMAP_DMA_AMODE_CONSTANT,
263 tx_reg, 0, 0);
264
265 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
266 OMAP_DMA_AMODE_POST_INC,
267 xfer->tx_dma, 0, 0);
268 }
269
270 if (rx != NULL) {
271 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
272 data_type, element_count, 1,
273 OMAP_DMA_SYNC_ELEMENT,
274 mcspi_dma->dma_rx_sync_dev, 1);
275
276 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
277 OMAP_DMA_AMODE_CONSTANT,
278 rx_reg, 0, 0);
279
280 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
281 OMAP_DMA_AMODE_POST_INC,
282 xfer->rx_dma, 0, 0);
283 }
284
285 if (tx != NULL) {
286 omap_start_dma(mcspi_dma->dma_tx_channel);
287 omap2_mcspi_set_dma_req(spi, 0, 1);
288 }
289
290 if (rx != NULL) {
291 omap_start_dma(mcspi_dma->dma_rx_channel);
292 omap2_mcspi_set_dma_req(spi, 1, 1);
293 }
294
295 if (tx != NULL) {
296 wait_for_completion(&mcspi_dma->dma_tx_completion);
297 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
298 }
299
300 if (rx != NULL) {
301 wait_for_completion(&mcspi_dma->dma_rx_completion);
302 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
303 }
304 return count;
305 }
306
307 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
308 {
309 unsigned long timeout;
310
311 timeout = jiffies + msecs_to_jiffies(1000);
312 while (!(__raw_readl(reg) & bit)) {
313 if (time_after(jiffies, timeout))
314 return -1;
315 cpu_relax();
316 }
317 return 0;
318 }
319
320 static unsigned
321 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
322 {
323 struct omap2_mcspi *mcspi;
324 struct omap2_mcspi_cs *cs = spi->controller_state;
325 unsigned int count, c;
326 u32 l;
327 void __iomem *base = cs->base;
328 void __iomem *tx_reg;
329 void __iomem *rx_reg;
330 void __iomem *chstat_reg;
331 int word_len;
332
333 mcspi = spi_master_get_devdata(spi->master);
334 count = xfer->len;
335 c = count;
336 word_len = cs->word_len;
337
338 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
339 l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
340
341 /* We store the pre-calculated register addresses on stack to speed
342 * up the transfer loop. */
343 tx_reg = base + OMAP2_MCSPI_TX0;
344 rx_reg = base + OMAP2_MCSPI_RX0;
345 chstat_reg = base + OMAP2_MCSPI_CHSTAT0;
346
347 if (word_len <= 8) {
348 u8 *rx;
349 const u8 *tx;
350
351 rx = xfer->rx_buf;
352 tx = xfer->tx_buf;
353
354 do {
355 c -= 1;
356 if (tx != NULL) {
357 if (mcspi_wait_for_reg_bit(chstat_reg,
358 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
359 dev_err(&spi->dev, "TXS timed out\n");
360 goto out;
361 }
362 #ifdef VERBOSE
363 dev_dbg(&spi->dev, "write-%d %02x\n",
364 word_len, *tx);
365 #endif
366 __raw_writel(*tx++, tx_reg);
367 }
368 if (rx != NULL) {
369 if (mcspi_wait_for_reg_bit(chstat_reg,
370 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
371 dev_err(&spi->dev, "RXS timed out\n");
372 goto out;
373 }
374 /* prevent last RX_ONLY read from triggering
375 * more word i/o: switch to rx+tx
376 */
377 if (c == 0 && tx == NULL)
378 mcspi_write_cs_reg(spi,
379 OMAP2_MCSPI_CHCONF0, l);
380 *rx++ = __raw_readl(rx_reg);
381 #ifdef VERBOSE
382 dev_dbg(&spi->dev, "read-%d %02x\n",
383 word_len, *(rx - 1));
384 #endif
385 }
386 } while (c);
387 } else if (word_len <= 16) {
388 u16 *rx;
389 const u16 *tx;
390
391 rx = xfer->rx_buf;
392 tx = xfer->tx_buf;
393 do {
394 c -= 2;
395 if (tx != NULL) {
396 if (mcspi_wait_for_reg_bit(chstat_reg,
397 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
398 dev_err(&spi->dev, "TXS timed out\n");
399 goto out;
400 }
401 #ifdef VERBOSE
402 dev_dbg(&spi->dev, "write-%d %04x\n",
403 word_len, *tx);
404 #endif
405 __raw_writel(*tx++, tx_reg);
406 }
407 if (rx != NULL) {
408 if (mcspi_wait_for_reg_bit(chstat_reg,
409 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
410 dev_err(&spi->dev, "RXS timed out\n");
411 goto out;
412 }
413 /* prevent last RX_ONLY read from triggering
414 * more word i/o: switch to rx+tx
415 */
416 if (c == 0 && tx == NULL)
417 mcspi_write_cs_reg(spi,
418 OMAP2_MCSPI_CHCONF0, l);
419 *rx++ = __raw_readl(rx_reg);
420 #ifdef VERBOSE
421 dev_dbg(&spi->dev, "read-%d %04x\n",
422 word_len, *(rx - 1));
423 #endif
424 }
425 } while (c);
426 } else if (word_len <= 32) {
427 u32 *rx;
428 const u32 *tx;
429
430 rx = xfer->rx_buf;
431 tx = xfer->tx_buf;
432 do {
433 c -= 4;
434 if (tx != NULL) {
435 if (mcspi_wait_for_reg_bit(chstat_reg,
436 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
437 dev_err(&spi->dev, "TXS timed out\n");
438 goto out;
439 }
440 #ifdef VERBOSE
441 dev_dbg(&spi->dev, "write-%d %04x\n",
442 word_len, *tx);
443 #endif
444 __raw_writel(*tx++, tx_reg);
445 }
446 if (rx != NULL) {
447 if (mcspi_wait_for_reg_bit(chstat_reg,
448 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
449 dev_err(&spi->dev, "RXS timed out\n");
450 goto out;
451 }
452 /* prevent last RX_ONLY read from triggering
453 * more word i/o: switch to rx+tx
454 */
455 if (c == 0 && tx == NULL)
456 mcspi_write_cs_reg(spi,
457 OMAP2_MCSPI_CHCONF0, l);
458 *rx++ = __raw_readl(rx_reg);
459 #ifdef VERBOSE
460 dev_dbg(&spi->dev, "read-%d %04x\n",
461 word_len, *(rx - 1));
462 #endif
463 }
464 } while (c);
465 }
466
467 /* for TX_ONLY mode, be sure all words have shifted out */
468 if (xfer->rx_buf == NULL) {
469 if (mcspi_wait_for_reg_bit(chstat_reg,
470 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
471 dev_err(&spi->dev, "TXS timed out\n");
472 } else if (mcspi_wait_for_reg_bit(chstat_reg,
473 OMAP2_MCSPI_CHSTAT_EOT) < 0)
474 dev_err(&spi->dev, "EOT timed out\n");
475 }
476 out:
477 return count - c;
478 }
479
480 /* called only when no transfer is active to this device */
481 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
482 struct spi_transfer *t)
483 {
484 struct omap2_mcspi_cs *cs = spi->controller_state;
485 struct omap2_mcspi *mcspi;
486 u32 l = 0, div = 0;
487 u8 word_len = spi->bits_per_word;
488
489 mcspi = spi_master_get_devdata(spi->master);
490
491 if (t != NULL && t->bits_per_word)
492 word_len = t->bits_per_word;
493
494 cs->word_len = word_len;
495
496 if (spi->max_speed_hz) {
497 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
498 > spi->max_speed_hz)
499 div++;
500 } else
501 div = 15;
502
503 l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
504
505 /* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
506 * REVISIT: this controller could support SPI_3WIRE mode.
507 */
508 l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
509 l |= OMAP2_MCSPI_CHCONF_DPE0;
510
511 /* wordlength */
512 l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
513 l |= (word_len - 1) << 7;
514
515 /* set chipselect polarity; manage with FORCE */
516 if (!(spi->mode & SPI_CS_HIGH))
517 l |= OMAP2_MCSPI_CHCONF_EPOL; /* active-low; normal */
518 else
519 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
520
521 /* set clock divisor */
522 l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
523 l |= div << 2;
524
525 /* set SPI mode 0..3 */
526 if (spi->mode & SPI_CPOL)
527 l |= OMAP2_MCSPI_CHCONF_POL;
528 else
529 l &= ~OMAP2_MCSPI_CHCONF_POL;
530 if (spi->mode & SPI_CPHA)
531 l |= OMAP2_MCSPI_CHCONF_PHA;
532 else
533 l &= ~OMAP2_MCSPI_CHCONF_PHA;
534
535 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
536
537 dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
538 OMAP2_MCSPI_MAX_FREQ / (1 << div),
539 (spi->mode & SPI_CPHA) ? "trailing" : "leading",
540 (spi->mode & SPI_CPOL) ? "inverted" : "normal");
541
542 return 0;
543 }
544
545 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
546 {
547 struct spi_device *spi = data;
548 struct omap2_mcspi *mcspi;
549 struct omap2_mcspi_dma *mcspi_dma;
550
551 mcspi = spi_master_get_devdata(spi->master);
552 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
553
554 complete(&mcspi_dma->dma_rx_completion);
555
556 /* We must disable the DMA RX request */
557 omap2_mcspi_set_dma_req(spi, 1, 0);
558 }
559
560 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
561 {
562 struct spi_device *spi = data;
563 struct omap2_mcspi *mcspi;
564 struct omap2_mcspi_dma *mcspi_dma;
565
566 mcspi = spi_master_get_devdata(spi->master);
567 mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
568
569 complete(&mcspi_dma->dma_tx_completion);
570
571 /* We must disable the DMA TX request */
572 omap2_mcspi_set_dma_req(spi, 0, 0);
573 }
574
575 static int omap2_mcspi_request_dma(struct spi_device *spi)
576 {
577 struct spi_master *master = spi->master;
578 struct omap2_mcspi *mcspi;
579 struct omap2_mcspi_dma *mcspi_dma;
580
581 mcspi = spi_master_get_devdata(master);
582 mcspi_dma = mcspi->dma_channels + spi->chip_select;
583
584 if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
585 omap2_mcspi_dma_rx_callback, spi,
586 &mcspi_dma->dma_rx_channel)) {
587 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
588 return -EAGAIN;
589 }
590
591 if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
592 omap2_mcspi_dma_tx_callback, spi,
593 &mcspi_dma->dma_tx_channel)) {
594 omap_free_dma(mcspi_dma->dma_rx_channel);
595 mcspi_dma->dma_rx_channel = -1;
596 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
597 return -EAGAIN;
598 }
599
600 init_completion(&mcspi_dma->dma_rx_completion);
601 init_completion(&mcspi_dma->dma_tx_completion);
602
603 return 0;
604 }
605
606 static int omap2_mcspi_setup(struct spi_device *spi)
607 {
608 int ret;
609 struct omap2_mcspi *mcspi;
610 struct omap2_mcspi_dma *mcspi_dma;
611 struct omap2_mcspi_cs *cs = spi->controller_state;
612
613 if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
614 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
615 spi->bits_per_word);
616 return -EINVAL;
617 }
618
619 mcspi = spi_master_get_devdata(spi->master);
620 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
621
622 if (!cs) {
623 cs = kzalloc(sizeof *cs, GFP_KERNEL);
624 if (!cs)
625 return -ENOMEM;
626 cs->base = mcspi->base + spi->chip_select * 0x14;
627 cs->phys = mcspi->phys + spi->chip_select * 0x14;
628 spi->controller_state = cs;
629 }
630
631 if (mcspi_dma->dma_rx_channel == -1
632 || mcspi_dma->dma_tx_channel == -1) {
633 ret = omap2_mcspi_request_dma(spi);
634 if (ret < 0)
635 return ret;
636 }
637
638 clk_enable(mcspi->ick);
639 clk_enable(mcspi->fck);
640 ret = omap2_mcspi_setup_transfer(spi, NULL);
641 clk_disable(mcspi->fck);
642 clk_disable(mcspi->ick);
643
644 return ret;
645 }
646
647 static void omap2_mcspi_cleanup(struct spi_device *spi)
648 {
649 struct omap2_mcspi *mcspi;
650 struct omap2_mcspi_dma *mcspi_dma;
651
652 mcspi = spi_master_get_devdata(spi->master);
653 mcspi_dma = &mcspi->dma_channels[spi->chip_select];
654
655 kfree(spi->controller_state);
656
657 if (mcspi_dma->dma_rx_channel != -1) {
658 omap_free_dma(mcspi_dma->dma_rx_channel);
659 mcspi_dma->dma_rx_channel = -1;
660 }
661 if (mcspi_dma->dma_tx_channel != -1) {
662 omap_free_dma(mcspi_dma->dma_tx_channel);
663 mcspi_dma->dma_tx_channel = -1;
664 }
665 }
666
667 static void omap2_mcspi_work(struct work_struct *work)
668 {
669 struct omap2_mcspi *mcspi;
670
671 mcspi = container_of(work, struct omap2_mcspi, work);
672 spin_lock_irq(&mcspi->lock);
673
674 clk_enable(mcspi->ick);
675 clk_enable(mcspi->fck);
676
677 /* We only enable one channel at a time -- the one whose message is
678 * at the head of the queue -- although this controller would gladly
679 * arbitrate among multiple channels. This corresponds to "single
680 * channel" master mode. As a side effect, we need to manage the
681 * chipselect with the FORCE bit ... CS != channel enable.
682 */
683 while (!list_empty(&mcspi->msg_queue)) {
684 struct spi_message *m;
685 struct spi_device *spi;
686 struct spi_transfer *t = NULL;
687 int cs_active = 0;
688 struct omap2_mcspi_cs *cs;
689 int par_override = 0;
690 int status = 0;
691 u32 chconf;
692
693 m = container_of(mcspi->msg_queue.next, struct spi_message,
694 queue);
695
696 list_del_init(&m->queue);
697 spin_unlock_irq(&mcspi->lock);
698
699 spi = m->spi;
700 cs = spi->controller_state;
701
702 omap2_mcspi_set_enable(spi, 1);
703 list_for_each_entry(t, &m->transfers, transfer_list) {
704 if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
705 status = -EINVAL;
706 break;
707 }
708 if (par_override || t->speed_hz || t->bits_per_word) {
709 par_override = 1;
710 status = omap2_mcspi_setup_transfer(spi, t);
711 if (status < 0)
712 break;
713 if (!t->speed_hz && !t->bits_per_word)
714 par_override = 0;
715 }
716
717 if (!cs_active) {
718 omap2_mcspi_force_cs(spi, 1);
719 cs_active = 1;
720 }
721
722 chconf = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
723 chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
724 if (t->tx_buf == NULL)
725 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
726 else if (t->rx_buf == NULL)
727 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
728 mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, chconf);
729
730 if (t->len) {
731 unsigned count;
732
733 /* RX_ONLY mode needs dummy data in TX reg */
734 if (t->tx_buf == NULL)
735 __raw_writel(0, cs->base
736 + OMAP2_MCSPI_TX0);
737
738 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
739 count = omap2_mcspi_txrx_dma(spi, t);
740 else
741 count = omap2_mcspi_txrx_pio(spi, t);
742 m->actual_length += count;
743
744 if (count != t->len) {
745 status = -EIO;
746 break;
747 }
748 }
749
750 if (t->delay_usecs)
751 udelay(t->delay_usecs);
752
753 /* ignore the "leave it on after last xfer" hint */
754 if (t->cs_change) {
755 omap2_mcspi_force_cs(spi, 0);
756 cs_active = 0;
757 }
758 }
759
760 /* Restore defaults if they were overriden */
761 if (par_override) {
762 par_override = 0;
763 status = omap2_mcspi_setup_transfer(spi, NULL);
764 }
765
766 if (cs_active)
767 omap2_mcspi_force_cs(spi, 0);
768
769 omap2_mcspi_set_enable(spi, 0);
770
771 m->status = status;
772 m->complete(m->context);
773
774 spin_lock_irq(&mcspi->lock);
775 }
776
777 clk_disable(mcspi->fck);
778 clk_disable(mcspi->ick);
779
780 spin_unlock_irq(&mcspi->lock);
781 }
782
783 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
784 {
785 struct omap2_mcspi *mcspi;
786 unsigned long flags;
787 struct spi_transfer *t;
788
789 m->actual_length = 0;
790 m->status = 0;
791
792 /* reject invalid messages and transfers */
793 if (list_empty(&m->transfers) || !m->complete)
794 return -EINVAL;
795 list_for_each_entry(t, &m->transfers, transfer_list) {
796 const void *tx_buf = t->tx_buf;
797 void *rx_buf = t->rx_buf;
798 unsigned len = t->len;
799
800 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
801 || (len && !(rx_buf || tx_buf))
802 || (t->bits_per_word &&
803 ( t->bits_per_word < 4
804 || t->bits_per_word > 32))) {
805 dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
806 t->speed_hz,
807 len,
808 tx_buf ? "tx" : "",
809 rx_buf ? "rx" : "",
810 t->bits_per_word);
811 return -EINVAL;
812 }
813 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
814 dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
815 t->speed_hz,
816 OMAP2_MCSPI_MAX_FREQ/(1<<16));
817 return -EINVAL;
818 }
819
820 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
821 continue;
822
823 /* Do DMA mapping "early" for better error reporting and
824 * dcache use. Note that if dma_unmap_single() ever starts
825 * to do real work on ARM, we'd need to clean up mappings
826 * for previous transfers on *ALL* exits of this loop...
827 */
828 if (tx_buf != NULL) {
829 t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
830 len, DMA_TO_DEVICE);
831 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
832 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
833 'T', len);
834 return -EINVAL;
835 }
836 }
837 if (rx_buf != NULL) {
838 t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
839 DMA_FROM_DEVICE);
840 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
841 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
842 'R', len);
843 if (tx_buf != NULL)
844 dma_unmap_single(NULL, t->tx_dma,
845 len, DMA_TO_DEVICE);
846 return -EINVAL;
847 }
848 }
849 }
850
851 mcspi = spi_master_get_devdata(spi->master);
852
853 spin_lock_irqsave(&mcspi->lock, flags);
854 list_add_tail(&m->queue, &mcspi->msg_queue);
855 queue_work(omap2_mcspi_wq, &mcspi->work);
856 spin_unlock_irqrestore(&mcspi->lock, flags);
857
858 return 0;
859 }
860
861 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
862 {
863 struct spi_master *master = mcspi->master;
864 u32 tmp;
865
866 clk_enable(mcspi->ick);
867 clk_enable(mcspi->fck);
868
869 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
870 OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
871 do {
872 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
873 } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
874
875 mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
876 /* (3 << 8) | (2 << 3) | */
877 OMAP2_MCSPI_SYSCONFIG_AUTOIDLE);
878
879 omap2_mcspi_set_master_mode(master);
880
881 clk_disable(mcspi->fck);
882 clk_disable(mcspi->ick);
883 return 0;
884 }
885
886 static u8 __initdata spi1_rxdma_id [] = {
887 OMAP24XX_DMA_SPI1_RX0,
888 OMAP24XX_DMA_SPI1_RX1,
889 OMAP24XX_DMA_SPI1_RX2,
890 OMAP24XX_DMA_SPI1_RX3,
891 };
892
893 static u8 __initdata spi1_txdma_id [] = {
894 OMAP24XX_DMA_SPI1_TX0,
895 OMAP24XX_DMA_SPI1_TX1,
896 OMAP24XX_DMA_SPI1_TX2,
897 OMAP24XX_DMA_SPI1_TX3,
898 };
899
900 static u8 __initdata spi2_rxdma_id[] = {
901 OMAP24XX_DMA_SPI2_RX0,
902 OMAP24XX_DMA_SPI2_RX1,
903 };
904
905 static u8 __initdata spi2_txdma_id[] = {
906 OMAP24XX_DMA_SPI2_TX0,
907 OMAP24XX_DMA_SPI2_TX1,
908 };
909
910 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
911 static u8 __initdata spi3_rxdma_id[] = {
912 OMAP24XX_DMA_SPI3_RX0,
913 OMAP24XX_DMA_SPI3_RX1,
914 };
915
916 static u8 __initdata spi3_txdma_id[] = {
917 OMAP24XX_DMA_SPI3_TX0,
918 OMAP24XX_DMA_SPI3_TX1,
919 };
920 #endif
921
922 #ifdef CONFIG_ARCH_OMAP3
923 static u8 __initdata spi4_rxdma_id[] = {
924 OMAP34XX_DMA_SPI4_RX0,
925 };
926
927 static u8 __initdata spi4_txdma_id[] = {
928 OMAP34XX_DMA_SPI4_TX0,
929 };
930 #endif
931
932 static int __init omap2_mcspi_probe(struct platform_device *pdev)
933 {
934 struct spi_master *master;
935 struct omap2_mcspi *mcspi;
936 struct resource *r;
937 int status = 0, i;
938 const u8 *rxdma_id, *txdma_id;
939 unsigned num_chipselect;
940
941 switch (pdev->id) {
942 case 1:
943 rxdma_id = spi1_rxdma_id;
944 txdma_id = spi1_txdma_id;
945 num_chipselect = 4;
946 break;
947 case 2:
948 rxdma_id = spi2_rxdma_id;
949 txdma_id = spi2_txdma_id;
950 num_chipselect = 2;
951 break;
952 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
953 case 3:
954 rxdma_id = spi3_rxdma_id;
955 txdma_id = spi3_txdma_id;
956 num_chipselect = 2;
957 break;
958 #endif
959 #ifdef CONFIG_ARCH_OMAP3
960 case 4:
961 rxdma_id = spi4_rxdma_id;
962 txdma_id = spi4_txdma_id;
963 num_chipselect = 1;
964 break;
965 #endif
966 default:
967 return -EINVAL;
968 }
969
970 master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
971 if (master == NULL) {
972 dev_dbg(&pdev->dev, "master allocation failed\n");
973 return -ENOMEM;
974 }
975
976 /* the spi->mode bits understood by this driver: */
977 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
978
979 if (pdev->id != -1)
980 master->bus_num = pdev->id;
981
982 master->setup = omap2_mcspi_setup;
983 master->transfer = omap2_mcspi_transfer;
984 master->cleanup = omap2_mcspi_cleanup;
985 master->num_chipselect = num_chipselect;
986
987 dev_set_drvdata(&pdev->dev, master);
988
989 mcspi = spi_master_get_devdata(master);
990 mcspi->master = master;
991
992 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
993 if (r == NULL) {
994 status = -ENODEV;
995 goto err1;
996 }
997 if (!request_mem_region(r->start, (r->end - r->start) + 1,
998 dev_name(&pdev->dev))) {
999 status = -EBUSY;
1000 goto err1;
1001 }
1002
1003 mcspi->phys = r->start;
1004 mcspi->base = ioremap(r->start, r->end - r->start + 1);
1005 if (!mcspi->base) {
1006 dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
1007 status = -ENOMEM;
1008 goto err1aa;
1009 }
1010
1011 INIT_WORK(&mcspi->work, omap2_mcspi_work);
1012
1013 spin_lock_init(&mcspi->lock);
1014 INIT_LIST_HEAD(&mcspi->msg_queue);
1015
1016 mcspi->ick = clk_get(&pdev->dev, "ick");
1017 if (IS_ERR(mcspi->ick)) {
1018 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1019 status = PTR_ERR(mcspi->ick);
1020 goto err1a;
1021 }
1022 mcspi->fck = clk_get(&pdev->dev, "fck");
1023 if (IS_ERR(mcspi->fck)) {
1024 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1025 status = PTR_ERR(mcspi->fck);
1026 goto err2;
1027 }
1028
1029 mcspi->dma_channels = kcalloc(master->num_chipselect,
1030 sizeof(struct omap2_mcspi_dma),
1031 GFP_KERNEL);
1032
1033 if (mcspi->dma_channels == NULL)
1034 goto err3;
1035
1036 for (i = 0; i < num_chipselect; i++) {
1037 mcspi->dma_channels[i].dma_rx_channel = -1;
1038 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1039 mcspi->dma_channels[i].dma_tx_channel = -1;
1040 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1041 }
1042
1043 if (omap2_mcspi_reset(mcspi) < 0)
1044 goto err4;
1045
1046 status = spi_register_master(master);
1047 if (status < 0)
1048 goto err4;
1049
1050 return status;
1051
1052 err4:
1053 kfree(mcspi->dma_channels);
1054 err3:
1055 clk_put(mcspi->fck);
1056 err2:
1057 clk_put(mcspi->ick);
1058 err1a:
1059 iounmap(mcspi->base);
1060 err1aa:
1061 release_mem_region(r->start, (r->end - r->start) + 1);
1062 err1:
1063 spi_master_put(master);
1064 return status;
1065 }
1066
1067 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1068 {
1069 struct spi_master *master;
1070 struct omap2_mcspi *mcspi;
1071 struct omap2_mcspi_dma *dma_channels;
1072 struct resource *r;
1073 void __iomem *base;
1074
1075 master = dev_get_drvdata(&pdev->dev);
1076 mcspi = spi_master_get_devdata(master);
1077 dma_channels = mcspi->dma_channels;
1078
1079 clk_put(mcspi->fck);
1080 clk_put(mcspi->ick);
1081
1082 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1083 release_mem_region(r->start, (r->end - r->start) + 1);
1084
1085 base = mcspi->base;
1086 spi_unregister_master(master);
1087 iounmap(base);
1088 kfree(dma_channels);
1089
1090 return 0;
1091 }
1092
1093 /* work with hotplug and coldplug */
1094 MODULE_ALIAS("platform:omap2_mcspi");
1095
1096 static struct platform_driver omap2_mcspi_driver = {
1097 .driver = {
1098 .name = "omap2_mcspi",
1099 .owner = THIS_MODULE,
1100 },
1101 .remove = __exit_p(omap2_mcspi_remove),
1102 };
1103
1104
1105 static int __init omap2_mcspi_init(void)
1106 {
1107 omap2_mcspi_wq = create_singlethread_workqueue(
1108 omap2_mcspi_driver.driver.name);
1109 if (omap2_mcspi_wq == NULL)
1110 return -1;
1111 return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1112 }
1113 subsys_initcall(omap2_mcspi_init);
1114
1115 static void __exit omap2_mcspi_exit(void)
1116 {
1117 platform_driver_unregister(&omap2_mcspi_driver);
1118
1119 destroy_workqueue(omap2_mcspi_wq);
1120 }
1121 module_exit(omap2_mcspi_exit);
1122
1123 MODULE_LICENSE("GPL");
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