drivers/gpio/gpio-mxs.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  20  * MA  02110-1301, USA.
  21  */
  22
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/gpio.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/slab.h>
  30 #include <linux/basic_mmio_gpio.h>
  31 #include <mach/mxs.h>
  32
  33 #define MXS_SET         0x4
  34 #define MXS_CLR         0x8
  35
  36 #define PINCTRL_DOUT(n)         ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
  37 #define PINCTRL_DIN(n)          ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
  38 #define PINCTRL_DOE(n)          ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
  39 #define PINCTRL_PIN2IRQ(n)      ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
  40 #define PINCTRL_IRQEN(n)        ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
  41 #define PINCTRL_IRQLEV(n)       ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
  42 #define PINCTRL_IRQPOL(n)       ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
  43 #define PINCTRL_IRQSTAT(n)      ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
  44
  45 #define GPIO_INT_FALL_EDGE      0x0
  46 #define GPIO_INT_LOW_LEV        0x1
  47 #define GPIO_INT_RISE_EDGE      0x2
  48 #define GPIO_INT_HIGH_LEV       0x3
  49 #define GPIO_INT_LEV_MASK       (1 << 0)
  50 #define GPIO_INT_POL_MASK       (1 << 1)
  51
  52 struct mxs_gpio_port {
  53         void __iomem *base;
  54         int id;
  55         int irq;
  56         int virtual_irq_start;
  57         struct bgpio_chip bgc;
  58 };
  59
  60 /* Note: This driver assumes 32 GPIOs are handled in one register */
  61
  62 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
  63 {
  64         u32 gpio = irq_to_gpio(d->irq);
  65         u32 pin_mask = 1 << (gpio & 31);
  66         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
  67         struct mxs_gpio_port *port = gc->private;
  68         void __iomem *pin_addr;
  69         int edge;
  70
  71         switch (type) {
  72         case IRQ_TYPE_EDGE_RISING:
  73                 edge = GPIO_INT_RISE_EDGE;
  74                 break;
  75         case IRQ_TYPE_EDGE_FALLING:
  76                 edge = GPIO_INT_FALL_EDGE;
  77                 break;
  78         case IRQ_TYPE_LEVEL_LOW:
  79                 edge = GPIO_INT_LOW_LEV;
  80                 break;
  81         case IRQ_TYPE_LEVEL_HIGH:
  82                 edge = GPIO_INT_HIGH_LEV;
  83                 break;
  84         default:
  85                 return -EINVAL;
  86         }
  87
  88         /* set level or edge */
  89         pin_addr = port->base + PINCTRL_IRQLEV(port->id);
  90         if (edge & GPIO_INT_LEV_MASK)
  91                 writel(pin_mask, pin_addr + MXS_SET);
  92         else
  93                 writel(pin_mask, pin_addr + MXS_CLR);
  94
  95         /* set polarity */
  96         pin_addr = port->base + PINCTRL_IRQPOL(port->id);
  97         if (edge & GPIO_INT_POL_MASK)
  98                 writel(pin_mask, pin_addr + MXS_SET);
  99         else
 100                 writel(pin_mask, pin_addr + MXS_CLR);
 101
 102         writel(1 << (gpio & 0x1f),
 103                port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 104
 105         return 0;
 106 }
 107
 108 /* MXS has one interrupt *per* gpio port */
 109 static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 110 {
 111         u32 irq_stat;
 112         struct mxs_gpio_port *port = irq_get_handler_data(irq);
 113         u32 gpio_irq_no_base = port->virtual_irq_start;
 114
 115         desc->irq_data.chip->irq_ack(&desc->irq_data);
 116
 117         irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) &
 118                         readl(port->base + PINCTRL_IRQEN(port->id));
 119
 120         while (irq_stat != 0) {
 121                 int irqoffset = fls(irq_stat) - 1;
 122                 generic_handle_irq(gpio_irq_no_base + irqoffset);
 123                 irq_stat &= ~(1 << irqoffset);
 124         }
 125 }
 126
 127 /*
 128  * Set interrupt number "irq" in the GPIO as a wake-up source.
 129  * While system is running, all registered GPIO interrupts need to have
 130  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 131  * need to have wake-up enabled.
 132  * @param  irq          interrupt source number
 133  * @param  enable       enable as wake-up if equal to non-zero
 134  * @return       This function returns 0 on success.
 135  */
 136 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable)
 137 {
 138         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 139         struct mxs_gpio_port *port = gc->private;
 140
 141         if (enable)
 142                 enable_irq_wake(port->irq);
 143         else
 144                 disable_irq_wake(port->irq);
 145
 146         return 0;
 147 }
 148
 149 static void __init mxs_gpio_init_gc(struct mxs_gpio_port *port)
 150 {
 151         struct irq_chip_generic *gc;
 152         struct irq_chip_type *ct;
 153
 154         gc = irq_alloc_generic_chip("gpio-mxs", 1, port->virtual_irq_start,
 155                                     port->base, handle_level_irq);
 156         gc->private = port;
 157
 158         ct = gc->chip_types;
 159         ct->chip.irq_ack = irq_gc_ack_set_bit;
 160         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 161         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 162         ct->chip.irq_set_type = mxs_gpio_set_irq_type;
 163         ct->chip.irq_set_wake = mxs_gpio_set_wake_irq;
 164         ct->regs.ack = PINCTRL_IRQSTAT(port->id) + MXS_CLR;
 165         ct->regs.mask = PINCTRL_IRQEN(port->id);
 166
 167         irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 168 }
 169
 170 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 171 {
 172         struct bgpio_chip *bgc = to_bgpio_chip(gc);
 173         struct mxs_gpio_port *port =
 174                 container_of(bgc, struct mxs_gpio_port, bgc);
 175
 176         return port->virtual_irq_start + offset;
 177 }
 178
 179 static int __devinit mxs_gpio_probe(struct platform_device *pdev)
 180 {
 181         static void __iomem *base;
 182         struct mxs_gpio_port *port;
 183         struct resource *iores = NULL;
 184         int err;
 185
 186         port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL);
 187         if (!port)
 188                 return -ENOMEM;
 189
 190         port->id = pdev->id;
 191         port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32;
 192
 193         /*
 194          * map memory region only once, as all the gpio ports
 195          * share the same one
 196          */
 197         if (!base) {
 198                 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 199                 if (!iores) {
 200                         err = -ENODEV;
 201                         goto out_kfree;
 202                 }
 203
 204                 if (!request_mem_region(iores->start, resource_size(iores),
 205                                         pdev->name)) {
 206                         err = -EBUSY;
 207                         goto out_kfree;
 208                 }
 209
 210                 base = ioremap(iores->start, resource_size(iores));
 211                 if (!base) {
 212                         err = -ENOMEM;
 213                         goto out_release_mem;
 214                 }
 215         }
 216         port->base = base;
 217
 218         port->irq = platform_get_irq(pdev, 0);
 219         if (port->irq < 0) {
 220                 err = -EINVAL;
 221                 goto out_iounmap;
 222         }
 223
 224         /*
 225          * select the pin interrupt functionality but initially
 226          * disable the interrupts
 227          */
 228         writel(~0U, port->base + PINCTRL_PIN2IRQ(port->id));
 229         writel(0, port->base + PINCTRL_IRQEN(port->id));
 230
 231         /* clear address has to be used to clear IRQSTAT bits */
 232         writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR);
 233
 234         /* gpio-mxs can be a generic irq chip */
 235         mxs_gpio_init_gc(port);
 236
 237         /* setup one handler for each entry */
 238         irq_set_chained_handler(port->irq, mxs_gpio_irq_handler);
 239         irq_set_handler_data(port->irq, port);
 240
 241         err = bgpio_init(&port->bgc, &pdev->dev, 4,
 242                          port->base + PINCTRL_DIN(port->id),
 243                          port->base + PINCTRL_DOUT(port->id), NULL,
 244                          port->base + PINCTRL_DOE(port->id), NULL, false);
 245         if (err)
 246                 goto out_iounmap;
 247
 248         port->bgc.gc.to_irq = mxs_gpio_to_irq;
 249         port->bgc.gc.base = port->id * 32;
 250
 251         err = gpiochip_add(&port->bgc.gc);
 252         if (err)
 253                 goto out_bgpio_remove;
 254
 255         return 0;
 256
 257 out_bgpio_remove:
 258         bgpio_remove(&port->bgc);
 259 out_iounmap:
 260         if (iores)
 261                 iounmap(port->base);
 262 out_release_mem:
 263         if (iores)
 264                 release_mem_region(iores->start, resource_size(iores));
 265 out_kfree:
 266         kfree(port);
 267         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 268         return err;
 269 }
 270
 271 static struct platform_driver mxs_gpio_driver = {
 272         .driver         = {
 273                 .name   = "gpio-mxs",
 274                 .owner  = THIS_MODULE,
 275         },
 276         .probe          = mxs_gpio_probe,
 277 };
 278
 279 static int __init mxs_gpio_init(void)
 280 {
 281         return platform_driver_register(&mxs_gpio_driver);
 282 }
 283 postcore_initcall(mxs_gpio_init);
 284
 285 MODULE_AUTHOR("Freescale Semiconductor, "
 286               "Daniel Mack <danielncaiaq.de>, "
 287               "Juergen Beisert <kernel@pengutronix.de>");
 288 MODULE_DESCRIPTION("Freescale MXS GPIO");
 289 MODULE_LICENSE("GPL");