arch/arm/mach-s3c2443/clock.c

   1 /* linux/arch/arm/mach-s3c2443/clock.c
   2  *
   3  * Copyright (c) 2007, 2010 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2443 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/init.h>
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/errno.h>
  29 #include <linux/err.h>
  30 #include <linux/sysdev.h>
  31 #include <linux/clk.h>
  32 #include <linux/mutex.h>
  33 #include <linux/serial_core.h>
  34 #include <linux/io.h>
  35
  36 #include <asm/mach/map.h>
  37
  38 #include <mach/hardware.h>
  39
  40 #include <mach/regs-s3c2443-clock.h>
  41
  42 #include <plat/cpu-freq.h>
  43
  44 #include <plat/s3c2443.h>
  45 #include <plat/clock.h>
  46 #include <plat/clock-clksrc.h>
  47 #include <plat/cpu.h>
  48
  49 /* We currently have to assume that the system is running
  50  * from the XTPll input, and that all ***REFCLKs are being
  51  * fed from it, as we cannot read the state of OM[4] from
  52  * software.
  53  *
  54  * It would be possible for each board initialisation to
  55  * set the correct muxing at initialisation
  56 */
  57
  58 /* clock selections */
  59
  60 static struct clk clk_i2s_ext = {
  61         .name           = "i2s-ext",
  62 };
  63
  64 /* armdiv
  65  *
  66  * this clock is sourced from msysclk and can have a number of
  67  * divider values applied to it to then be fed into armclk.
  68 */
  69
  70 /* armdiv divisor table */
  71
  72 static unsigned int armdiv[16] = {
  73         [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 1,
  74         [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 2,
  75         [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 3,
  76         [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 4,
  77         [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 6,
  78         [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 8,
  79         [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]     = 12,
  80         [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]     = 16,
  81 };
  82
  83 static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
  84 {
  85         clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
  86
  87         return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
  88 }
  89
  90 static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
  91                                               unsigned long rate)
  92 {
  93         unsigned long parent = clk_get_rate(clk->parent);
  94         unsigned long calc;
  95         unsigned best = 256; /* bigger than any value */
  96         unsigned div;
  97         int ptr;
  98
  99         for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
 100                 div = armdiv[ptr];
 101                 calc = parent / div;
 102                 if (calc <= rate && div < best)
 103                         best = div;
 104         }
 105
 106         return parent / best;
 107 }
 108
 109 static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
 110 {
 111         unsigned long parent = clk_get_rate(clk->parent);
 112         unsigned long calc;
 113         unsigned div;
 114         unsigned best = 256; /* bigger than any value */
 115         int ptr;
 116         int val = -1;
 117
 118         for (ptr = 0; ptr < ARRAY_SIZE(armdiv); ptr++) {
 119                 div = armdiv[ptr];
 120                 calc = parent / div;
 121                 if (calc <= rate && div < best) {
 122                         best = div;
 123                         val = ptr;
 124                 }
 125         }
 126
 127         if (val >= 0) {
 128                 unsigned long clkcon0;
 129
 130                 clkcon0 = __raw_readl(S3C2443_CLKDIV0);
 131                 clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
 132                 clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
 133                 __raw_writel(clkcon0, S3C2443_CLKDIV0);
 134         }
 135
 136         return (val == -1) ? -EINVAL : 0;
 137 }
 138
 139 static struct clk clk_armdiv = {
 140         .name           = "armdiv",
 141         .parent         = &clk_msysclk.clk,
 142         .ops            = &(struct clk_ops) {
 143                 .round_rate = s3c2443_armclk_roundrate,
 144                 .set_rate = s3c2443_armclk_setrate,
 145         },
 146 };
 147
 148 /* armclk
 149  *
 150  * this is the clock fed into the ARM core itself, from armdiv or from hclk.
 151  */
 152
 153 static struct clk *clk_arm_sources[] = {
 154         [0] = &clk_armdiv,
 155         [1] = &clk_h,
 156 };
 157
 158 static struct clksrc_clk clk_arm = {
 159         .clk    = {
 160                 .name           = "armclk",
 161         },
 162         .sources = &(struct clksrc_sources) {
 163                 .sources = clk_arm_sources,
 164                 .nr_sources = ARRAY_SIZE(clk_arm_sources),
 165         },
 166         .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
 167 };
 168
 169 /* hsspi
 170  *
 171  * high-speed spi clock, sourced from esysclk
 172 */
 173
 174 static struct clksrc_clk clk_hsspi = {
 175         .clk    = {
 176                 .name           = "hsspi",
 177                 .parent         = &clk_esysclk.clk,
 178                 .ctrlbit        = S3C2443_SCLKCON_HSSPICLK,
 179                 .enable         = s3c2443_clkcon_enable_s,
 180         },
 181         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
 182 };
 183
 184
 185 /* clk_hsmcc_div
 186  *
 187  * this clock is sourced from epll, and is fed through a divider,
 188  * to a mux controlled by sclkcon where either it or a extclk can
 189  * be fed to the hsmmc block
 190 */
 191
 192 static struct clksrc_clk clk_hsmmc_div = {
 193         .clk    = {
 194                 .name           = "hsmmc-div",
 195                 .devname        = "s3c-sdhci.1",
 196                 .parent         = &clk_esysclk.clk,
 197         },
 198         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
 199 };
 200
 201 static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
 202 {
 203         unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
 204
 205         clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
 206                     S3C2443_SCLKCON_HSMMCCLK_EPLL);
 207
 208         if (parent == &clk_epll)
 209                 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
 210         else if (parent == &clk_ext)
 211                 clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
 212         else
 213                 return -EINVAL;
 214
 215         if (clk->usage > 0) {
 216                 __raw_writel(clksrc, S3C2443_SCLKCON);
 217         }
 218
 219         clk->parent = parent;
 220         return 0;
 221 }
 222
 223 static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
 224 {
 225         return s3c2443_setparent_hsmmc(clk, clk->parent);
 226 }
 227
 228 static struct clk clk_hsmmc = {
 229         .name           = "hsmmc-if",
 230         .devname        = "s3c-sdhci.1",
 231         .parent         = &clk_hsmmc_div.clk,
 232         .enable         = s3c2443_enable_hsmmc,
 233         .ops            = &(struct clk_ops) {
 234                 .set_parent     = s3c2443_setparent_hsmmc,
 235         },
 236 };
 237
 238 /* i2s_eplldiv
 239  *
 240  * This clock is the output from the I2S divisor of ESYSCLK, and is separate
 241  * from the mux that comes after it (cannot merge into one single clock)
 242 */
 243
 244 static struct clksrc_clk clk_i2s_eplldiv = {
 245         .clk    = {
 246                 .name           = "i2s-eplldiv",
 247                 .parent         = &clk_esysclk.clk,
 248         },
 249         .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
 250 };
 251
 252 /* i2s-ref
 253  *
 254  * i2s bus reference clock, selectable from external, esysclk or epllref
 255  *
 256  * Note, this used to be two clocks, but was compressed into one.
 257 */
 258
 259 struct clk *clk_i2s_srclist[] = {
 260         [0] = &clk_i2s_eplldiv.clk,
 261         [1] = &clk_i2s_ext,
 262         [2] = &clk_epllref.clk,
 263         [3] = &clk_epllref.clk,
 264 };
 265
 266 static struct clksrc_clk clk_i2s = {
 267         .clk    = {
 268                 .name           = "i2s-if",
 269                 .ctrlbit        = S3C2443_SCLKCON_I2SCLK,
 270                 .enable         = s3c2443_clkcon_enable_s,
 271
 272         },
 273         .sources = &(struct clksrc_sources) {
 274                 .sources = clk_i2s_srclist,
 275                 .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
 276         },
 277         .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
 278 };
 279
 280 /* standard clock definitions */
 281
 282 static struct clk init_clocks_off[] = {
 283         {
 284                 .name           = "sdi",
 285                 .parent         = &clk_p,
 286                 .enable         = s3c2443_clkcon_enable_p,
 287                 .ctrlbit        = S3C2443_PCLKCON_SDI,
 288         }, {
 289                 .name           = "iis",
 290                 .parent         = &clk_p,
 291                 .enable         = s3c2443_clkcon_enable_p,
 292                 .ctrlbit        = S3C2443_PCLKCON_IIS,
 293         }, {
 294                 .name           = "spi",
 295                 .devname        = "s3c2410-spi.0",
 296                 .parent         = &clk_p,
 297                 .enable         = s3c2443_clkcon_enable_p,
 298                 .ctrlbit        = S3C2443_PCLKCON_SPI0,
 299         }, {
 300                 .name           = "spi",
 301                 .devname        = "s3c2410-spi.1",
 302                 .parent         = &clk_p,
 303                 .enable         = s3c2443_clkcon_enable_p,
 304                 .ctrlbit        = S3C2443_PCLKCON_SPI1,
 305         }
 306 };
 307
 308 static struct clk init_clocks[] = {
 309 };
 310
 311 /* clocks to add straight away */
 312
 313 static struct clksrc_clk *clksrcs[] __initdata = {
 314         &clk_arm,
 315         &clk_i2s_eplldiv,
 316         &clk_i2s,
 317         &clk_hsspi,
 318         &clk_hsmmc_div,
 319 };
 320
 321 static struct clk *clks[] __initdata = {
 322         &clk_hsmmc,
 323         &clk_armdiv,
 324 };
 325
 326 void __init_or_cpufreq s3c2443_setup_clocks(void)
 327 {
 328         s3c2443_common_setup_clocks(s3c2443_get_mpll, s3c2443_fclk_div);
 329 }
 330
 331 void __init s3c2443_init_clocks(int xtal)
 332 {
 333         unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
 334         int ptr;
 335
 336         clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
 337         clk_epll.parent = &clk_epllref.clk;
 338
 339         s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, s3c2443_fclk_div);
 340
 341         s3c2443_setup_clocks();
 342
 343         s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
 344
 345         for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 346                 s3c_register_clksrc(clksrcs[ptr], 1);
 347
 348         /* register clocks from clock array */
 349
 350         s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
 351
 352         /* We must be careful disabling the clocks we are not intending to
 353          * be using at boot time, as subsystems such as the LCD which do
 354          * their own DMA requests to the bus can cause the system to lockup
 355          * if they where in the middle of requesting bus access.
 356          *
 357          * Disabling the LCD clock if the LCD is active is very dangerous,
 358          * and therefore the bootloader should be careful to not enable
 359          * the LCD clock if it is not needed.
 360         */
 361
 362         /* install (and disable) the clocks we do not need immediately */
 363
 364         s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 365         s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
 366
 367         s3c_pwmclk_init();
 368 }