drivers/scsi/mesh.h

   1 /*
   2  * mesh.h: definitions for the driver for the MESH SCSI bus adaptor
   3  * (Macintosh Enhanced SCSI Hardware) found on Power Macintosh computers.
   4  *
   5  * Copyright (C) 1996 Paul Mackerras.
   6  */
   7 #ifndef _MESH_H
   8 #define _MESH_H
   9
  10 /*
  11  * Registers in the MESH controller.
  12  */
  13
  14 struct mesh_regs {
  15         unsigned char   count_lo;
  16         char pad0[15];
  17         unsigned char   count_hi;
  18         char pad1[15];
  19         unsigned char   fifo;
  20         char pad2[15];
  21         unsigned char   sequence;
  22         char pad3[15];
  23         unsigned char   bus_status0;
  24         char pad4[15];
  25         unsigned char   bus_status1;
  26         char pad5[15];
  27         unsigned char   fifo_count;
  28         char pad6[15];
  29         unsigned char   exception;
  30         char pad7[15];
  31         unsigned char   error;
  32         char pad8[15];
  33         unsigned char   intr_mask;
  34         char pad9[15];
  35         unsigned char   interrupt;
  36         char pad10[15];
  37         unsigned char   source_id;
  38         char pad11[15];
  39         unsigned char   dest_id;
  40         char pad12[15];
  41         unsigned char   sync_params;
  42         char pad13[15];
  43         unsigned char   mesh_id;
  44         char pad14[15];
  45         unsigned char   sel_timeout;
  46         char pad15[15];
  47 };
  48
  49 /* Bits in the sequence register. */
  50 #define SEQ_DMA_MODE    0x80    /* use DMA for data transfer */
  51 #define SEQ_TARGET      0x40    /* put the controller into target mode */
  52 #define SEQ_ATN         0x20    /* assert ATN signal */
  53 #define SEQ_ACTIVE_NEG  0x10    /* use active negation on REQ/ACK */
  54 #define SEQ_CMD         0x0f    /* command bits: */
  55 #define SEQ_ARBITRATE   1       /*  get the bus */
  56 #define SEQ_SELECT      2       /*  select a target */
  57 #define SEQ_COMMAND     3       /*  send a command */
  58 #define SEQ_STATUS      4       /*  receive status */
  59 #define SEQ_DATAOUT     5       /*  send data */
  60 #define SEQ_DATAIN      6       /*  receive data */
  61 #define SEQ_MSGOUT      7       /*  send a message */
  62 #define SEQ_MSGIN       8       /*  receive a message */
  63 #define SEQ_BUSFREE     9       /*  look for bus free */
  64 #define SEQ_ENBPARITY   0x0a    /*  enable parity checking */
  65 #define SEQ_DISPARITY   0x0b    /*  disable parity checking */
  66 #define SEQ_ENBRESEL    0x0c    /*  enable reselection */
  67 #define SEQ_DISRESEL    0x0d    /*  disable reselection */
  68 #define SEQ_RESETMESH   0x0e    /*  reset the controller */
  69 #define SEQ_FLUSHFIFO   0x0f    /*  clear out the FIFO */
  70
  71 /* Bits in the bus_status0 and bus_status1 registers:
  72    these correspond directly to the SCSI bus control signals. */
  73 #define BS0_REQ         0x20
  74 #define BS0_ACK         0x10
  75 #define BS0_ATN         0x08
  76 #define BS0_MSG         0x04
  77 #define BS0_CD          0x02
  78 #define BS0_IO          0x01
  79 #define BS1_RST         0x80
  80 #define BS1_BSY         0x40
  81 #define BS1_SEL         0x20
  82
  83 /* Bus phases defined by the bits in bus_status0 */
  84 #define BS0_PHASE       (BS0_MSG+BS0_CD+BS0_IO)
  85 #define BP_DATAOUT      0
  86 #define BP_DATAIN       BS0_IO
  87 #define BP_COMMAND      BS0_CD
  88 #define BP_STATUS       (BS0_CD+BS0_IO)
  89 #define BP_MSGOUT       (BS0_MSG+BS0_CD)
  90 #define BP_MSGIN        (BS0_MSG+BS0_CD+BS0_IO)
  91
  92 /* Bits in the exception register. */
  93 #define EXC_SELWATN     0x20    /* (as target) we were selected with ATN */
  94 #define EXC_SELECTED    0x10    /* (as target) we were selected w/o ATN */
  95 #define EXC_RESELECTED  0x08    /* (as initiator) we were reselected */
  96 #define EXC_ARBLOST     0x04    /* we lost arbitration */
  97 #define EXC_PHASEMM     0x02    /* SCSI phase mismatch */
  98 #define EXC_SELTO       0x01    /* selection timeout */
  99
 100 /* Bits in the error register */
 101 #define ERR_UNEXPDISC   0x40    /* target unexpectedly disconnected */
 102 #define ERR_SCSIRESET   0x20    /* SCSI bus got reset on us */
 103 #define ERR_SEQERR      0x10    /* we did something the chip didn't like */
 104 #define ERR_PARITY      0x01    /* parity error was detected */
 105
 106 /* Bits in the interrupt and intr_mask registers */
 107 #define INT_ERROR       0x04    /* error interrupt */
 108 #define INT_EXCEPTION   0x02    /* exception interrupt */
 109 #define INT_CMDDONE     0x01    /* command done interrupt */
 110
 111 /* Fields in the sync_params register */
 112 #define SYNC_OFF(x)     ((x) >> 4)      /* offset field */
 113 #define SYNC_PER(x)     ((x) & 0xf)     /* period field */
 114 #define SYNC_PARAMS(o, p)       (((o) << 4) | (p))
 115 #define ASYNC_PARAMS    2       /* sync_params value for async xfers */
 116
 117 /*
 118  * Assuming a clock frequency of 50MHz:
 119  *
 120  * The transfer period with SYNC_PER(sync_params) == x
 121  * is (x + 2) * 40ns, except that x == 0 gives 100ns.
 122  *
 123  * The units of the sel_timeout register are 10ms.
 124  */
 125
 126
 127 #endif /* _MESH_H */