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[CPUFREQ] Misc cleanups in ondemand.
[linux-2.6/next.git] / drivers / serial / s3c2410.c
blob4c62ab949ecc3e01aaf04da45ca23cb7d2443a21
1 /*
2 * linux/drivers/serial/s3c2410.c
3 *
4 * Driver for onboard UARTs on the Samsung S3C24XX
5 *
6 * Based on drivers/char/serial.c and drivers/char/21285.c
7 *
8 * Ben Dooks, (c) 2003-2005 Simtec Electronics
9 * http://www.simtec.co.uk/products/SWLINUX/
10 *
11 * Changelog:
12 *
13 * 22-Jul-2004 BJD Finished off device rewrite
14 *
15 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
16 * problems with baud rate and loss of IR settings. Update
17 * to add configuration via platform_device structure
18 *
19 * 28-Sep-2004 BJD Re-write for the following items
20 * - S3C2410 and S3C2440 serial support
21 * - Power Management support
22 * - Fix console via IrDA devices
23 * - SysReq (Herbert Pötzl)
24 * - Break character handling (Herbert Pötzl)
25 * - spin-lock initialisation (Dimitry Andric)
26 * - added clock control
27 * - updated init code to use platform_device info
28 *
29 * 06-Mar-2005 BJD Add s3c2440 fclk clock source
30 *
31 * 09-Mar-2005 BJD Add s3c2400 support
32 *
33 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
34 */
35
36 /* Note on 2440 fclk clock source handling
37 *
38 * Whilst it is possible to use the fclk as clock source, the method
39 * of properly switching too/from this is currently un-implemented, so
40 * whichever way is configured at startup is the one that will be used.
41 */
42
43 /* Hote on 2410 error handling
44 *
45 * The s3c2410 manual has a love/hate affair with the contents of the
46 * UERSTAT register in the UART blocks, and keeps marking some of the
47 * error bits as reserved. Having checked with the s3c2410x01,
48 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
49 * feature from the latter versions of the manual.
50 *
51 * If it becomes aparrent that latter versions of the 2410 remove these
52 * bits, then action will have to be taken to differentiate the versions
53 * and change the policy on BREAK
54 *
55 * BJD, 04-Nov-2004
56 */
57
58 #include <linux/config.h>
59
60 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
61 #define SUPPORT_SYSRQ
62 #endif
63
64 #include <linux/module.h>
65 #include <linux/ioport.h>
66 #include <linux/platform_device.h>
67 #include <linux/init.h>
68 #include <linux/sysrq.h>
69 #include <linux/console.h>
70 #include <linux/tty.h>
71 #include <linux/tty_flip.h>
72 #include <linux/serial_core.h>
73 #include <linux/serial.h>
74 #include <linux/delay.h>
75 #include <linux/clk.h>
76
77 #include <asm/io.h>
78 #include <asm/irq.h>
79
80 #include <asm/hardware.h>
81
82 #include <asm/arch/regs-serial.h>
83 #include <asm/arch/regs-gpio.h>
84
85 /* structures */
86
87 struct s3c24xx_uart_info {
88 char *name;
89 unsigned int type;
90 unsigned int fifosize;
91 unsigned long rx_fifomask;
92 unsigned long rx_fifoshift;
93 unsigned long rx_fifofull;
94 unsigned long tx_fifomask;
95 unsigned long tx_fifoshift;
96 unsigned long tx_fifofull;
97
98 /* clock source control */
99
100 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
101 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
102
103 /* uart controls */
104 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
105 };
106
107 struct s3c24xx_uart_port {
108 unsigned char rx_claimed;
109 unsigned char tx_claimed;
110
111 struct s3c24xx_uart_info *info;
112 struct s3c24xx_uart_clksrc *clksrc;
113 struct clk *clk;
114 struct clk *baudclk;
115 struct uart_port port;
116 };
117
118
119 /* configuration defines */
120
121 #if 0
122 #if 1
123 /* send debug to the low-level output routines */
124
125 extern void printascii(const char *);
126
127 static void
128 s3c24xx_serial_dbg(const char *fmt, ...)
129 {
130 va_list va;
131 char buff[256];
132
133 va_start(va, fmt);
134 vsprintf(buff, fmt, va);
135 va_end(va);
136
137 printascii(buff);
138 }
139
140 #define dbg(x...) s3c24xx_serial_dbg(x)
141
142 #else
143 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
144 #endif
145 #else /* no debug */
146 #define dbg(x...) do {} while(0)
147 #endif
148
149 /* UART name and device definitions */
150
151 #define S3C24XX_SERIAL_NAME "ttySAC"
152 #define S3C24XX_SERIAL_MAJOR 204
153 #define S3C24XX_SERIAL_MINOR 64
154
155
156 /* conversion functions */
157
158 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
159 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
160
161 /* we can support 3 uarts, but not always use them */
162
163 #ifdef CONFIG_CPU_S3C2400
164 #define NR_PORTS (2)
165 #else
166 #define NR_PORTS (3)
167 #endif
168
169 /* port irq numbers */
170
171 #define TX_IRQ(port) ((port)->irq + 1)
172 #define RX_IRQ(port) ((port)->irq)
173
174 /* register access controls */
175
176 #define portaddr(port, reg) ((port)->membase + (reg))
177
178 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
179 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
180
181 #define wr_regb(port, reg, val) \
182 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
183
184 #define wr_regl(port, reg, val) \
185 do { __raw_writel(val, portaddr(port, reg)); } while(0)
186
187 /* macros to change one thing to another */
188
189 #define tx_enabled(port) ((port)->unused[0])
190 #define rx_enabled(port) ((port)->unused[1])
191
192 /* flag to ignore all characters comming in */
193 #define RXSTAT_DUMMY_READ (0x10000000)
194
195 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
196 {
197 return container_of(port, struct s3c24xx_uart_port, port);
198 }
199
200 /* translate a port to the device name */
201
202 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
203 {
204 return to_platform_device(port->dev)->name;
205 }
206
207 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
208 {
209 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
210 }
211
212 static void s3c24xx_serial_rx_enable(struct uart_port *port)
213 {
214 unsigned long flags;
215 unsigned int ucon, ufcon;
216 int count = 10000;
217
218 spin_lock_irqsave(&port->lock, flags);
219
220 while (--count && !s3c24xx_serial_txempty_nofifo(port))
221 udelay(100);
222
223 ufcon = rd_regl(port, S3C2410_UFCON);
224 ufcon |= S3C2410_UFCON_RESETRX;
225 wr_regl(port, S3C2410_UFCON, ufcon);
226
227 ucon = rd_regl(port, S3C2410_UCON);
228 ucon |= S3C2410_UCON_RXIRQMODE;
229 wr_regl(port, S3C2410_UCON, ucon);
230
231 rx_enabled(port) = 1;
232 spin_unlock_irqrestore(&port->lock, flags);
233 }
234
235 static void s3c24xx_serial_rx_disable(struct uart_port *port)
236 {
237 unsigned long flags;
238 unsigned int ucon;
239
240 spin_lock_irqsave(&port->lock, flags);
241
242 ucon = rd_regl(port, S3C2410_UCON);
243 ucon &= ~S3C2410_UCON_RXIRQMODE;
244 wr_regl(port, S3C2410_UCON, ucon);
245
246 rx_enabled(port) = 0;
247 spin_unlock_irqrestore(&port->lock, flags);
248 }
249
250 static void s3c24xx_serial_stop_tx(struct uart_port *port)
251 {
252 if (tx_enabled(port)) {
253 disable_irq(TX_IRQ(port));
254 tx_enabled(port) = 0;
255 if (port->flags & UPF_CONS_FLOW)
256 s3c24xx_serial_rx_enable(port);
257 }
258 }
259
260 static void s3c24xx_serial_start_tx(struct uart_port *port)
261 {
262 if (!tx_enabled(port)) {
263 if (port->flags & UPF_CONS_FLOW)
264 s3c24xx_serial_rx_disable(port);
265
266 enable_irq(TX_IRQ(port));
267 tx_enabled(port) = 1;
268 }
269 }
270
271
272 static void s3c24xx_serial_stop_rx(struct uart_port *port)
273 {
274 if (rx_enabled(port)) {
275 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
276 disable_irq(RX_IRQ(port));
277 rx_enabled(port) = 0;
278 }
279 }
280
281 static void s3c24xx_serial_enable_ms(struct uart_port *port)
282 {
283 }
284
285 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
286 {
287 return to_ourport(port)->info;
288 }
289
290 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
291 {
292 if (port->dev == NULL)
293 return NULL;
294
295 return (struct s3c2410_uartcfg *)port->dev->platform_data;
296 }
297
298 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
299 unsigned long ufstat)
300 {
301 struct s3c24xx_uart_info *info = ourport->info;
302
303 if (ufstat & info->rx_fifofull)
304 return info->fifosize;
305
306 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
307 }
308
309
310 /* ? - where has parity gone?? */
311 #define S3C2410_UERSTAT_PARITY (0x1000)
312
313 static irqreturn_t
314 s3c24xx_serial_rx_chars(int irq, void *dev_id, struct pt_regs *regs)
315 {
316 struct s3c24xx_uart_port *ourport = dev_id;
317 struct uart_port *port = &ourport->port;
318 struct tty_struct *tty = port->info->tty;
319 unsigned int ufcon, ch, flag, ufstat, uerstat;
320 int max_count = 64;
321
322 while (max_count-- > 0) {
323 ufcon = rd_regl(port, S3C2410_UFCON);
324 ufstat = rd_regl(port, S3C2410_UFSTAT);
325
326 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
327 break;
328
329 uerstat = rd_regl(port, S3C2410_UERSTAT);
330 ch = rd_regb(port, S3C2410_URXH);
331
332 if (port->flags & UPF_CONS_FLOW) {
333 int txe = s3c24xx_serial_txempty_nofifo(port);
334
335 if (rx_enabled(port)) {
336 if (!txe) {
337 rx_enabled(port) = 0;
338 continue;
339 }
340 } else {
341 if (txe) {
342 ufcon |= S3C2410_UFCON_RESETRX;
343 wr_regl(port, S3C2410_UFCON, ufcon);
344 rx_enabled(port) = 1;
345 goto out;
346 }
347 continue;
348 }
349 }
350
351 /* insert the character into the buffer */
352
353 flag = TTY_NORMAL;
354 port->icount.rx++;
355
356 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
357 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
358 ch, uerstat);
359
360 /* check for break */
361 if (uerstat & S3C2410_UERSTAT_BREAK) {
362 dbg("break!\n");
363 port->icount.brk++;
364 if (uart_handle_break(port))
365 goto ignore_char;
366 }
367
368 if (uerstat & S3C2410_UERSTAT_FRAME)
369 port->icount.frame++;
370 if (uerstat & S3C2410_UERSTAT_OVERRUN)
371 port->icount.overrun++;
372
373 uerstat &= port->read_status_mask;
374
375 if (uerstat & S3C2410_UERSTAT_BREAK)
376 flag = TTY_BREAK;
377 else if (uerstat & S3C2410_UERSTAT_PARITY)
378 flag = TTY_PARITY;
379 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
380 flag = TTY_FRAME;
381 }
382
383 if (uart_handle_sysrq_char(port, ch, regs))
384 goto ignore_char;
385
386 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
387
388 ignore_char:
389 continue;
390 }
391 tty_flip_buffer_push(tty);
392
393 out:
394 return IRQ_HANDLED;
395 }
396
397 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id, struct pt_regs *regs)
398 {
399 struct s3c24xx_uart_port *ourport = id;
400 struct uart_port *port = &ourport->port;
401 struct circ_buf *xmit = &port->info->xmit;
402 int count = 256;
403
404 if (port->x_char) {
405 wr_regb(port, S3C2410_UTXH, port->x_char);
406 port->icount.tx++;
407 port->x_char = 0;
408 goto out;
409 }
410
411 /* if there isnt anything more to transmit, or the uart is now
412 * stopped, disable the uart and exit
413 */
414
415 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
416 s3c24xx_serial_stop_tx(port);
417 goto out;
418 }
419
420 /* try and drain the buffer... */
421
422 while (!uart_circ_empty(xmit) && count-- > 0) {
423 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
424 break;
425
426 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
427 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
428 port->icount.tx++;
429 }
430
431 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
432 uart_write_wakeup(port);
433
434 if (uart_circ_empty(xmit))
435 s3c24xx_serial_stop_tx(port);
436
437 out:
438 return IRQ_HANDLED;
439 }
440
441 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
442 {
443 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
444 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
445 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
446
447 if (ufcon & S3C2410_UFCON_FIFOMODE) {
448 if ((ufstat & info->tx_fifomask) != 0 ||
449 (ufstat & info->tx_fifofull))
450 return 0;
451
452 return 1;
453 }
454
455 return s3c24xx_serial_txempty_nofifo(port);
456 }
457
458 /* no modem control lines */
459 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
460 {
461 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
462
463 if (umstat & S3C2410_UMSTAT_CTS)
464 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
465 else
466 return TIOCM_CAR | TIOCM_DSR;
467 }
468
469 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
470 {
471 /* todo - possibly remove AFC and do manual CTS */
472 }
473
474 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
475 {
476 unsigned long flags;
477 unsigned int ucon;
478
479 spin_lock_irqsave(&port->lock, flags);
480
481 ucon = rd_regl(port, S3C2410_UCON);
482
483 if (break_state)
484 ucon |= S3C2410_UCON_SBREAK;
485 else
486 ucon &= ~S3C2410_UCON_SBREAK;
487
488 wr_regl(port, S3C2410_UCON, ucon);
489
490 spin_unlock_irqrestore(&port->lock, flags);
491 }
492
493 static void s3c24xx_serial_shutdown(struct uart_port *port)
494 {
495 struct s3c24xx_uart_port *ourport = to_ourport(port);
496
497 if (ourport->tx_claimed) {
498 free_irq(TX_IRQ(port), ourport);
499 tx_enabled(port) = 0;
500 ourport->tx_claimed = 0;
501 }
502
503 if (ourport->rx_claimed) {
504 free_irq(RX_IRQ(port), ourport);
505 ourport->rx_claimed = 0;
506 rx_enabled(port) = 0;
507 }
508 }
509
510
511 static int s3c24xx_serial_startup(struct uart_port *port)
512 {
513 struct s3c24xx_uart_port *ourport = to_ourport(port);
514 int ret;
515
516 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
517 port->mapbase, port->membase);
518
519 rx_enabled(port) = 1;
520
521 ret = request_irq(RX_IRQ(port),
522 s3c24xx_serial_rx_chars, 0,
523 s3c24xx_serial_portname(port), ourport);
524
525 if (ret != 0) {
526 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
527 return ret;
528 }
529
530 ourport->rx_claimed = 1;
531
532 dbg("requesting tx irq...\n");
533
534 tx_enabled(port) = 1;
535
536 ret = request_irq(TX_IRQ(port),
537 s3c24xx_serial_tx_chars, 0,
538 s3c24xx_serial_portname(port), ourport);
539
540 if (ret) {
541 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
542 goto err;
543 }
544
545 ourport->tx_claimed = 1;
546
547 dbg("s3c24xx_serial_startup ok\n");
548
549 /* the port reset code should have done the correct
550 * register setup for the port controls */
551
552 return ret;
553
554 err:
555 s3c24xx_serial_shutdown(port);
556 return ret;
557 }
558
559 /* power power management control */
560
561 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
562 unsigned int old)
563 {
564 struct s3c24xx_uart_port *ourport = to_ourport(port);
565
566 switch (level) {
567 case 3:
568 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
569 clk_disable(ourport->baudclk);
570
571 clk_disable(ourport->clk);
572 break;
573
574 case 0:
575 clk_enable(ourport->clk);
576
577 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
578 clk_enable(ourport->baudclk);
579
580 break;
581 default:
582 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
583 }
584 }
585
586 /* baud rate calculation
587 *
588 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
589 * of different sources, including the peripheral clock ("pclk") and an
590 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
591 * with a programmable extra divisor.
592 *
593 * The following code goes through the clock sources, and calculates the
594 * baud clocks (and the resultant actual baud rates) and then tries to
595 * pick the closest one and select that.
596 *
597 */
598
599
600 #define MAX_CLKS (8)
601
602 static struct s3c24xx_uart_clksrc tmp_clksrc = {
603 .name = "pclk",
604 .min_baud = 0,
605 .max_baud = 0,
606 .divisor = 1,
607 };
608
609 static inline int
610 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
611 {
612 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
613
614 return (info->get_clksrc)(port, c);
615 }
616
617 static inline int
618 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
619 {
620 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
621
622 return (info->set_clksrc)(port, c);
623 }
624
625 struct baud_calc {
626 struct s3c24xx_uart_clksrc *clksrc;
627 unsigned int calc;
628 unsigned int quot;
629 struct clk *src;
630 };
631
632 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
633 struct uart_port *port,
634 struct s3c24xx_uart_clksrc *clksrc,
635 unsigned int baud)
636 {
637 unsigned long rate;
638
639 calc->src = clk_get(port->dev, clksrc->name);
640 if (calc->src == NULL || IS_ERR(calc->src))
641 return 0;
642
643 rate = clk_get_rate(calc->src);
644 rate /= clksrc->divisor;
645
646 calc->clksrc = clksrc;
647 calc->quot = (rate + (8 * baud)) / (16 * baud);
648 calc->calc = (rate / (calc->quot * 16));
649
650 calc->quot--;
651 return 1;
652 }
653
654 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
655 struct s3c24xx_uart_clksrc **clksrc,
656 struct clk **clk,
657 unsigned int baud)
658 {
659 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
660 struct s3c24xx_uart_clksrc *clkp;
661 struct baud_calc res[MAX_CLKS];
662 struct baud_calc *resptr, *best, *sptr;
663 int i;
664
665 clkp = cfg->clocks;
666 best = NULL;
667
668 if (cfg->clocks_size < 2) {
669 if (cfg->clocks_size == 0)
670 clkp = &tmp_clksrc;
671
672 /* check to see if we're sourcing fclk, and if so we're
673 * going to have to update the clock source
674 */
675
676 if (strcmp(clkp->name, "fclk") == 0) {
677 struct s3c24xx_uart_clksrc src;
678
679 s3c24xx_serial_getsource(port, &src);
680
681 /* check that the port already using fclk, and if
682 * not, then re-select fclk
683 */
684
685 if (strcmp(src.name, clkp->name) == 0) {
686 s3c24xx_serial_setsource(port, clkp);
687 s3c24xx_serial_getsource(port, &src);
688 }
689
690 clkp->divisor = src.divisor;
691 }
692
693 s3c24xx_serial_calcbaud(res, port, clkp, baud);
694 best = res;
695 resptr = best + 1;
696 } else {
697 resptr = res;
698
699 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
700 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
701 resptr++;
702 }
703 }
704
705 /* ok, we now need to select the best clock we found */
706
707 if (!best) {
708 unsigned int deviation = (1<<30)|((1<<30)-1);
709 int calc_deviation;
710
711 for (sptr = res; sptr < resptr; sptr++) {
712 printk(KERN_DEBUG
713 "found clk %p (%s) quot %d, calc %d\n",
714 sptr->clksrc, sptr->clksrc->name,
715 sptr->quot, sptr->calc);
716
717 calc_deviation = baud - sptr->calc;
718 if (calc_deviation < 0)
719 calc_deviation = -calc_deviation;
720
721 if (calc_deviation < deviation) {
722 best = sptr;
723 deviation = calc_deviation;
724 }
725 }
726
727 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
728 }
729
730 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
731 best->clksrc, best->clksrc->name, best->quot, best->calc);
732
733 /* store results to pass back */
734
735 *clksrc = best->clksrc;
736 *clk = best->src;
737
738 return best->quot;
739 }
740
741 static void s3c24xx_serial_set_termios(struct uart_port *port,
742 struct termios *termios,
743 struct termios *old)
744 {
745 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
746 struct s3c24xx_uart_port *ourport = to_ourport(port);
747 struct s3c24xx_uart_clksrc *clksrc = NULL;
748 struct clk *clk = NULL;
749 unsigned long flags;
750 unsigned int baud, quot;
751 unsigned int ulcon;
752 unsigned int umcon;
753
754 /*
755 * We don't support modem control lines.
756 */
757 termios->c_cflag &= ~(HUPCL | CMSPAR);
758 termios->c_cflag |= CLOCAL;
759
760 /*
761 * Ask the core to calculate the divisor for us.
762 */
763
764 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
765
766 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
767 quot = port->custom_divisor;
768 else
769 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
770
771 /* check to see if we need to change clock source */
772
773 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
774 s3c24xx_serial_setsource(port, clksrc);
775
776 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
777 clk_disable(ourport->baudclk);
778 ourport->baudclk = NULL;
779 }
780
781 clk_enable(clk);
782
783 ourport->clksrc = clksrc;
784 ourport->baudclk = clk;
785 }
786
787 switch (termios->c_cflag & CSIZE) {
788 case CS5:
789 dbg("config: 5bits/char\n");
790 ulcon = S3C2410_LCON_CS5;
791 break;
792 case CS6:
793 dbg("config: 6bits/char\n");
794 ulcon = S3C2410_LCON_CS6;
795 break;
796 case CS7:
797 dbg("config: 7bits/char\n");
798 ulcon = S3C2410_LCON_CS7;
799 break;
800 case CS8:
801 default:
802 dbg("config: 8bits/char\n");
803 ulcon = S3C2410_LCON_CS8;
804 break;
805 }
806
807 /* preserve original lcon IR settings */
808 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
809
810 if (termios->c_cflag & CSTOPB)
811 ulcon |= S3C2410_LCON_STOPB;
812
813 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
814
815 if (termios->c_cflag & PARENB) {
816 if (termios->c_cflag & PARODD)
817 ulcon |= S3C2410_LCON_PODD;
818 else
819 ulcon |= S3C2410_LCON_PEVEN;
820 } else {
821 ulcon |= S3C2410_LCON_PNONE;
822 }
823
824 spin_lock_irqsave(&port->lock, flags);
825
826 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
827
828 wr_regl(port, S3C2410_ULCON, ulcon);
829 wr_regl(port, S3C2410_UBRDIV, quot);
830 wr_regl(port, S3C2410_UMCON, umcon);
831
832 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
833 rd_regl(port, S3C2410_ULCON),
834 rd_regl(port, S3C2410_UCON),
835 rd_regl(port, S3C2410_UFCON));
836
837 /*
838 * Update the per-port timeout.
839 */
840 uart_update_timeout(port, termios->c_cflag, baud);
841
842 /*
843 * Which character status flags are we interested in?
844 */
845 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
846 if (termios->c_iflag & INPCK)
847 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
848
849 /*
850 * Which character status flags should we ignore?
851 */
852 port->ignore_status_mask = 0;
853 if (termios->c_iflag & IGNPAR)
854 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
855 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
856 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
857
858 /*
859 * Ignore all characters if CREAD is not set.
860 */
861 if ((termios->c_cflag & CREAD) == 0)
862 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
863
864 spin_unlock_irqrestore(&port->lock, flags);
865 }
866
867 static const char *s3c24xx_serial_type(struct uart_port *port)
868 {
869 switch (port->type) {
870 case PORT_S3C2410:
871 return "S3C2410";
872 case PORT_S3C2440:
873 return "S3C2440";
874 case PORT_S3C2412:
875 return "S3C2412";
876 default:
877 return NULL;
878 }
879 }
880
881 #define MAP_SIZE (0x100)
882
883 static void s3c24xx_serial_release_port(struct uart_port *port)
884 {
885 release_mem_region(port->mapbase, MAP_SIZE);
886 }
887
888 static int s3c24xx_serial_request_port(struct uart_port *port)
889 {
890 const char *name = s3c24xx_serial_portname(port);
891 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
892 }
893
894 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
895 {
896 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
897
898 if (flags & UART_CONFIG_TYPE &&
899 s3c24xx_serial_request_port(port) == 0)
900 port->type = info->type;
901 }
902
903 /*
904 * verify the new serial_struct (for TIOCSSERIAL).
905 */
906 static int
907 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
908 {
909 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
910
911 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
912 return -EINVAL;
913
914 return 0;
915 }
916
917
918 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
919
920 static struct console s3c24xx_serial_console;
921
922 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
923 #else
924 #define S3C24XX_SERIAL_CONSOLE NULL
925 #endif
926
927 static struct uart_ops s3c24xx_serial_ops = {
928 .pm = s3c24xx_serial_pm,
929 .tx_empty = s3c24xx_serial_tx_empty,
930 .get_mctrl = s3c24xx_serial_get_mctrl,
931 .set_mctrl = s3c24xx_serial_set_mctrl,
932 .stop_tx = s3c24xx_serial_stop_tx,
933 .start_tx = s3c24xx_serial_start_tx,
934 .stop_rx = s3c24xx_serial_stop_rx,
935 .enable_ms = s3c24xx_serial_enable_ms,
936 .break_ctl = s3c24xx_serial_break_ctl,
937 .startup = s3c24xx_serial_startup,
938 .shutdown = s3c24xx_serial_shutdown,
939 .set_termios = s3c24xx_serial_set_termios,
940 .type = s3c24xx_serial_type,
941 .release_port = s3c24xx_serial_release_port,
942 .request_port = s3c24xx_serial_request_port,
943 .config_port = s3c24xx_serial_config_port,
944 .verify_port = s3c24xx_serial_verify_port,
945 };
946
947
948 static struct uart_driver s3c24xx_uart_drv = {
949 .owner = THIS_MODULE,
950 .dev_name = "s3c2410_serial",
951 .nr = 3,
952 .cons = S3C24XX_SERIAL_CONSOLE,
953 .driver_name = S3C24XX_SERIAL_NAME,
954 .major = S3C24XX_SERIAL_MAJOR,
955 .minor = S3C24XX_SERIAL_MINOR,
956 };
957
958 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
959 [0] = {
960 .port = {
961 .lock = SPIN_LOCK_UNLOCKED,
962 .iotype = UPIO_MEM,
963 .irq = IRQ_S3CUART_RX0,
964 .uartclk = 0,
965 .fifosize = 16,
966 .ops = &s3c24xx_serial_ops,
967 .flags = UPF_BOOT_AUTOCONF,
968 .line = 0,
969 }
970 },
971 [1] = {
972 .port = {
973 .lock = SPIN_LOCK_UNLOCKED,
974 .iotype = UPIO_MEM,
975 .irq = IRQ_S3CUART_RX1,
976 .uartclk = 0,
977 .fifosize = 16,
978 .ops = &s3c24xx_serial_ops,
979 .flags = UPF_BOOT_AUTOCONF,
980 .line = 1,
981 }
982 },
983 #if NR_PORTS > 2
984
985 [2] = {
986 .port = {
987 .lock = SPIN_LOCK_UNLOCKED,
988 .iotype = UPIO_MEM,
989 .irq = IRQ_S3CUART_RX2,
990 .uartclk = 0,
991 .fifosize = 16,
992 .ops = &s3c24xx_serial_ops,
993 .flags = UPF_BOOT_AUTOCONF,
994 .line = 2,
995 }
996 }
997 #endif
998 };
999
1000 /* s3c24xx_serial_resetport
1001 *
1002 * wrapper to call the specific reset for this port (reset the fifos
1003 * and the settings)
1004 */
1005
1006 static inline int s3c24xx_serial_resetport(struct uart_port * port,
1007 struct s3c2410_uartcfg *cfg)
1008 {
1009 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1010
1011 return (info->reset_port)(port, cfg);
1012 }
1013
1014 /* s3c24xx_serial_init_port
1015 *
1016 * initialise a single serial port from the platform device given
1017 */
1018
1019 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1020 struct s3c24xx_uart_info *info,
1021 struct platform_device *platdev)
1022 {
1023 struct uart_port *port = &ourport->port;
1024 struct s3c2410_uartcfg *cfg;
1025 struct resource *res;
1026
1027 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1028
1029 if (platdev == NULL)
1030 return -ENODEV;
1031
1032 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1033
1034 if (port->mapbase != 0)
1035 return 0;
1036
1037 if (cfg->hwport > 3)
1038 return -EINVAL;
1039
1040 /* setup info for port */
1041 port->dev = &platdev->dev;
1042 ourport->info = info;
1043
1044 /* copy the info in from provided structure */
1045 ourport->port.fifosize = info->fifosize;
1046
1047 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1048
1049 port->uartclk = 1;
1050
1051 if (cfg->uart_flags & UPF_CONS_FLOW) {
1052 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1053 port->flags |= UPF_CONS_FLOW;
1054 }
1055
1056 /* sort our the physical and virtual addresses for each UART */
1057
1058 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1059 if (res == NULL) {
1060 printk(KERN_ERR "failed to find memory resource for uart\n");
1061 return -EINVAL;
1062 }
1063
1064 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1065
1066 port->mapbase = res->start;
1067 port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
1068 port->irq = platform_get_irq(platdev, 0);
1069 if (port->irq < 0)
1070 port->irq = 0;
1071
1072 ourport->clk = clk_get(&platdev->dev, "uart");
1073
1074 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1075 port->mapbase, port->membase, port->irq, port->uartclk);
1076
1077 /* reset the fifos (and setup the uart) */
1078 s3c24xx_serial_resetport(port, cfg);
1079 return 0;
1080 }
1081
1082 /* Device driver serial port probe */
1083
1084 static int probe_index = 0;
1085
1086 static int s3c24xx_serial_probe(struct platform_device *dev,
1087 struct s3c24xx_uart_info *info)
1088 {
1089 struct s3c24xx_uart_port *ourport;
1090 int ret;
1091
1092 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1093
1094 ourport = &s3c24xx_serial_ports[probe_index];
1095 probe_index++;
1096
1097 dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
1098
1099 ret = s3c24xx_serial_init_port(ourport, info, dev);
1100 if (ret < 0)
1101 goto probe_err;
1102
1103 dbg("%s: adding port\n", __FUNCTION__);
1104 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1105 platform_set_drvdata(dev, &ourport->port);
1106
1107 return 0;
1108
1109 probe_err:
1110 return ret;
1111 }
1112
1113 static int s3c24xx_serial_remove(struct platform_device *dev)
1114 {
1115 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1116
1117 if (port)
1118 uart_remove_one_port(&s3c24xx_uart_drv, port);
1119
1120 return 0;
1121 }
1122
1123 /* UART power management code */
1124
1125 #ifdef CONFIG_PM
1126
1127 static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
1128 {
1129 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1130
1131 if (port)
1132 uart_suspend_port(&s3c24xx_uart_drv, port);
1133
1134 return 0;
1135 }
1136
1137 static int s3c24xx_serial_resume(struct platform_device *dev)
1138 {
1139 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1140 struct s3c24xx_uart_port *ourport = to_ourport(port);
1141
1142 if (port) {
1143 clk_enable(ourport->clk);
1144 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1145 clk_disable(ourport->clk);
1146
1147 uart_resume_port(&s3c24xx_uart_drv, port);
1148 }
1149
1150 return 0;
1151 }
1152
1153 #else
1154 #define s3c24xx_serial_suspend NULL
1155 #define s3c24xx_serial_resume NULL
1156 #endif
1157
1158 static int s3c24xx_serial_init(struct platform_driver *drv,
1159 struct s3c24xx_uart_info *info)
1160 {
1161 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1162 return platform_driver_register(drv);
1163 }
1164
1165
1166 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1167 * port information
1168 */
1169
1170 /* cpu specific variations on the serial port support */
1171
1172 #ifdef CONFIG_CPU_S3C2400
1173
1174 static int s3c2400_serial_getsource(struct uart_port *port,
1175 struct s3c24xx_uart_clksrc *clk)
1176 {
1177 clk->divisor = 1;
1178 clk->name = "pclk";
1179
1180 return 0;
1181 }
1182
1183 static int s3c2400_serial_setsource(struct uart_port *port,
1184 struct s3c24xx_uart_clksrc *clk)
1185 {
1186 return 0;
1187 }
1188
1189 static int s3c2400_serial_resetport(struct uart_port *port,
1190 struct s3c2410_uartcfg *cfg)
1191 {
1192 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1193 port, port->mapbase, cfg);
1194
1195 wr_regl(port, S3C2410_UCON, cfg->ucon);
1196 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1197
1198 /* reset both fifos */
1199
1200 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1201 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1202
1203 return 0;
1204 }
1205
1206 static struct s3c24xx_uart_info s3c2400_uart_inf = {
1207 .name = "Samsung S3C2400 UART",
1208 .type = PORT_S3C2400,
1209 .fifosize = 16,
1210 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1211 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1212 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1213 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1214 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1215 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1216 .get_clksrc = s3c2400_serial_getsource,
1217 .set_clksrc = s3c2400_serial_setsource,
1218 .reset_port = s3c2400_serial_resetport,
1219 };
1220
1221 static int s3c2400_serial_probe(struct platform_device *dev)
1222 {
1223 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1224 }
1225
1226 static struct platform_driver s3c2400_serial_drv = {
1227 .probe = s3c2400_serial_probe,
1228 .remove = s3c24xx_serial_remove,
1229 .suspend = s3c24xx_serial_suspend,
1230 .resume = s3c24xx_serial_resume,
1231 .driver = {
1232 .name = "s3c2400-uart",
1233 .owner = THIS_MODULE,
1234 },
1235 };
1236
1237 static inline int s3c2400_serial_init(void)
1238 {
1239 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1240 }
1241
1242 static inline void s3c2400_serial_exit(void)
1243 {
1244 platform_driver_unregister(&s3c2400_serial_drv);
1245 }
1246
1247 #define s3c2400_uart_inf_at &s3c2400_uart_inf
1248 #else
1249
1250 static inline int s3c2400_serial_init(void)
1251 {
1252 return 0;
1253 }
1254
1255 static inline void s3c2400_serial_exit(void)
1256 {
1257 }
1258
1259 #define s3c2400_uart_inf_at NULL
1260
1261 #endif /* CONFIG_CPU_S3C2400 */
1262
1263 /* S3C2410 support */
1264
1265 #ifdef CONFIG_CPU_S3C2410
1266
1267 static int s3c2410_serial_setsource(struct uart_port *port,
1268 struct s3c24xx_uart_clksrc *clk)
1269 {
1270 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1271
1272 if (strcmp(clk->name, "uclk") == 0)
1273 ucon |= S3C2410_UCON_UCLK;
1274 else
1275 ucon &= ~S3C2410_UCON_UCLK;
1276
1277 wr_regl(port, S3C2410_UCON, ucon);
1278 return 0;
1279 }
1280
1281 static int s3c2410_serial_getsource(struct uart_port *port,
1282 struct s3c24xx_uart_clksrc *clk)
1283 {
1284 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1285
1286 clk->divisor = 1;
1287 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1288
1289 return 0;
1290 }
1291
1292 static int s3c2410_serial_resetport(struct uart_port *port,
1293 struct s3c2410_uartcfg *cfg)
1294 {
1295 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1296 port, port->mapbase, cfg);
1297
1298 wr_regl(port, S3C2410_UCON, cfg->ucon);
1299 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1300
1301 /* reset both fifos */
1302
1303 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1304 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1305
1306 return 0;
1307 }
1308
1309 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1310 .name = "Samsung S3C2410 UART",
1311 .type = PORT_S3C2410,
1312 .fifosize = 16,
1313 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1314 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1315 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1316 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1317 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1318 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1319 .get_clksrc = s3c2410_serial_getsource,
1320 .set_clksrc = s3c2410_serial_setsource,
1321 .reset_port = s3c2410_serial_resetport,
1322 };
1323
1324 /* device management */
1325
1326 static int s3c2410_serial_probe(struct platform_device *dev)
1327 {
1328 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1329 }
1330
1331 static struct platform_driver s3c2410_serial_drv = {
1332 .probe = s3c2410_serial_probe,
1333 .remove = s3c24xx_serial_remove,
1334 .suspend = s3c24xx_serial_suspend,
1335 .resume = s3c24xx_serial_resume,
1336 .driver = {
1337 .name = "s3c2410-uart",
1338 .owner = THIS_MODULE,
1339 },
1340 };
1341
1342 static inline int s3c2410_serial_init(void)
1343 {
1344 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1345 }
1346
1347 static inline void s3c2410_serial_exit(void)
1348 {
1349 platform_driver_unregister(&s3c2410_serial_drv);
1350 }
1351
1352 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1353 #else
1354
1355 static inline int s3c2410_serial_init(void)
1356 {
1357 return 0;
1358 }
1359
1360 static inline void s3c2410_serial_exit(void)
1361 {
1362 }
1363
1364 #define s3c2410_uart_inf_at NULL
1365
1366 #endif /* CONFIG_CPU_S3C2410 */
1367
1368 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
1369
1370 static int s3c2440_serial_setsource(struct uart_port *port,
1371 struct s3c24xx_uart_clksrc *clk)
1372 {
1373 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1374
1375 // todo - proper fclk<>nonfclk switch //
1376
1377 ucon &= ~S3C2440_UCON_CLKMASK;
1378
1379 if (strcmp(clk->name, "uclk") == 0)
1380 ucon |= S3C2440_UCON_UCLK;
1381 else if (strcmp(clk->name, "pclk") == 0)
1382 ucon |= S3C2440_UCON_PCLK;
1383 else if (strcmp(clk->name, "fclk") == 0)
1384 ucon |= S3C2440_UCON_FCLK;
1385 else {
1386 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1387 return -EINVAL;
1388 }
1389
1390 wr_regl(port, S3C2410_UCON, ucon);
1391 return 0;
1392 }
1393
1394
1395 static int s3c2440_serial_getsource(struct uart_port *port,
1396 struct s3c24xx_uart_clksrc *clk)
1397 {
1398 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1399 unsigned long ucon0, ucon1, ucon2;
1400
1401 switch (ucon & S3C2440_UCON_CLKMASK) {
1402 case S3C2440_UCON_UCLK:
1403 clk->divisor = 1;
1404 clk->name = "uclk";
1405 break;
1406
1407 case S3C2440_UCON_PCLK:
1408 case S3C2440_UCON_PCLK2:
1409 clk->divisor = 1;
1410 clk->name = "pclk";
1411 break;
1412
1413 case S3C2440_UCON_FCLK:
1414 /* the fun of calculating the uart divisors on
1415 * the s3c2440 */
1416
1417 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1418 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1419 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1420
1421 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1422
1423 ucon0 &= S3C2440_UCON0_DIVMASK;
1424 ucon1 &= S3C2440_UCON1_DIVMASK;
1425 ucon2 &= S3C2440_UCON2_DIVMASK;
1426
1427 if (ucon0 != 0) {
1428 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1429 clk->divisor += 6;
1430 } else if (ucon1 != 0) {
1431 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1432 clk->divisor += 21;
1433 } else if (ucon2 != 0) {
1434 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1435 clk->divisor += 36;
1436 } else {
1437 /* manual calims 44, seems to be 9 */
1438 clk->divisor = 9;
1439 }
1440
1441 clk->name = "fclk";
1442 break;
1443 }
1444
1445 return 0;
1446 }
1447
1448 static int s3c2440_serial_resetport(struct uart_port *port,
1449 struct s3c2410_uartcfg *cfg)
1450 {
1451 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1452
1453 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1454 port, port->mapbase, cfg);
1455
1456 /* ensure we don't change the clock settings... */
1457
1458 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1459
1460 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1461 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1462
1463 /* reset both fifos */
1464
1465 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1466 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1467
1468 return 0;
1469 }
1470
1471 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1472 .name = "Samsung S3C2440 UART",
1473 .type = PORT_S3C2440,
1474 .fifosize = 64,
1475 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1476 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1477 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1478 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1479 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1480 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1481 .get_clksrc = s3c2440_serial_getsource,
1482 .set_clksrc = s3c2440_serial_setsource,
1483 .reset_port = s3c2440_serial_resetport,
1484 };
1485
1486 /* device management */
1487
1488 static int s3c2440_serial_probe(struct platform_device *dev)
1489 {
1490 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1491 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1492 }
1493
1494 static struct platform_driver s3c2440_serial_drv = {
1495 .probe = s3c2440_serial_probe,
1496 .remove = s3c24xx_serial_remove,
1497 .suspend = s3c24xx_serial_suspend,
1498 .resume = s3c24xx_serial_resume,
1499 .driver = {
1500 .name = "s3c2440-uart",
1501 .owner = THIS_MODULE,
1502 },
1503 };
1504
1505
1506 static inline int s3c2440_serial_init(void)
1507 {
1508 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1509 }
1510
1511 static inline void s3c2440_serial_exit(void)
1512 {
1513 platform_driver_unregister(&s3c2440_serial_drv);
1514 }
1515
1516 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1517 #else
1518
1519 static inline int s3c2440_serial_init(void)
1520 {
1521 return 0;
1522 }
1523
1524 static inline void s3c2440_serial_exit(void)
1525 {
1526 }
1527
1528 #define s3c2440_uart_inf_at NULL
1529 #endif /* CONFIG_CPU_S3C2440 */
1530
1531 #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
1532
1533 static int s3c2412_serial_setsource(struct uart_port *port,
1534 struct s3c24xx_uart_clksrc *clk)
1535 {
1536 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1537
1538 ucon &= ~S3C2412_UCON_CLKMASK;
1539
1540 if (strcmp(clk->name, "uclk") == 0)
1541 ucon |= S3C2440_UCON_UCLK;
1542 else if (strcmp(clk->name, "pclk") == 0)
1543 ucon |= S3C2440_UCON_PCLK;
1544 else if (strcmp(clk->name, "usysclk") == 0)
1545 ucon |= S3C2412_UCON_USYSCLK;
1546 else {
1547 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1548 return -EINVAL;
1549 }
1550
1551 wr_regl(port, S3C2410_UCON, ucon);
1552 return 0;
1553 }
1554
1555
1556 static int s3c2412_serial_getsource(struct uart_port *port,
1557 struct s3c24xx_uart_clksrc *clk)
1558 {
1559 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1560
1561 switch (ucon & S3C2412_UCON_CLKMASK) {
1562 case S3C2412_UCON_UCLK:
1563 clk->divisor = 1;
1564 clk->name = "uclk";
1565 break;
1566
1567 case S3C2412_UCON_PCLK:
1568 case S3C2412_UCON_PCLK2:
1569 clk->divisor = 1;
1570 clk->name = "pclk";
1571 break;
1572
1573 case S3C2412_UCON_USYSCLK:
1574 clk->divisor = 1;
1575 clk->name = "usysclk";
1576 break;
1577 }
1578
1579 return 0;
1580 }
1581
1582 static int s3c2412_serial_resetport(struct uart_port *port,
1583 struct s3c2410_uartcfg *cfg)
1584 {
1585 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1586
1587 dbg("%s: port=%p (%08lx), cfg=%p\n",
1588 __FUNCTION__, port, port->mapbase, cfg);
1589
1590 /* ensure we don't change the clock settings... */
1591
1592 ucon &= S3C2412_UCON_CLKMASK;
1593
1594 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1595 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1596
1597 /* reset both fifos */
1598
1599 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1600 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1601
1602 return 0;
1603 }
1604
1605 static struct s3c24xx_uart_info s3c2412_uart_inf = {
1606 .name = "Samsung S3C2412 UART",
1607 .type = PORT_S3C2412,
1608 .fifosize = 64,
1609 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1610 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1611 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1612 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1613 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1614 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1615 .get_clksrc = s3c2412_serial_getsource,
1616 .set_clksrc = s3c2412_serial_setsource,
1617 .reset_port = s3c2412_serial_resetport,
1618 };
1619
1620 /* device management */
1621
1622 static int s3c2412_serial_probe(struct platform_device *dev)
1623 {
1624 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1625 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1626 }
1627
1628 static struct platform_driver s3c2412_serial_drv = {
1629 .probe = s3c2412_serial_probe,
1630 .remove = s3c24xx_serial_remove,
1631 .suspend = s3c24xx_serial_suspend,
1632 .resume = s3c24xx_serial_resume,
1633 .driver = {
1634 .name = "s3c2412-uart",
1635 .owner = THIS_MODULE,
1636 },
1637 };
1638
1639
1640 static inline int s3c2412_serial_init(void)
1641 {
1642 return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
1643 }
1644
1645 static inline void s3c2412_serial_exit(void)
1646 {
1647 platform_driver_unregister(&s3c2412_serial_drv);
1648 }
1649
1650 #define s3c2412_uart_inf_at &s3c2412_uart_inf
1651 #else
1652
1653 static inline int s3c2412_serial_init(void)
1654 {
1655 return 0;
1656 }
1657
1658 static inline void s3c2412_serial_exit(void)
1659 {
1660 }
1661
1662 #define s3c2412_uart_inf_at NULL
1663 #endif /* CONFIG_CPU_S3C2440 */
1664
1665
1666 /* module initialisation code */
1667
1668 static int __init s3c24xx_serial_modinit(void)
1669 {
1670 int ret;
1671
1672 ret = uart_register_driver(&s3c24xx_uart_drv);
1673 if (ret < 0) {
1674 printk(KERN_ERR "failed to register UART driver\n");
1675 return -1;
1676 }
1677
1678 s3c2400_serial_init();
1679 s3c2410_serial_init();
1680 s3c2412_serial_init();
1681 s3c2440_serial_init();
1682
1683 return 0;
1684 }
1685
1686 static void __exit s3c24xx_serial_modexit(void)
1687 {
1688 s3c2400_serial_exit();
1689 s3c2410_serial_exit();
1690 s3c2412_serial_exit();
1691 s3c2440_serial_exit();
1692
1693 uart_unregister_driver(&s3c24xx_uart_drv);
1694 }
1695
1696
1697 module_init(s3c24xx_serial_modinit);
1698 module_exit(s3c24xx_serial_modexit);
1699
1700 /* Console code */
1701
1702 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1703
1704 static struct uart_port *cons_uart;
1705
1706 static int
1707 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1708 {
1709 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1710 unsigned long ufstat, utrstat;
1711
1712 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1713 /* fifo mode - check ammount of data in fifo registers... */
1714
1715 ufstat = rd_regl(port, S3C2410_UFSTAT);
1716 return (ufstat & info->tx_fifofull) ? 0 : 1;
1717 }
1718
1719 /* in non-fifo mode, we go and use the tx buffer empty */
1720
1721 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1722 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1723 }
1724
1725 static void
1726 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1727 {
1728 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1729 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1730 barrier();
1731 wr_regb(cons_uart, S3C2410_UTXH, ch);
1732 }
1733
1734 static void
1735 s3c24xx_serial_console_write(struct console *co, const char *s,
1736 unsigned int count)
1737 {
1738 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1739 }
1740
1741 static void __init
1742 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1743 int *parity, int *bits)
1744 {
1745 struct s3c24xx_uart_clksrc clksrc;
1746 struct clk *clk;
1747 unsigned int ulcon;
1748 unsigned int ucon;
1749 unsigned int ubrdiv;
1750 unsigned long rate;
1751
1752 ulcon = rd_regl(port, S3C2410_ULCON);
1753 ucon = rd_regl(port, S3C2410_UCON);
1754 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1755
1756 dbg("s3c24xx_serial_get_options: port=%p\n"
1757 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1758 port, ulcon, ucon, ubrdiv);
1759
1760 if ((ucon & 0xf) != 0) {
1761 /* consider the serial port configured if the tx/rx mode set */
1762
1763 switch (ulcon & S3C2410_LCON_CSMASK) {
1764 case S3C2410_LCON_CS5:
1765 *bits = 5;
1766 break;
1767 case S3C2410_LCON_CS6:
1768 *bits = 6;
1769 break;
1770 case S3C2410_LCON_CS7:
1771 *bits = 7;
1772 break;
1773 default:
1774 case S3C2410_LCON_CS8:
1775 *bits = 8;
1776 break;
1777 }
1778
1779 switch (ulcon & S3C2410_LCON_PMASK) {
1780 case S3C2410_LCON_PEVEN:
1781 *parity = 'e';
1782 break;
1783
1784 case S3C2410_LCON_PODD:
1785 *parity = 'o';
1786 break;
1787
1788 case S3C2410_LCON_PNONE:
1789 default:
1790 *parity = 'n';
1791 }
1792
1793 /* now calculate the baud rate */
1794
1795 s3c24xx_serial_getsource(port, &clksrc);
1796
1797 clk = clk_get(port->dev, clksrc.name);
1798 if (!IS_ERR(clk) && clk != NULL)
1799 rate = clk_get_rate(clk) / clksrc.divisor;
1800 else
1801 rate = 1;
1802
1803
1804 *baud = rate / ( 16 * (ubrdiv + 1));
1805 dbg("calculated baud %d\n", *baud);
1806 }
1807
1808 }
1809
1810 /* s3c24xx_serial_init_ports
1811 *
1812 * initialise the serial ports from the machine provided initialisation
1813 * data.
1814 */
1815
1816 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1817 {
1818 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1819 struct platform_device **platdev_ptr;
1820 int i;
1821
1822 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1823
1824 platdev_ptr = s3c24xx_uart_devs;
1825
1826 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1827 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1828 }
1829
1830 return 0;
1831 }
1832
1833 static int __init
1834 s3c24xx_serial_console_setup(struct console *co, char *options)
1835 {
1836 struct uart_port *port;
1837 int baud = 9600;
1838 int bits = 8;
1839 int parity = 'n';
1840 int flow = 'n';
1841
1842 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1843 co, co->index, options);
1844
1845 /* is this a valid port */
1846
1847 if (co->index == -1 || co->index >= NR_PORTS)
1848 co->index = 0;
1849
1850 port = &s3c24xx_serial_ports[co->index].port;
1851
1852 /* is the port configured? */
1853
1854 if (port->mapbase == 0x0) {
1855 co->index = 0;
1856 port = &s3c24xx_serial_ports[co->index].port;
1857 }
1858
1859 cons_uart = port;
1860
1861 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1862
1863 /*
1864 * Check whether an invalid uart number has been specified, and
1865 * if so, search for the first available port that does have
1866 * console support.
1867 */
1868 if (options)
1869 uart_parse_options(options, &baud, &parity, &bits, &flow);
1870 else
1871 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1872
1873 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1874
1875 return uart_set_options(port, co, baud, parity, bits, flow);
1876 }
1877
1878 /* s3c24xx_serial_initconsole
1879 *
1880 * initialise the console from one of the uart drivers
1881 */
1882
1883 static struct console s3c24xx_serial_console =
1884 {
1885 .name = S3C24XX_SERIAL_NAME,
1886 .device = uart_console_device,
1887 .flags = CON_PRINTBUFFER,
1888 .index = -1,
1889 .write = s3c24xx_serial_console_write,
1890 .setup = s3c24xx_serial_console_setup
1891 };
1892
1893 static int s3c24xx_serial_initconsole(void)
1894 {
1895 struct s3c24xx_uart_info *info;
1896 struct platform_device *dev = s3c24xx_uart_devs[0];
1897
1898 dbg("s3c24xx_serial_initconsole\n");
1899
1900 /* select driver based on the cpu */
1901
1902 if (dev == NULL) {
1903 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1904 return 0;
1905 }
1906
1907 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1908 info = s3c2400_uart_inf_at;
1909 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1910 info = s3c2410_uart_inf_at;
1911 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1912 info = s3c2440_uart_inf_at;
1913 } else if (strcmp(dev->name, "s3c2412-uart") == 0) {
1914 info = s3c2412_uart_inf_at;
1915 } else {
1916 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1917 return 0;
1918 }
1919
1920 if (info == NULL) {
1921 printk(KERN_ERR "s3c24xx: no driver for console\n");
1922 return 0;
1923 }
1924
1925 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1926 s3c24xx_serial_init_ports(info);
1927
1928 register_console(&s3c24xx_serial_console);
1929 return 0;
1930 }
1931
1932 console_initcall(s3c24xx_serial_initconsole);
1933
1934 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1935
1936 MODULE_LICENSE("GPL");
1937 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1938 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440/S3C2412 Serial port driver");
linux-next