arch/arm/mach-pxa/pxa27x.c

   1 /*
   2  *  linux/arch/arm/mach-pxa/pxa27x.c
   3  *
   4  *  Author:     Nicolas Pitre
   5  *  Created:    Nov 05, 2002
   6  *  Copyright:  MontaVista Software Inc.
   7  *
   8  * Code specific to PXA27x aka Bulverde.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/suspend.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/sysdev.h>
  20
  21 #include <mach/hardware.h>
  22 #include <asm/irq.h>
  23 #include <mach/irqs.h>
  24 #include <mach/pxa-regs.h>
  25 #include <mach/pxa2xx-regs.h>
  26 #include <mach/mfp-pxa27x.h>
  27 #include <mach/reset.h>
  28 #include <mach/ohci.h>
  29 #include <mach/pm.h>
  30 #include <mach/dma.h>
  31 #include <mach/i2c.h>
  32
  33 #include "generic.h"
  34 #include "devices.h"
  35 #include "clock.h"
  36
  37 void pxa27x_clear_otgph(void)
  38 {
  39         if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
  40                 PSSR |= PSSR_OTGPH;
  41 }
  42 EXPORT_SYMBOL(pxa27x_clear_otgph);
  43
  44 /* Crystal clock: 13MHz */
  45 #define BASE_CLK        13000000
  46
  47 /*
  48  * Get the clock frequency as reflected by CCSR and the turbo flag.
  49  * We assume these values have been applied via a fcs.
  50  * If info is not 0 we also display the current settings.
  51  */
  52 unsigned int pxa27x_get_clk_frequency_khz(int info)
  53 {
  54         unsigned long ccsr, clkcfg;
  55         unsigned int l, L, m, M, n2, N, S;
  56         int cccr_a, t, ht, b;
  57
  58         ccsr = CCSR;
  59         cccr_a = CCCR & (1 << 25);
  60
  61         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
  62         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
  63         t  = clkcfg & (1 << 0);
  64         ht = clkcfg & (1 << 2);
  65         b  = clkcfg & (1 << 3);
  66
  67         l  = ccsr & 0x1f;
  68         n2 = (ccsr>>7) & 0xf;
  69         m  = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
  70
  71         L  = l * BASE_CLK;
  72         N  = (L * n2) / 2;
  73         M  = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
  74         S  = (b) ? L : (L/2);
  75
  76         if (info) {
  77                 printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
  78                         L / 1000000, (L % 1000000) / 10000, l );
  79                 printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
  80                         N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
  81                         (t) ? "" : "in" );
  82                 printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
  83                         M / 1000000, (M % 1000000) / 10000, m );
  84                 printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
  85                         S / 1000000, (S % 1000000) / 10000 );
  86         }
  87
  88         return (t) ? (N/1000) : (L/1000);
  89 }
  90
  91 /*
  92  * Return the current mem clock frequency in units of 10kHz as
  93  * reflected by CCCR[A], B, and L
  94  */
  95 unsigned int pxa27x_get_memclk_frequency_10khz(void)
  96 {
  97         unsigned long ccsr, clkcfg;
  98         unsigned int l, L, m, M;
  99         int cccr_a, b;
 100
 101         ccsr = CCSR;
 102         cccr_a = CCCR & (1 << 25);
 103
 104         /* Read clkcfg register: it has turbo, b, half-turbo (and f) */
 105         asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
 106         b = clkcfg & (1 << 3);
 107
 108         l = ccsr & 0x1f;
 109         m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
 110
 111         L = l * BASE_CLK;
 112         M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
 113
 114         return (M / 10000);
 115 }
 116
 117 /*
 118  * Return the current LCD clock frequency in units of 10kHz as
 119  */
 120 static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
 121 {
 122         unsigned long ccsr;
 123         unsigned int l, L, k, K;
 124
 125         ccsr = CCSR;
 126
 127         l = ccsr & 0x1f;
 128         k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
 129
 130         L = l * BASE_CLK;
 131         K = L / k;
 132
 133         return (K / 10000);
 134 }
 135
 136 static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
 137 {
 138         return pxa27x_get_lcdclk_frequency_10khz() * 10000;
 139 }
 140
 141 static const struct clkops clk_pxa27x_lcd_ops = {
 142         .enable         = clk_cken_enable,
 143         .disable        = clk_cken_disable,
 144         .getrate        = clk_pxa27x_lcd_getrate,
 145 };
 146
 147 static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
 148 static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
 149 static DEFINE_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
 150 static DEFINE_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
 151 static DEFINE_CKEN(pxa27x_stuart, STUART, 14857000, 1);
 152 static DEFINE_CKEN(pxa27x_i2s, I2S, 14682000, 0);
 153 static DEFINE_CKEN(pxa27x_i2c, I2C, 32842000, 0);
 154 static DEFINE_CKEN(pxa27x_usb, USB, 48000000, 5);
 155 static DEFINE_CKEN(pxa27x_mmc, MMC, 19500000, 0);
 156 static DEFINE_CKEN(pxa27x_ficp, FICP, 48000000, 0);
 157 static DEFINE_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
 158 static DEFINE_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
 159 static DEFINE_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
 160 static DEFINE_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
 161 static DEFINE_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
 162 static DEFINE_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
 163 static DEFINE_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
 164 static DEFINE_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
 165 static DEFINE_CKEN(pxa27x_ac97, AC97, 24576000, 0);
 166 static DEFINE_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
 167 static DEFINE_CKEN(pxa27x_msl, MSL, 48000000, 0);
 168 static DEFINE_CKEN(pxa27x_usim, USIM, 48000000, 0);
 169 static DEFINE_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
 170 static DEFINE_CKEN(pxa27x_im, IM, 0, 0);
 171 static DEFINE_CKEN(pxa27x_memc, MEMC, 0, 0);
 172
 173 static struct clk_lookup pxa27x_clkregs[] = {
 174         INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
 175         INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
 176         INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
 177         INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
 178         INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
 179         INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
 180         INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
 181         INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
 182         INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
 183         INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
 184         INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
 185         INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
 186         INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
 187         INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
 188         INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
 189         INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
 190         INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
 191         INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
 192         INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
 193         INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
 194         INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
 195         INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
 196         INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
 197         INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
 198         INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
 199         INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
 200 };
 201
 202 #ifdef CONFIG_PM
 203
 204 #define SAVE(x)         sleep_save[SLEEP_SAVE_##x] = x
 205 #define RESTORE(x)      x = sleep_save[SLEEP_SAVE_##x]
 206
 207 /*
 208  * List of global PXA peripheral registers to preserve.
 209  * More ones like CP and general purpose register values are preserved
 210  * with the stack pointer in sleep.S.
 211  */
 212 enum {
 213         SLEEP_SAVE_PSTR,
 214         SLEEP_SAVE_CKEN,
 215         SLEEP_SAVE_MDREFR,
 216         SLEEP_SAVE_PCFR,
 217         SLEEP_SAVE_COUNT
 218 };
 219
 220 void pxa27x_cpu_pm_save(unsigned long *sleep_save)
 221 {
 222         SAVE(MDREFR);
 223         SAVE(PCFR);
 224
 225         SAVE(CKEN);
 226         SAVE(PSTR);
 227 }
 228
 229 void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
 230 {
 231         RESTORE(MDREFR);
 232         RESTORE(PCFR);
 233
 234         PSSR = PSSR_RDH | PSSR_PH;
 235
 236         RESTORE(CKEN);
 237         RESTORE(PSTR);
 238 }
 239
 240 void pxa27x_cpu_pm_enter(suspend_state_t state)
 241 {
 242         extern void pxa_cpu_standby(void);
 243
 244         /* ensure voltage-change sequencer not initiated, which hangs */
 245         PCFR &= ~PCFR_FVC;
 246
 247         /* Clear edge-detect status register. */
 248         PEDR = 0xDF12FE1B;
 249
 250         /* Clear reset status */
 251         RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
 252
 253         switch (state) {
 254         case PM_SUSPEND_STANDBY:
 255                 pxa_cpu_standby();
 256                 break;
 257         case PM_SUSPEND_MEM:
 258                 pxa27x_cpu_suspend(PWRMODE_SLEEP);
 259                 break;
 260         }
 261 }
 262
 263 static int pxa27x_cpu_pm_valid(suspend_state_t state)
 264 {
 265         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 266 }
 267
 268 static int pxa27x_cpu_pm_prepare(void)
 269 {
 270         /* set resume return address */
 271         PSPR = virt_to_phys(pxa_cpu_resume);
 272         return 0;
 273 }
 274
 275 static void pxa27x_cpu_pm_finish(void)
 276 {
 277         /* ensure not to come back here if it wasn't intended */
 278         PSPR = 0;
 279 }
 280
 281 static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
 282         .save_count     = SLEEP_SAVE_COUNT,
 283         .save           = pxa27x_cpu_pm_save,
 284         .restore        = pxa27x_cpu_pm_restore,
 285         .valid          = pxa27x_cpu_pm_valid,
 286         .enter          = pxa27x_cpu_pm_enter,
 287         .prepare        = pxa27x_cpu_pm_prepare,
 288         .finish         = pxa27x_cpu_pm_finish,
 289 };
 290
 291 static void __init pxa27x_init_pm(void)
 292 {
 293         pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
 294 }
 295 #else
 296 static inline void pxa27x_init_pm(void) {}
 297 #endif
 298
 299 /* PXA27x:  Various gpios can issue wakeup events.  This logic only
 300  * handles the simple cases, not the WEMUX2 and WEMUX3 options
 301  */
 302 static int pxa27x_set_wake(unsigned int irq, unsigned int on)
 303 {
 304         int gpio = IRQ_TO_GPIO(irq);
 305         uint32_t mask;
 306
 307         if (gpio >= 0 && gpio < 128)
 308                 return gpio_set_wake(gpio, on);
 309
 310         if (irq == IRQ_KEYPAD)
 311                 return keypad_set_wake(on);
 312
 313         switch (irq) {
 314         case IRQ_RTCAlrm:
 315                 mask = PWER_RTC;
 316                 break;
 317         case IRQ_USB:
 318                 mask = 1u << 26;
 319                 break;
 320         default:
 321                 return -EINVAL;
 322         }
 323
 324         if (on)
 325                 PWER |= mask;
 326         else
 327                 PWER &=~mask;
 328
 329         return 0;
 330 }
 331
 332 void __init pxa27x_init_irq(void)
 333 {
 334         pxa_init_irq(34, pxa27x_set_wake);
 335         pxa_init_gpio(121, pxa27x_set_wake);
 336 }
 337
 338 /*
 339  * device registration specific to PXA27x.
 340  */
 341 void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 342 {
 343         local_irq_disable();
 344         PCFR |= PCFR_PI2CEN;
 345         local_irq_enable();
 346         pxa_register_device(&pxa27x_device_i2c_power, info);
 347 }
 348
 349 static struct platform_device *devices[] __initdata = {
 350         &pxa27x_device_udc,
 351         &pxa_device_ffuart,
 352         &pxa_device_btuart,
 353         &pxa_device_stuart,
 354         &pxa_device_i2s,
 355         &sa1100_device_rtc,
 356         &pxa_device_rtc,
 357         &pxa27x_device_ssp1,
 358         &pxa27x_device_ssp2,
 359         &pxa27x_device_ssp3,
 360         &pxa27x_device_pwm0,
 361         &pxa27x_device_pwm1,
 362 };
 363
 364 static struct sys_device pxa27x_sysdev[] = {
 365         {
 366                 .cls    = &pxa_irq_sysclass,
 367         }, {
 368                 .cls    = &pxa2xx_mfp_sysclass,
 369         }, {
 370                 .cls    = &pxa_gpio_sysclass,
 371         },
 372 };
 373
 374 static int __init pxa27x_init(void)
 375 {
 376         int i, ret = 0;
 377
 378         if (cpu_is_pxa27x()) {
 379
 380                 reset_status = RCSR;
 381
 382                 clks_register(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
 383
 384                 if ((ret = pxa_init_dma(32)))
 385                         return ret;
 386
 387                 pxa27x_init_pm();
 388
 389                 for (i = 0; i < ARRAY_SIZE(pxa27x_sysdev); i++) {
 390                         ret = sysdev_register(&pxa27x_sysdev[i]);
 391                         if (ret)
 392                                 pr_err("failed to register sysdev[%d]\n", i);
 393                 }
 394
 395                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
 396         }
 397
 398         return ret;
 399 }
 400
 401 postcore_initcall(pxa27x_init);