arch/sh/kernel/cpu/sh4a/setup-sh7722.c

   1 /*
   2  * SH7722 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/mm.h>
  15 #include <linux/uio_driver.h>
  16 #include <asm/clock.h>
  17 #include <asm/mmzone.h>
  18
  19 static struct resource rtc_resources[] = {
  20         [0] = {
  21                 .start  = 0xa465fec0,
  22                 .end    = 0xa465fec0 + 0x58 - 1,
  23                 .flags  = IORESOURCE_IO,
  24         },
  25         [1] = {
  26                 /* Period IRQ */
  27                 .start  = 45,
  28                 .flags  = IORESOURCE_IRQ,
  29         },
  30         [2] = {
  31                 /* Carry IRQ */
  32                 .start  = 46,
  33                 .flags  = IORESOURCE_IRQ,
  34         },
  35         [3] = {
  36                 /* Alarm IRQ */
  37                 .start  = 44,
  38                 .flags  = IORESOURCE_IRQ,
  39         },
  40 };
  41
  42 static struct platform_device rtc_device = {
  43         .name           = "sh-rtc",
  44         .id             = -1,
  45         .num_resources  = ARRAY_SIZE(rtc_resources),
  46         .resource       = rtc_resources,
  47 };
  48
  49 static struct resource usbf_resources[] = {
  50         [0] = {
  51                 .name   = "m66592_udc",
  52                 .start  = 0x04480000,
  53                 .end    = 0x044800FF,
  54                 .flags  = IORESOURCE_MEM,
  55         },
  56         [1] = {
  57                 .start  = 65,
  58                 .end    = 65,
  59                 .flags  = IORESOURCE_IRQ,
  60         },
  61 };
  62
  63 static struct platform_device usbf_device = {
  64         .name           = "m66592_udc",
  65         .id             = 0, /* "usbf0" clock */
  66         .dev = {
  67                 .dma_mask               = NULL,
  68                 .coherent_dma_mask      = 0xffffffff,
  69         },
  70         .num_resources  = ARRAY_SIZE(usbf_resources),
  71         .resource       = usbf_resources,
  72 };
  73
  74 static struct resource iic_resources[] = {
  75         [0] = {
  76                 .name   = "IIC",
  77                 .start  = 0x04470000,
  78                 .end    = 0x04470017,
  79                 .flags  = IORESOURCE_MEM,
  80         },
  81         [1] = {
  82                 .start  = 96,
  83                 .end    = 99,
  84                 .flags  = IORESOURCE_IRQ,
  85        },
  86 };
  87
  88 static struct platform_device iic_device = {
  89         .name           = "i2c-sh_mobile",
  90         .id             = 0, /* "i2c0" clock */
  91         .num_resources  = ARRAY_SIZE(iic_resources),
  92         .resource       = iic_resources,
  93 };
  94
  95 static struct uio_info vpu_platform_data = {
  96         .name = "VPU4",
  97         .version = "0",
  98         .irq = 60,
  99 };
 100
 101 static struct resource vpu_resources[] = {
 102         [0] = {
 103                 .name   = "VPU",
 104                 .start  = 0xfe900000,
 105                 .end    = 0xfe9022eb,
 106                 .flags  = IORESOURCE_MEM,
 107         },
 108         [1] = {
 109                 /* place holder for contiguous memory */
 110         },
 111 };
 112
 113 static struct platform_device vpu_device = {
 114         .name           = "uio_pdrv_genirq",
 115         .id             = 0,
 116         .dev = {
 117                 .platform_data  = &vpu_platform_data,
 118         },
 119         .resource       = vpu_resources,
 120         .num_resources  = ARRAY_SIZE(vpu_resources),
 121 };
 122
 123 static struct uio_info veu_platform_data = {
 124         .name = "VEU",
 125         .version = "0",
 126         .irq = 54,
 127 };
 128
 129 static struct resource veu_resources[] = {
 130         [0] = {
 131                 .name   = "VEU",
 132                 .start  = 0xfe920000,
 133                 .end    = 0xfe9200b7,
 134                 .flags  = IORESOURCE_MEM,
 135         },
 136         [1] = {
 137                 /* place holder for contiguous memory */
 138         },
 139 };
 140
 141 static struct platform_device veu_device = {
 142         .name           = "uio_pdrv_genirq",
 143         .id             = 1,
 144         .dev = {
 145                 .platform_data  = &veu_platform_data,
 146         },
 147         .resource       = veu_resources,
 148         .num_resources  = ARRAY_SIZE(veu_resources),
 149 };
 150
 151 static struct uio_info jpu_platform_data = {
 152         .name = "JPU",
 153         .version = "0",
 154         .irq = 27,
 155 };
 156
 157 static struct resource jpu_resources[] = {
 158         [0] = {
 159                 .name   = "JPU",
 160                 .start  = 0xfea00000,
 161                 .end    = 0xfea102d3,
 162                 .flags  = IORESOURCE_MEM,
 163         },
 164         [1] = {
 165                 /* place holder for contiguous memory */
 166         },
 167 };
 168
 169 static struct platform_device jpu_device = {
 170         .name           = "uio_pdrv_genirq",
 171         .id             = 2,
 172         .dev = {
 173                 .platform_data  = &jpu_platform_data,
 174         },
 175         .resource       = jpu_resources,
 176         .num_resources  = ARRAY_SIZE(jpu_resources),
 177 };
 178
 179 static struct plat_sci_port sci_platform_data[] = {
 180         {
 181                 .mapbase        = 0xffe00000,
 182                 .flags          = UPF_BOOT_AUTOCONF,
 183                 .type           = PORT_SCIF,
 184                 .irqs           = { 80, 80, 80, 80 },
 185         },
 186         {
 187                 .mapbase        = 0xffe10000,
 188                 .flags          = UPF_BOOT_AUTOCONF,
 189                 .type           = PORT_SCIF,
 190                 .irqs           = { 81, 81, 81, 81 },
 191         },
 192         {
 193                 .mapbase        = 0xffe20000,
 194                 .flags          = UPF_BOOT_AUTOCONF,
 195                 .type           = PORT_SCIF,
 196                 .irqs           = { 82, 82, 82, 82 },
 197         },
 198         {
 199                 .flags = 0,
 200         }
 201 };
 202
 203 static struct platform_device sci_device = {
 204         .name           = "sh-sci",
 205         .id             = -1,
 206         .dev            = {
 207                 .platform_data  = sci_platform_data,
 208         },
 209 };
 210
 211 static struct platform_device *sh7722_devices[] __initdata = {
 212         &rtc_device,
 213         &usbf_device,
 214         &iic_device,
 215         &sci_device,
 216         &vpu_device,
 217         &veu_device,
 218         &jpu_device,
 219 };
 220
 221 static int __init sh7722_devices_setup(void)
 222 {
 223         clk_always_enable("uram0"); /* URAM */
 224         clk_always_enable("xymem0"); /* XYMEM */
 225         clk_always_enable("rtc0"); /* RTC */
 226         clk_always_enable("veu0"); /* VEU */
 227         clk_always_enable("vpu0"); /* VPU */
 228         clk_always_enable("jpu0"); /* JPU */
 229
 230         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 231         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 232         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 233
 234         return platform_add_devices(sh7722_devices,
 235                                     ARRAY_SIZE(sh7722_devices));
 236 }
 237 __initcall(sh7722_devices_setup);
 238
 239 enum {
 240         UNUSED=0,
 241
 242         /* interrupt sources */
 243         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 244         HUDI,
 245         SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
 246         RTC_ATI, RTC_PRI, RTC_CUI,
 247         DMAC0, DMAC1, DMAC2, DMAC3,
 248         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 249         VPU, TPU,
 250         USB_USBI0, USB_USBI1,
 251         DMAC4, DMAC5, DMAC_DADERR,
 252         KEYSC,
 253         SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
 254         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 255         I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
 256         SDHI0, SDHI1, SDHI2, SDHI3,
 257         CMT, TSIF, SIU, TWODG,
 258         TMU0, TMU1, TMU2,
 259         IRDA, JPU, LCDC,
 260
 261         /* interrupt groups */
 262         SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
 263 };
 264
 265 static struct intc_vect vectors[] __initdata = {
 266         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 267         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 268         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 269         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 270         INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
 271         INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
 272         INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
 273         INTC_VECT(RTC_CUI, 0x7c0),
 274         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 275         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 276         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 277         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 278         INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
 279         INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
 280         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 281         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 282         INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
 283         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
 284         INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
 285         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 286         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 287         INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
 288         INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
 289         INTC_VECT(SDHI0, 0xe80), INTC_VECT(SDHI1, 0xea0),
 290         INTC_VECT(SDHI2, 0xec0), INTC_VECT(SDHI3, 0xee0),
 291         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 292         INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
 293         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 294         INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
 295         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 296 };
 297
 298 static struct intc_group groups[] __initdata = {
 299         INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
 300         INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
 301         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 302         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 303         INTC_GROUP(USB, USB_USBI0, USB_USBI1),
 304         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 305         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 306                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 307         INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
 308         INTC_GROUP(SDHI, SDHI0, SDHI1, SDHI2, SDHI3),
 309 };
 310
 311 static struct intc_mask_reg mask_registers[] __initdata = {
 312         { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
 313           { } },
 314         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 315           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 316         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 317           { 0, 0, 0, VPU, } },
 318         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 319           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 320         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 321           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 322         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 323           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
 324         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 325           { 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
 326         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 327           { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
 328             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 329         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 330           { SDHI3, SDHI2, SDHI1, SDHI0, 0, 0, TWODG, SIU } },
 331         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 332           { 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
 333         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 334           { } },
 335         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 336           { 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
 337         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 338           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 339 };
 340
 341 static struct intc_prio_reg prio_registers[] __initdata = {
 342         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
 343         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 344         { 0xa4080008, 0, 16, 4, /* IPRC */ { } },
 345         { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
 346         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
 347         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 348         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
 349         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
 350         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
 351         { 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
 352         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
 353         { 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
 354         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 355           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 356 };
 357
 358 static struct intc_sense_reg sense_registers[] __initdata = {
 359         { 0xa414001c, 16, 2, /* ICR1 */
 360           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 361 };
 362
 363 static struct intc_mask_reg ack_registers[] __initdata = {
 364         { 0xa4140024, 0, 8, /* INTREQ00 */
 365           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 366 };
 367
 368 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7722", vectors, groups,
 369                              mask_registers, prio_registers, sense_registers,
 370                              ack_registers);
 371
 372 void __init plat_irq_setup(void)
 373 {
 374         register_intc_controller(&intc_desc);
 375 }
 376
 377 void __init plat_mem_setup(void)
 378 {
 379         /* Register the URAM space as Node 1 */
 380         setup_bootmem_node(1, 0x055f0000, 0x05610000);
 381 }