arch/arm/plat-omap/include/mach/mcbsp.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/mcbsp.h
   3  *
   4  * Defines for Multi-Channel Buffered Serial Port
   5  *
   6  * Copyright (C) 2002 RidgeRun, Inc.
   7  * Author: Steve Johnson
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22  *
  23  */
  24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
  25 #define __ASM_ARCH_OMAP_MCBSP_H
  26
  27 #include <linux/completion.h>
  28 #include <linux/spinlock.h>
  29
  30 #include <mach/hardware.h>
  31 #include <mach/clock.h>
  32
  33 #define OMAP730_MCBSP1_BASE     0xfffb1000
  34 #define OMAP730_MCBSP2_BASE     0xfffb1800
  35
  36 #define OMAP1510_MCBSP1_BASE    0xe1011800
  37 #define OMAP1510_MCBSP2_BASE    0xfffb1000
  38 #define OMAP1510_MCBSP3_BASE    0xe1017000
  39
  40 #define OMAP1610_MCBSP1_BASE    0xe1011800
  41 #define OMAP1610_MCBSP2_BASE    0xfffb1000
  42 #define OMAP1610_MCBSP3_BASE    0xe1017000
  43
  44 #define OMAP24XX_MCBSP1_BASE    0x48074000
  45 #define OMAP24XX_MCBSP2_BASE    0x48076000
  46 #define OMAP2430_MCBSP3_BASE    0x4808c000
  47 #define OMAP2430_MCBSP4_BASE    0x4808e000
  48 #define OMAP2430_MCBSP5_BASE    0x48096000
  49
  50 #define OMAP34XX_MCBSP1_BASE    0x48074000
  51 #define OMAP34XX_MCBSP2_BASE    0x49022000
  52 #define OMAP34XX_MCBSP3_BASE    0x49024000
  53 #define OMAP34XX_MCBSP4_BASE    0x49026000
  54 #define OMAP34XX_MCBSP5_BASE    0x48096000
  55
  56 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
  57
  58 #define OMAP_MCBSP_REG_DRR2     0x00
  59 #define OMAP_MCBSP_REG_DRR1     0x02
  60 #define OMAP_MCBSP_REG_DXR2     0x04
  61 #define OMAP_MCBSP_REG_DXR1     0x06
  62 #define OMAP_MCBSP_REG_SPCR2    0x08
  63 #define OMAP_MCBSP_REG_SPCR1    0x0a
  64 #define OMAP_MCBSP_REG_RCR2     0x0c
  65 #define OMAP_MCBSP_REG_RCR1     0x0e
  66 #define OMAP_MCBSP_REG_XCR2     0x10
  67 #define OMAP_MCBSP_REG_XCR1     0x12
  68 #define OMAP_MCBSP_REG_SRGR2    0x14
  69 #define OMAP_MCBSP_REG_SRGR1    0x16
  70 #define OMAP_MCBSP_REG_MCR2     0x18
  71 #define OMAP_MCBSP_REG_MCR1     0x1a
  72 #define OMAP_MCBSP_REG_RCERA    0x1c
  73 #define OMAP_MCBSP_REG_RCERB    0x1e
  74 #define OMAP_MCBSP_REG_XCERA    0x20
  75 #define OMAP_MCBSP_REG_XCERB    0x22
  76 #define OMAP_MCBSP_REG_PCR0     0x24
  77 #define OMAP_MCBSP_REG_RCERC    0x26
  78 #define OMAP_MCBSP_REG_RCERD    0x28
  79 #define OMAP_MCBSP_REG_XCERC    0x2A
  80 #define OMAP_MCBSP_REG_XCERD    0x2C
  81 #define OMAP_MCBSP_REG_RCERE    0x2E
  82 #define OMAP_MCBSP_REG_RCERF    0x30
  83 #define OMAP_MCBSP_REG_XCERE    0x32
  84 #define OMAP_MCBSP_REG_XCERF    0x34
  85 #define OMAP_MCBSP_REG_RCERG    0x36
  86 #define OMAP_MCBSP_REG_RCERH    0x38
  87 #define OMAP_MCBSP_REG_XCERG    0x3A
  88 #define OMAP_MCBSP_REG_XCERH    0x3C
  89
  90 #define AUDIO_MCBSP_DATAWRITE   (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
  91 #define AUDIO_MCBSP_DATAREAD    (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
  92
  93 #define AUDIO_MCBSP             OMAP_MCBSP1
  94 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
  95 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
  96
  97 #elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
  98
  99 #define OMAP_MCBSP_REG_DRR2     0x00
 100 #define OMAP_MCBSP_REG_DRR1     0x04
 101 #define OMAP_MCBSP_REG_DXR2     0x08
 102 #define OMAP_MCBSP_REG_DXR1     0x0C
 103 #define OMAP_MCBSP_REG_DRR      0x00
 104 #define OMAP_MCBSP_REG_DXR      0x08
 105 #define OMAP_MCBSP_REG_SPCR2    0x10
 106 #define OMAP_MCBSP_REG_SPCR1    0x14
 107 #define OMAP_MCBSP_REG_RCR2     0x18
 108 #define OMAP_MCBSP_REG_RCR1     0x1C
 109 #define OMAP_MCBSP_REG_XCR2     0x20
 110 #define OMAP_MCBSP_REG_XCR1     0x24
 111 #define OMAP_MCBSP_REG_SRGR2    0x28
 112 #define OMAP_MCBSP_REG_SRGR1    0x2C
 113 #define OMAP_MCBSP_REG_MCR2     0x30
 114 #define OMAP_MCBSP_REG_MCR1     0x34
 115 #define OMAP_MCBSP_REG_RCERA    0x38
 116 #define OMAP_MCBSP_REG_RCERB    0x3C
 117 #define OMAP_MCBSP_REG_XCERA    0x40
 118 #define OMAP_MCBSP_REG_XCERB    0x44
 119 #define OMAP_MCBSP_REG_PCR0     0x48
 120 #define OMAP_MCBSP_REG_RCERC    0x4C
 121 #define OMAP_MCBSP_REG_RCERD    0x50
 122 #define OMAP_MCBSP_REG_XCERC    0x54
 123 #define OMAP_MCBSP_REG_XCERD    0x58
 124 #define OMAP_MCBSP_REG_RCERE    0x5C
 125 #define OMAP_MCBSP_REG_RCERF    0x60
 126 #define OMAP_MCBSP_REG_XCERE    0x64
 127 #define OMAP_MCBSP_REG_XCERF    0x68
 128 #define OMAP_MCBSP_REG_RCERG    0x6C
 129 #define OMAP_MCBSP_REG_RCERH    0x70
 130 #define OMAP_MCBSP_REG_XCERG    0x74
 131 #define OMAP_MCBSP_REG_XCERH    0x78
 132 #define OMAP_MCBSP_REG_SYSCON   0x8C
 133 #define OMAP_MCBSP_REG_XCCR     0xAC
 134 #define OMAP_MCBSP_REG_RCCR     0xB0
 135
 136 #define AUDIO_MCBSP_DATAWRITE   (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
 137 #define AUDIO_MCBSP_DATAREAD    (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
 138
 139 #define AUDIO_MCBSP             OMAP_MCBSP2
 140 #define AUDIO_DMA_TX            OMAP24XX_DMA_MCBSP2_TX
 141 #define AUDIO_DMA_RX            OMAP24XX_DMA_MCBSP2_RX
 142
 143 #endif
 144
 145 /************************** McBSP SPCR1 bit definitions ***********************/
 146 #define RRST                    0x0001
 147 #define RRDY                    0x0002
 148 #define RFULL                   0x0004
 149 #define RSYNC_ERR               0x0008
 150 #define RINTM(value)            ((value)<<4)    /* bits 4:5 */
 151 #define ABIS                    0x0040
 152 #define DXENA                   0x0080
 153 #define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
 154 #define RJUST(value)            ((value)<<13)   /* bits 13:14 */
 155 #define ALB                     0x8000
 156 #define DLB                     0x8000
 157
 158 /************************** McBSP SPCR2 bit definitions ***********************/
 159 #define XRST            0x0001
 160 #define XRDY            0x0002
 161 #define XEMPTY          0x0004
 162 #define XSYNC_ERR       0x0008
 163 #define XINTM(value)    ((value)<<4)            /* bits 4:5 */
 164 #define GRST            0x0040
 165 #define FRST            0x0080
 166 #define SOFT            0x0100
 167 #define FREE            0x0200
 168
 169 /************************** McBSP PCR bit definitions *************************/
 170 #define CLKRP           0x0001
 171 #define CLKXP           0x0002
 172 #define FSRP            0x0004
 173 #define FSXP            0x0008
 174 #define DR_STAT         0x0010
 175 #define DX_STAT         0x0020
 176 #define CLKS_STAT       0x0040
 177 #define SCLKME          0x0080
 178 #define CLKRM           0x0100
 179 #define CLKXM           0x0200
 180 #define FSRM            0x0400
 181 #define FSXM            0x0800
 182 #define RIOEN           0x1000
 183 #define XIOEN           0x2000
 184 #define IDLE_EN         0x4000
 185
 186 /************************** McBSP RCR1 bit definitions ************************/
 187 #define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 188 #define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 189
 190 /************************** McBSP XCR1 bit definitions ************************/
 191 #define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
 192 #define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
 193
 194 /*************************** McBSP RCR2 bit definitions ***********************/
 195 #define RDATDLY(value)          (value)         /* Bits 0:1 */
 196 #define RFIG                    0x0004
 197 #define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 198 #define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 199 #define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 200 #define RPHASE                  0x8000
 201
 202 /*************************** McBSP XCR2 bit definitions ***********************/
 203 #define XDATDLY(value)          (value)         /* Bits 0:1 */
 204 #define XFIG                    0x0004
 205 #define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
 206 #define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
 207 #define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
 208 #define XPHASE                  0x8000
 209
 210 /************************* McBSP SRGR1 bit definitions ************************/
 211 #define CLKGDV(value)           (value)         /* Bits 0:7 */
 212 #define FWID(value)             ((value)<<8)    /* Bits 8:15 */
 213
 214 /************************* McBSP SRGR2 bit definitions ************************/
 215 #define FPER(value)             (value)         /* Bits 0:11 */
 216 #define FSGM                    0x1000
 217 #define CLKSM                   0x2000
 218 #define CLKSP                   0x4000
 219 #define GSYNC                   0x8000
 220
 221 /************************* McBSP MCR1 bit definitions *************************/
 222 #define RMCM                    0x0001
 223 #define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 224 #define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 225 #define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 226
 227 /************************* McBSP MCR2 bit definitions *************************/
 228 #define XMCM(value)             (value)         /* Bits 0:1 */
 229 #define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
 230 #define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
 231 #define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
 232
 233 /*********************** McBSP XCCR bit definitions *************************/
 234 #define DILB                    0x0020
 235 #define XDMAEN                  0x0008
 236 #define XDISABLE                0x0001
 237
 238 /********************** McBSP RCCR bit definitions *************************/
 239 #define RDMAEN                  0x0008
 240 #define RDISABLE                0x0001
 241
 242 /********************** McBSP SYSCONFIG bit definitions ********************/
 243 #define SOFTRST                 0x0002
 244
 245 /* we don't do multichannel for now */
 246 struct omap_mcbsp_reg_cfg {
 247         u16 spcr2;
 248         u16 spcr1;
 249         u16 rcr2;
 250         u16 rcr1;
 251         u16 xcr2;
 252         u16 xcr1;
 253         u16 srgr2;
 254         u16 srgr1;
 255         u16 mcr2;
 256         u16 mcr1;
 257         u16 pcr0;
 258         u16 rcerc;
 259         u16 rcerd;
 260         u16 xcerc;
 261         u16 xcerd;
 262         u16 rcere;
 263         u16 rcerf;
 264         u16 xcere;
 265         u16 xcerf;
 266         u16 rcerg;
 267         u16 rcerh;
 268         u16 xcerg;
 269         u16 xcerh;
 270 };
 271
 272 typedef enum {
 273         OMAP_MCBSP1 = 0,
 274         OMAP_MCBSP2,
 275         OMAP_MCBSP3,
 276         OMAP_MCBSP4,
 277         OMAP_MCBSP5
 278 } omap_mcbsp_id;
 279
 280 typedef int __bitwise omap_mcbsp_io_type_t;
 281 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
 282 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
 283
 284 typedef enum {
 285         OMAP_MCBSP_WORD_8 = 0,
 286         OMAP_MCBSP_WORD_12,
 287         OMAP_MCBSP_WORD_16,
 288         OMAP_MCBSP_WORD_20,
 289         OMAP_MCBSP_WORD_24,
 290         OMAP_MCBSP_WORD_32,
 291 } omap_mcbsp_word_length;
 292
 293 typedef enum {
 294         OMAP_MCBSP_CLK_RISING = 0,
 295         OMAP_MCBSP_CLK_FALLING,
 296 } omap_mcbsp_clk_polarity;
 297
 298 typedef enum {
 299         OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
 300         OMAP_MCBSP_FS_ACTIVE_LOW,
 301 } omap_mcbsp_fs_polarity;
 302
 303 typedef enum {
 304         OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
 305         OMAP_MCBSP_CLK_STP_MODE_DELAY,
 306 } omap_mcbsp_clk_stp_mode;
 307
 308
 309 /******* SPI specific mode **********/
 310 typedef enum {
 311         OMAP_MCBSP_SPI_MASTER = 0,
 312         OMAP_MCBSP_SPI_SLAVE,
 313 } omap_mcbsp_spi_mode;
 314
 315 struct omap_mcbsp_spi_cfg {
 316         omap_mcbsp_spi_mode             spi_mode;
 317         omap_mcbsp_clk_polarity         rx_clock_polarity;
 318         omap_mcbsp_clk_polarity         tx_clock_polarity;
 319         omap_mcbsp_fs_polarity          fsx_polarity;
 320         u8                              clk_div;
 321         omap_mcbsp_clk_stp_mode         clk_stp_mode;
 322         omap_mcbsp_word_length          word_length;
 323 };
 324
 325 /* Platform specific configuration */
 326 struct omap_mcbsp_ops {
 327         void (*request)(unsigned int);
 328         void (*free)(unsigned int);
 329 };
 330
 331 struct omap_mcbsp_platform_data {
 332         unsigned long phys_base;
 333         u8 dma_rx_sync, dma_tx_sync;
 334         u16 rx_irq, tx_irq;
 335         struct omap_mcbsp_ops *ops;
 336         char const *clk_name;
 337 };
 338
 339 struct omap_mcbsp {
 340         struct device *dev;
 341         unsigned long phys_base;
 342         void __iomem *io_base;
 343         u8 id;
 344         u8 free;
 345         omap_mcbsp_word_length rx_word_length;
 346         omap_mcbsp_word_length tx_word_length;
 347
 348         omap_mcbsp_io_type_t io_type; /* IRQ or poll */
 349         /* IRQ based TX/RX */
 350         int rx_irq;
 351         int tx_irq;
 352
 353         /* DMA stuff */
 354         u8 dma_rx_sync;
 355         short dma_rx_lch;
 356         u8 dma_tx_sync;
 357         short dma_tx_lch;
 358
 359         /* Completion queues */
 360         struct completion tx_irq_completion;
 361         struct completion rx_irq_completion;
 362         struct completion tx_dma_completion;
 363         struct completion rx_dma_completion;
 364
 365         /* Protect the field .free, while checking if the mcbsp is in use */
 366         spinlock_t lock;
 367         struct omap_mcbsp_platform_data *pdata;
 368         struct clk *clk;
 369 };
 370 extern struct omap_mcbsp **mcbsp_ptr;
 371 extern int omap_mcbsp_count;
 372
 373 int omap_mcbsp_init(void);
 374 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 375                                         int size);
 376 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 377 int omap_mcbsp_request(unsigned int id);
 378 void omap_mcbsp_free(unsigned int id);
 379 void omap_mcbsp_start(unsigned int id);
 380 void omap_mcbsp_stop(unsigned int id);
 381 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
 382 u32 omap_mcbsp_recv_word(unsigned int id);
 383
 384 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 385 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
 386 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
 387 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
 388
 389
 390 /* SPI specific API */
 391 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
 392
 393 /* Polled read/write functions */
 394 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
 395 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
 396 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 397
 398 #endif