include/asm-blackfin/mach-bf527/anomaly.h

   1 /*
   2  * File: include/asm-blackfin/mach-bf527/anomaly.h
   3  * Bugs: Enter bugs at http://blackfin.uclinux.org/
   4  *
   5  * Copyright (C) 2004-2007 Analog Devices Inc.
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 /* This file shoule be up to date with:
  10  *  - Revision A, May 30, 2007; ADSP-BF527 Blackfin Processor Anomaly List
  11  */
  12
  13 #ifndef _MACH_ANOMALY_H_
  14 #define _MACH_ANOMALY_H_
  15
  16 /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
  17 #define ANOMALY_05000074 (1)
  18 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
  19 #define ANOMALY_05000119 (1)
  20 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
  21 #define ANOMALY_05000122 (1)
  22 /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
  23 #define ANOMALY_05000245 (1)
  24 /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
  25 #define ANOMALY_05000265 (1)
  26 /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
  27 #define ANOMALY_05000301 (1)
  28 /* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
  29 #define ANOMALY_05000312 (1)
  30 /* Incorrect Access of OTP_STATUS During otp_write() Function */
  31 #define ANOMALY_05000328 (1)
  32 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
  33 #define ANOMALY_05000337 (1)
  34 /* TWI Does Not Operate Correctly Under Certain Signal Termination Conditions */
  35 #define ANOMALY_05000342 (1)
  36 /* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
  37 #define ANOMALY_05000347 (1)
  38
  39 /* Anomalies that don't exist on this proc */
  40 #define ANOMALY_05000323 (0)
  41 #define ANOMALY_05000244 (0)
  42 #define ANOMALY_05000198 (0)
  43 #define ANOMALY_05000125 (0)
  44 #define ANOMALY_05000158 (0)
  45 #define ANOMALY_05000273 (0)
  46 #define ANOMALY_05000263 (0)
  47 #define ANOMALY_05000311 (0)
  48 #define ANOMALY_05000230 (0)
  49 #endif