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ide-pci-generic: kill the unused ifdef/endif/MODULE code
[linux-2.6/openmoko-kernel/knife-kernel.git] / drivers / net / igb / igb_main.c
blobd4eb8e2d87202b681cff99ff6cd8ec1eec1f3664
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/module.h>
29 #include <linux/types.h>
30 #include <linux/init.h>
31 #include <linux/vmalloc.h>
32 #include <linux/pagemap.h>
33 #include <linux/netdevice.h>
34 #include <linux/tcp.h>
35 #include <linux/ipv6.h>
36 #include <net/checksum.h>
37 #include <net/ip6_checksum.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if_vlan.h>
41 #include <linux/pci.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/if_ether.h>
45
46 #include "igb.h"
47
48 #define DRV_VERSION "1.0.8-k2"
49 char igb_driver_name[] = "igb";
50 char igb_driver_version[] = DRV_VERSION;
51 static const char igb_driver_string[] =
52 "Intel(R) Gigabit Ethernet Network Driver";
53 static const char igb_copyright[] = "Copyright (c) 2007 Intel Corporation.";
54
55
56 static const struct e1000_info *igb_info_tbl[] = {
57 [board_82575] = &e1000_82575_info,
58 };
59
60 static struct pci_device_id igb_pci_tbl[] = {
61 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
62 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
63 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
64 /* required last entry */
65 {0, }
66 };
67
68 MODULE_DEVICE_TABLE(pci, igb_pci_tbl);
69
70 void igb_reset(struct igb_adapter *);
71 static int igb_setup_all_tx_resources(struct igb_adapter *);
72 static int igb_setup_all_rx_resources(struct igb_adapter *);
73 static void igb_free_all_tx_resources(struct igb_adapter *);
74 static void igb_free_all_rx_resources(struct igb_adapter *);
75 static void igb_free_tx_resources(struct igb_adapter *, struct igb_ring *);
76 static void igb_free_rx_resources(struct igb_adapter *, struct igb_ring *);
77 void igb_update_stats(struct igb_adapter *);
78 static int igb_probe(struct pci_dev *, const struct pci_device_id *);
79 static void __devexit igb_remove(struct pci_dev *pdev);
80 static int igb_sw_init(struct igb_adapter *);
81 static int igb_open(struct net_device *);
82 static int igb_close(struct net_device *);
83 static void igb_configure_tx(struct igb_adapter *);
84 static void igb_configure_rx(struct igb_adapter *);
85 static void igb_setup_rctl(struct igb_adapter *);
86 static void igb_clean_all_tx_rings(struct igb_adapter *);
87 static void igb_clean_all_rx_rings(struct igb_adapter *);
88 static void igb_clean_tx_ring(struct igb_adapter *, struct igb_ring *);
89 static void igb_clean_rx_ring(struct igb_adapter *, struct igb_ring *);
90 static void igb_set_multi(struct net_device *);
91 static void igb_update_phy_info(unsigned long);
92 static void igb_watchdog(unsigned long);
93 static void igb_watchdog_task(struct work_struct *);
94 static int igb_xmit_frame_ring_adv(struct sk_buff *, struct net_device *,
95 struct igb_ring *);
96 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *);
97 static struct net_device_stats *igb_get_stats(struct net_device *);
98 static int igb_change_mtu(struct net_device *, int);
99 static int igb_set_mac(struct net_device *, void *);
100 static irqreturn_t igb_intr(int irq, void *);
101 static irqreturn_t igb_intr_msi(int irq, void *);
102 static irqreturn_t igb_msix_other(int irq, void *);
103 static irqreturn_t igb_msix_rx(int irq, void *);
104 static irqreturn_t igb_msix_tx(int irq, void *);
105 static int igb_clean_rx_ring_msix(struct napi_struct *, int);
106 static bool igb_clean_tx_irq(struct igb_adapter *, struct igb_ring *);
107 static int igb_clean(struct napi_struct *, int);
108 static bool igb_clean_rx_irq_adv(struct igb_adapter *,
109 struct igb_ring *, int *, int);
110 static void igb_alloc_rx_buffers_adv(struct igb_adapter *,
111 struct igb_ring *, int);
112 static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
113 static void igb_tx_timeout(struct net_device *);
114 static void igb_reset_task(struct work_struct *);
115 static void igb_vlan_rx_register(struct net_device *, struct vlan_group *);
116 static void igb_vlan_rx_add_vid(struct net_device *, u16);
117 static void igb_vlan_rx_kill_vid(struct net_device *, u16);
118 static void igb_restore_vlan(struct igb_adapter *);
119
120 static int igb_suspend(struct pci_dev *, pm_message_t);
121 #ifdef CONFIG_PM
122 static int igb_resume(struct pci_dev *);
123 #endif
124 static void igb_shutdown(struct pci_dev *);
125
126 #ifdef CONFIG_NET_POLL_CONTROLLER
127 /* for netdump / net console */
128 static void igb_netpoll(struct net_device *);
129 #endif
130
131 static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
132 pci_channel_state_t);
133 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
134 static void igb_io_resume(struct pci_dev *);
135
136 static struct pci_error_handlers igb_err_handler = {
137 .error_detected = igb_io_error_detected,
138 .slot_reset = igb_io_slot_reset,
139 .resume = igb_io_resume,
140 };
141
142
143 static struct pci_driver igb_driver = {
144 .name = igb_driver_name,
145 .id_table = igb_pci_tbl,
146 .probe = igb_probe,
147 .remove = __devexit_p(igb_remove),
148 #ifdef CONFIG_PM
149 /* Power Managment Hooks */
150 .suspend = igb_suspend,
151 .resume = igb_resume,
152 #endif
153 .shutdown = igb_shutdown,
154 .err_handler = &igb_err_handler
155 };
156
157 MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
158 MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
159 MODULE_LICENSE("GPL");
160 MODULE_VERSION(DRV_VERSION);
161
162 #ifdef DEBUG
163 /**
164 * igb_get_hw_dev_name - return device name string
165 * used by hardware layer to print debugging information
166 **/
167 char *igb_get_hw_dev_name(struct e1000_hw *hw)
168 {
169 struct igb_adapter *adapter = hw->back;
170 return adapter->netdev->name;
171 }
172 #endif
173
174 /**
175 * igb_init_module - Driver Registration Routine
176 *
177 * igb_init_module is the first routine called when the driver is
178 * loaded. All it does is register with the PCI subsystem.
179 **/
180 static int __init igb_init_module(void)
181 {
182 int ret;
183 printk(KERN_INFO "%s - version %s\n",
184 igb_driver_string, igb_driver_version);
185
186 printk(KERN_INFO "%s\n", igb_copyright);
187
188 ret = pci_register_driver(&igb_driver);
189 return ret;
190 }
191
192 module_init(igb_init_module);
193
194 /**
195 * igb_exit_module - Driver Exit Cleanup Routine
196 *
197 * igb_exit_module is called just before the driver is removed
198 * from memory.
199 **/
200 static void __exit igb_exit_module(void)
201 {
202 pci_unregister_driver(&igb_driver);
203 }
204
205 module_exit(igb_exit_module);
206
207 /**
208 * igb_alloc_queues - Allocate memory for all rings
209 * @adapter: board private structure to initialize
210 *
211 * We allocate one ring per queue at run-time since we don't know the
212 * number of queues at compile-time.
213 **/
214 static int igb_alloc_queues(struct igb_adapter *adapter)
215 {
216 int i;
217
218 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
219 sizeof(struct igb_ring), GFP_KERNEL);
220 if (!adapter->tx_ring)
221 return -ENOMEM;
222
223 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
224 sizeof(struct igb_ring), GFP_KERNEL);
225 if (!adapter->rx_ring) {
226 kfree(adapter->tx_ring);
227 return -ENOMEM;
228 }
229
230 for (i = 0; i < adapter->num_rx_queues; i++) {
231 struct igb_ring *ring = &(adapter->rx_ring[i]);
232 ring->adapter = adapter;
233 ring->itr_register = E1000_ITR;
234
235 if (!ring->napi.poll)
236 netif_napi_add(adapter->netdev, &ring->napi, igb_clean,
237 adapter->napi.weight /
238 adapter->num_rx_queues);
239 }
240 return 0;
241 }
242
243 #define IGB_N0_QUEUE -1
244 static void igb_assign_vector(struct igb_adapter *adapter, int rx_queue,
245 int tx_queue, int msix_vector)
246 {
247 u32 msixbm = 0;
248 struct e1000_hw *hw = &adapter->hw;
249 /* The 82575 assigns vectors using a bitmask, which matches the
250 bitmask for the EICR/EIMS/EIMC registers. To assign one
251 or more queues to a vector, we write the appropriate bits
252 into the MSIXBM register for that vector. */
253 if (rx_queue > IGB_N0_QUEUE) {
254 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
255 adapter->rx_ring[rx_queue].eims_value = msixbm;
256 }
257 if (tx_queue > IGB_N0_QUEUE) {
258 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
259 adapter->tx_ring[tx_queue].eims_value =
260 E1000_EICR_TX_QUEUE0 << tx_queue;
261 }
262 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
263 }
264
265 /**
266 * igb_configure_msix - Configure MSI-X hardware
267 *
268 * igb_configure_msix sets up the hardware to properly
269 * generate MSI-X interrupts.
270 **/
271 static void igb_configure_msix(struct igb_adapter *adapter)
272 {
273 u32 tmp;
274 int i, vector = 0;
275 struct e1000_hw *hw = &adapter->hw;
276
277 adapter->eims_enable_mask = 0;
278
279 for (i = 0; i < adapter->num_tx_queues; i++) {
280 struct igb_ring *tx_ring = &adapter->tx_ring[i];
281 igb_assign_vector(adapter, IGB_N0_QUEUE, i, vector++);
282 adapter->eims_enable_mask |= tx_ring->eims_value;
283 if (tx_ring->itr_val)
284 writel(1000000000 / (tx_ring->itr_val * 256),
285 hw->hw_addr + tx_ring->itr_register);
286 else
287 writel(1, hw->hw_addr + tx_ring->itr_register);
288 }
289
290 for (i = 0; i < adapter->num_rx_queues; i++) {
291 struct igb_ring *rx_ring = &adapter->rx_ring[i];
292 igb_assign_vector(adapter, i, IGB_N0_QUEUE, vector++);
293 adapter->eims_enable_mask |= rx_ring->eims_value;
294 if (rx_ring->itr_val)
295 writel(1000000000 / (rx_ring->itr_val * 256),
296 hw->hw_addr + rx_ring->itr_register);
297 else
298 writel(1, hw->hw_addr + rx_ring->itr_register);
299 }
300
301
302 /* set vector for other causes, i.e. link changes */
303 array_wr32(E1000_MSIXBM(0), vector++,
304 E1000_EIMS_OTHER);
305
306 /* disable IAM for ICR interrupt bits */
307 wr32(E1000_IAM, 0);
308
309 tmp = rd32(E1000_CTRL_EXT);
310 /* enable MSI-X PBA support*/
311 tmp |= E1000_CTRL_EXT_PBA_CLR;
312
313 /* Auto-Mask interrupts upon ICR read. */
314 tmp |= E1000_CTRL_EXT_EIAME;
315 tmp |= E1000_CTRL_EXT_IRCA;
316
317 wr32(E1000_CTRL_EXT, tmp);
318 adapter->eims_enable_mask |= E1000_EIMS_OTHER;
319
320 wrfl();
321 }
322
323 /**
324 * igb_request_msix - Initialize MSI-X interrupts
325 *
326 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
327 * kernel.
328 **/
329 static int igb_request_msix(struct igb_adapter *adapter)
330 {
331 struct net_device *netdev = adapter->netdev;
332 int i, err = 0, vector = 0;
333
334 vector = 0;
335
336 for (i = 0; i < adapter->num_tx_queues; i++) {
337 struct igb_ring *ring = &(adapter->tx_ring[i]);
338 sprintf(ring->name, "%s-tx%d", netdev->name, i);
339 err = request_irq(adapter->msix_entries[vector].vector,
340 &igb_msix_tx, 0, ring->name,
341 &(adapter->tx_ring[i]));
342 if (err)
343 goto out;
344 ring->itr_register = E1000_EITR(0) + (vector << 2);
345 ring->itr_val = adapter->itr;
346 vector++;
347 }
348 for (i = 0; i < adapter->num_rx_queues; i++) {
349 struct igb_ring *ring = &(adapter->rx_ring[i]);
350 if (strlen(netdev->name) < (IFNAMSIZ - 5))
351 sprintf(ring->name, "%s-rx%d", netdev->name, i);
352 else
353 memcpy(ring->name, netdev->name, IFNAMSIZ);
354 err = request_irq(adapter->msix_entries[vector].vector,
355 &igb_msix_rx, 0, ring->name,
356 &(adapter->rx_ring[i]));
357 if (err)
358 goto out;
359 ring->itr_register = E1000_EITR(0) + (vector << 2);
360 ring->itr_val = adapter->itr;
361 vector++;
362 }
363
364 err = request_irq(adapter->msix_entries[vector].vector,
365 &igb_msix_other, 0, netdev->name, netdev);
366 if (err)
367 goto out;
368
369 adapter->napi.poll = igb_clean_rx_ring_msix;
370 for (i = 0; i < adapter->num_rx_queues; i++)
371 adapter->rx_ring[i].napi.poll = adapter->napi.poll;
372 igb_configure_msix(adapter);
373 return 0;
374 out:
375 return err;
376 }
377
378 static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
379 {
380 if (adapter->msix_entries) {
381 pci_disable_msix(adapter->pdev);
382 kfree(adapter->msix_entries);
383 adapter->msix_entries = NULL;
384 } else if (adapter->msi_enabled)
385 pci_disable_msi(adapter->pdev);
386 return;
387 }
388
389
390 /**
391 * igb_set_interrupt_capability - set MSI or MSI-X if supported
392 *
393 * Attempt to configure interrupts using the best available
394 * capabilities of the hardware and kernel.
395 **/
396 static void igb_set_interrupt_capability(struct igb_adapter *adapter)
397 {
398 int err;
399 int numvecs, i;
400
401 numvecs = adapter->num_tx_queues + adapter->num_rx_queues + 1;
402 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
403 GFP_KERNEL);
404 if (!adapter->msix_entries)
405 goto msi_only;
406
407 for (i = 0; i < numvecs; i++)
408 adapter->msix_entries[i].entry = i;
409
410 err = pci_enable_msix(adapter->pdev,
411 adapter->msix_entries,
412 numvecs);
413 if (err == 0)
414 return;
415
416 igb_reset_interrupt_capability(adapter);
417
418 /* If we can't do MSI-X, try MSI */
419 msi_only:
420 adapter->num_rx_queues = 1;
421 if (!pci_enable_msi(adapter->pdev))
422 adapter->msi_enabled = 1;
423 return;
424 }
425
426 /**
427 * igb_request_irq - initialize interrupts
428 *
429 * Attempts to configure interrupts using the best available
430 * capabilities of the hardware and kernel.
431 **/
432 static int igb_request_irq(struct igb_adapter *adapter)
433 {
434 struct net_device *netdev = adapter->netdev;
435 struct e1000_hw *hw = &adapter->hw;
436 int err = 0;
437
438 if (adapter->msix_entries) {
439 err = igb_request_msix(adapter);
440 if (!err) {
441 /* enable IAM, auto-mask,
442 * DO NOT USE EIAME or IAME in legacy mode */
443 wr32(E1000_IAM, IMS_ENABLE_MASK);
444 goto request_done;
445 }
446 /* fall back to MSI */
447 igb_reset_interrupt_capability(adapter);
448 if (!pci_enable_msi(adapter->pdev))
449 adapter->msi_enabled = 1;
450 igb_free_all_tx_resources(adapter);
451 igb_free_all_rx_resources(adapter);
452 adapter->num_rx_queues = 1;
453 igb_alloc_queues(adapter);
454 }
455 if (adapter->msi_enabled) {
456 err = request_irq(adapter->pdev->irq, &igb_intr_msi, 0,
457 netdev->name, netdev);
458 if (!err)
459 goto request_done;
460 /* fall back to legacy interrupts */
461 igb_reset_interrupt_capability(adapter);
462 adapter->msi_enabled = 0;
463 }
464
465 err = request_irq(adapter->pdev->irq, &igb_intr, IRQF_SHARED,
466 netdev->name, netdev);
467
468 if (err) {
469 dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
470 err);
471 goto request_done;
472 }
473
474 /* enable IAM, auto-mask */
475 wr32(E1000_IAM, IMS_ENABLE_MASK);
476
477 request_done:
478 return err;
479 }
480
481 static void igb_free_irq(struct igb_adapter *adapter)
482 {
483 struct net_device *netdev = adapter->netdev;
484
485 if (adapter->msix_entries) {
486 int vector = 0, i;
487
488 for (i = 0; i < adapter->num_tx_queues; i++)
489 free_irq(adapter->msix_entries[vector++].vector,
490 &(adapter->tx_ring[i]));
491 for (i = 0; i < adapter->num_rx_queues; i++)
492 free_irq(adapter->msix_entries[vector++].vector,
493 &(adapter->rx_ring[i]));
494
495 free_irq(adapter->msix_entries[vector++].vector, netdev);
496 return;
497 }
498
499 free_irq(adapter->pdev->irq, netdev);
500 }
501
502 /**
503 * igb_irq_disable - Mask off interrupt generation on the NIC
504 * @adapter: board private structure
505 **/
506 static void igb_irq_disable(struct igb_adapter *adapter)
507 {
508 struct e1000_hw *hw = &adapter->hw;
509
510 if (adapter->msix_entries) {
511 wr32(E1000_EIMC, ~0);
512 wr32(E1000_EIAC, 0);
513 }
514 wr32(E1000_IMC, ~0);
515 wrfl();
516 synchronize_irq(adapter->pdev->irq);
517 }
518
519 /**
520 * igb_irq_enable - Enable default interrupt generation settings
521 * @adapter: board private structure
522 **/
523 static void igb_irq_enable(struct igb_adapter *adapter)
524 {
525 struct e1000_hw *hw = &adapter->hw;
526
527 if (adapter->msix_entries) {
528 wr32(E1000_EIMS,
529 adapter->eims_enable_mask);
530 wr32(E1000_EIAC,
531 adapter->eims_enable_mask);
532 wr32(E1000_IMS, E1000_IMS_LSC);
533 } else
534 wr32(E1000_IMS, IMS_ENABLE_MASK);
535 }
536
537 static void igb_update_mng_vlan(struct igb_adapter *adapter)
538 {
539 struct net_device *netdev = adapter->netdev;
540 u16 vid = adapter->hw.mng_cookie.vlan_id;
541 u16 old_vid = adapter->mng_vlan_id;
542 if (adapter->vlgrp) {
543 if (!vlan_group_get_device(adapter->vlgrp, vid)) {
544 if (adapter->hw.mng_cookie.status &
545 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
546 igb_vlan_rx_add_vid(netdev, vid);
547 adapter->mng_vlan_id = vid;
548 } else
549 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
550
551 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
552 (vid != old_vid) &&
553 !vlan_group_get_device(adapter->vlgrp, old_vid))
554 igb_vlan_rx_kill_vid(netdev, old_vid);
555 } else
556 adapter->mng_vlan_id = vid;
557 }
558 }
559
560 /**
561 * igb_release_hw_control - release control of the h/w to f/w
562 * @adapter: address of board private structure
563 *
564 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
565 * For ASF and Pass Through versions of f/w this means that the
566 * driver is no longer loaded.
567 *
568 **/
569 static void igb_release_hw_control(struct igb_adapter *adapter)
570 {
571 struct e1000_hw *hw = &adapter->hw;
572 u32 ctrl_ext;
573
574 /* Let firmware take over control of h/w */
575 ctrl_ext = rd32(E1000_CTRL_EXT);
576 wr32(E1000_CTRL_EXT,
577 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
578 }
579
580
581 /**
582 * igb_get_hw_control - get control of the h/w from f/w
583 * @adapter: address of board private structure
584 *
585 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
586 * For ASF and Pass Through versions of f/w this means that
587 * the driver is loaded.
588 *
589 **/
590 static void igb_get_hw_control(struct igb_adapter *adapter)
591 {
592 struct e1000_hw *hw = &adapter->hw;
593 u32 ctrl_ext;
594
595 /* Let firmware know the driver has taken over */
596 ctrl_ext = rd32(E1000_CTRL_EXT);
597 wr32(E1000_CTRL_EXT,
598 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
599 }
600
601 static void igb_init_manageability(struct igb_adapter *adapter)
602 {
603 struct e1000_hw *hw = &adapter->hw;
604
605 if (adapter->en_mng_pt) {
606 u32 manc2h = rd32(E1000_MANC2H);
607 u32 manc = rd32(E1000_MANC);
608
609 /* disable hardware interception of ARP */
610 manc &= ~(E1000_MANC_ARP_EN);
611
612 /* enable receiving management packets to the host */
613 /* this will probably generate destination unreachable messages
614 * from the host OS, but the packets will be handled on SMBUS */
615 manc |= E1000_MANC_EN_MNG2HOST;
616 #define E1000_MNG2HOST_PORT_623 (1 << 5)
617 #define E1000_MNG2HOST_PORT_664 (1 << 6)
618 manc2h |= E1000_MNG2HOST_PORT_623;
619 manc2h |= E1000_MNG2HOST_PORT_664;
620 wr32(E1000_MANC2H, manc2h);
621
622 wr32(E1000_MANC, manc);
623 }
624 }
625
626 static void igb_release_manageability(struct igb_adapter *adapter)
627 {
628 struct e1000_hw *hw = &adapter->hw;
629
630 if (adapter->en_mng_pt) {
631 u32 manc = rd32(E1000_MANC);
632
633 /* re-enable hardware interception of ARP */
634 manc |= E1000_MANC_ARP_EN;
635 manc &= ~E1000_MANC_EN_MNG2HOST;
636
637 /* don't explicitly have to mess with MANC2H since
638 * MANC has an enable disable that gates MANC2H */
639
640 /* XXX stop the hardware watchdog ? */
641 wr32(E1000_MANC, manc);
642 }
643 }
644
645 /**
646 * igb_configure - configure the hardware for RX and TX
647 * @adapter: private board structure
648 **/
649 static void igb_configure(struct igb_adapter *adapter)
650 {
651 struct net_device *netdev = adapter->netdev;
652 int i;
653
654 igb_get_hw_control(adapter);
655 igb_set_multi(netdev);
656
657 igb_restore_vlan(adapter);
658 igb_init_manageability(adapter);
659
660 igb_configure_tx(adapter);
661 igb_setup_rctl(adapter);
662 igb_configure_rx(adapter);
663 /* call IGB_DESC_UNUSED which always leaves
664 * at least 1 descriptor unused to make sure
665 * next_to_use != next_to_clean */
666 for (i = 0; i < adapter->num_rx_queues; i++) {
667 struct igb_ring *ring = &adapter->rx_ring[i];
668 igb_alloc_rx_buffers_adv(adapter, ring, IGB_DESC_UNUSED(ring));
669 }
670
671
672 adapter->tx_queue_len = netdev->tx_queue_len;
673 }
674
675
676 /**
677 * igb_up - Open the interface and prepare it to handle traffic
678 * @adapter: board private structure
679 **/
680
681 int igb_up(struct igb_adapter *adapter)
682 {
683 struct e1000_hw *hw = &adapter->hw;
684 int i;
685
686 /* hardware has been reset, we need to reload some things */
687 igb_configure(adapter);
688
689 clear_bit(__IGB_DOWN, &adapter->state);
690
691 napi_enable(&adapter->napi);
692
693 if (adapter->msix_entries) {
694 for (i = 0; i < adapter->num_rx_queues; i++)
695 napi_enable(&adapter->rx_ring[i].napi);
696 igb_configure_msix(adapter);
697 }
698
699 /* Clear any pending interrupts. */
700 rd32(E1000_ICR);
701 igb_irq_enable(adapter);
702
703 /* Fire a link change interrupt to start the watchdog. */
704 wr32(E1000_ICS, E1000_ICS_LSC);
705 return 0;
706 }
707
708 void igb_down(struct igb_adapter *adapter)
709 {
710 struct e1000_hw *hw = &adapter->hw;
711 struct net_device *netdev = adapter->netdev;
712 u32 tctl, rctl;
713 int i;
714
715 /* signal that we're down so the interrupt handler does not
716 * reschedule our watchdog timer */
717 set_bit(__IGB_DOWN, &adapter->state);
718
719 /* disable receives in the hardware */
720 rctl = rd32(E1000_RCTL);
721 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
722 /* flush and sleep below */
723
724 netif_stop_queue(netdev);
725
726 /* disable transmits in the hardware */
727 tctl = rd32(E1000_TCTL);
728 tctl &= ~E1000_TCTL_EN;
729 wr32(E1000_TCTL, tctl);
730 /* flush both disables and wait for them to finish */
731 wrfl();
732 msleep(10);
733
734 napi_disable(&adapter->napi);
735
736 if (adapter->msix_entries)
737 for (i = 0; i < adapter->num_rx_queues; i++)
738 napi_disable(&adapter->rx_ring[i].napi);
739 igb_irq_disable(adapter);
740
741 del_timer_sync(&adapter->watchdog_timer);
742 del_timer_sync(&adapter->phy_info_timer);
743
744 netdev->tx_queue_len = adapter->tx_queue_len;
745 netif_carrier_off(netdev);
746 adapter->link_speed = 0;
747 adapter->link_duplex = 0;
748
749 igb_reset(adapter);
750 igb_clean_all_tx_rings(adapter);
751 igb_clean_all_rx_rings(adapter);
752 }
753
754 void igb_reinit_locked(struct igb_adapter *adapter)
755 {
756 WARN_ON(in_interrupt());
757 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
758 msleep(1);
759 igb_down(adapter);
760 igb_up(adapter);
761 clear_bit(__IGB_RESETTING, &adapter->state);
762 }
763
764 void igb_reset(struct igb_adapter *adapter)
765 {
766 struct e1000_hw *hw = &adapter->hw;
767 struct e1000_fc_info *fc = &adapter->hw.fc;
768 u32 pba = 0, tx_space, min_tx_space, min_rx_space;
769 u16 hwm;
770
771 /* Repartition Pba for greater than 9k mtu
772 * To take effect CTRL.RST is required.
773 */
774 pba = E1000_PBA_34K;
775
776 if (adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) {
777 /* adjust PBA for jumbo frames */
778 wr32(E1000_PBA, pba);
779
780 /* To maintain wire speed transmits, the Tx FIFO should be
781 * large enough to accommodate two full transmit packets,
782 * rounded up to the next 1KB and expressed in KB. Likewise,
783 * the Rx FIFO should be large enough to accommodate at least
784 * one full receive packet and is similarly rounded up and
785 * expressed in KB. */
786 pba = rd32(E1000_PBA);
787 /* upper 16 bits has Tx packet buffer allocation size in KB */
788 tx_space = pba >> 16;
789 /* lower 16 bits has Rx packet buffer allocation size in KB */
790 pba &= 0xffff;
791 /* the tx fifo also stores 16 bytes of information about the tx
792 * but don't include ethernet FCS because hardware appends it */
793 min_tx_space = (adapter->max_frame_size +
794 sizeof(struct e1000_tx_desc) -
795 ETH_FCS_LEN) * 2;
796 min_tx_space = ALIGN(min_tx_space, 1024);
797 min_tx_space >>= 10;
798 /* software strips receive CRC, so leave room for it */
799 min_rx_space = adapter->max_frame_size;
800 min_rx_space = ALIGN(min_rx_space, 1024);
801 min_rx_space >>= 10;
802
803 /* If current Tx allocation is less than the min Tx FIFO size,
804 * and the min Tx FIFO size is less than the current Rx FIFO
805 * allocation, take space away from current Rx allocation */
806 if (tx_space < min_tx_space &&
807 ((min_tx_space - tx_space) < pba)) {
808 pba = pba - (min_tx_space - tx_space);
809
810 /* if short on rx space, rx wins and must trump tx
811 * adjustment */
812 if (pba < min_rx_space)
813 pba = min_rx_space;
814 }
815 }
816 wr32(E1000_PBA, pba);
817
818 /* flow control settings */
819 /* The high water mark must be low enough to fit one full frame
820 * (or the size used for early receive) above it in the Rx FIFO.
821 * Set it to the lower of:
822 * - 90% of the Rx FIFO size, or
823 * - the full Rx FIFO size minus one full frame */
824 hwm = min(((pba << 10) * 9 / 10),
825 ((pba << 10) - adapter->max_frame_size));
826
827 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
828 fc->low_water = fc->high_water - 8;
829 fc->pause_time = 0xFFFF;
830 fc->send_xon = 1;
831 fc->type = fc->original_type;
832
833 /* Allow time for pending master requests to run */
834 adapter->hw.mac.ops.reset_hw(&adapter->hw);
835 wr32(E1000_WUC, 0);
836
837 if (adapter->hw.mac.ops.init_hw(&adapter->hw))
838 dev_err(&adapter->pdev->dev, "Hardware Error\n");
839
840 igb_update_mng_vlan(adapter);
841
842 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
843 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);
844
845 igb_reset_adaptive(&adapter->hw);
846 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
847 igb_release_manageability(adapter);
848 }
849
850 /**
851 * igb_probe - Device Initialization Routine
852 * @pdev: PCI device information struct
853 * @ent: entry in igb_pci_tbl
854 *
855 * Returns 0 on success, negative on failure
856 *
857 * igb_probe initializes an adapter identified by a pci_dev structure.
858 * The OS initialization, configuring of the adapter private structure,
859 * and a hardware reset occur.
860 **/
861 static int __devinit igb_probe(struct pci_dev *pdev,
862 const struct pci_device_id *ent)
863 {
864 struct net_device *netdev;
865 struct igb_adapter *adapter;
866 struct e1000_hw *hw;
867 const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
868 unsigned long mmio_start, mmio_len;
869 static int cards_found;
870 int i, err, pci_using_dac;
871 u16 eeprom_data = 0;
872 u16 eeprom_apme_mask = IGB_EEPROM_APME;
873 u32 part_num;
874
875 err = pci_enable_device(pdev);
876 if (err)
877 return err;
878
879 pci_using_dac = 0;
880 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
881 if (!err) {
882 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
883 if (!err)
884 pci_using_dac = 1;
885 } else {
886 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
887 if (err) {
888 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
889 if (err) {
890 dev_err(&pdev->dev, "No usable DMA "
891 "configuration, aborting\n");
892 goto err_dma;
893 }
894 }
895 }
896
897 err = pci_request_regions(pdev, igb_driver_name);
898 if (err)
899 goto err_pci_reg;
900
901 pci_set_master(pdev);
902
903 err = -ENOMEM;
904 netdev = alloc_etherdev(sizeof(struct igb_adapter));
905 if (!netdev)
906 goto err_alloc_etherdev;
907
908 SET_NETDEV_DEV(netdev, &pdev->dev);
909
910 pci_set_drvdata(pdev, netdev);
911 adapter = netdev_priv(netdev);
912 adapter->netdev = netdev;
913 adapter->pdev = pdev;
914 hw = &adapter->hw;
915 hw->back = adapter;
916 adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;
917
918 mmio_start = pci_resource_start(pdev, 0);
919 mmio_len = pci_resource_len(pdev, 0);
920
921 err = -EIO;
922 adapter->hw.hw_addr = ioremap(mmio_start, mmio_len);
923 if (!adapter->hw.hw_addr)
924 goto err_ioremap;
925
926 netdev->open = &igb_open;
927 netdev->stop = &igb_close;
928 netdev->get_stats = &igb_get_stats;
929 netdev->set_multicast_list = &igb_set_multi;
930 netdev->set_mac_address = &igb_set_mac;
931 netdev->change_mtu = &igb_change_mtu;
932 netdev->do_ioctl = &igb_ioctl;
933 igb_set_ethtool_ops(netdev);
934 netdev->tx_timeout = &igb_tx_timeout;
935 netdev->watchdog_timeo = 5 * HZ;
936 netif_napi_add(netdev, &adapter->napi, igb_clean, 64);
937 netdev->vlan_rx_register = igb_vlan_rx_register;
938 netdev->vlan_rx_add_vid = igb_vlan_rx_add_vid;
939 netdev->vlan_rx_kill_vid = igb_vlan_rx_kill_vid;
940 #ifdef CONFIG_NET_POLL_CONTROLLER
941 netdev->poll_controller = igb_netpoll;
942 #endif
943 netdev->hard_start_xmit = &igb_xmit_frame_adv;
944
945 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
946
947 netdev->mem_start = mmio_start;
948 netdev->mem_end = mmio_start + mmio_len;
949
950 adapter->bd_number = cards_found;
951
952 /* PCI config space info */
953 hw->vendor_id = pdev->vendor;
954 hw->device_id = pdev->device;
955 hw->revision_id = pdev->revision;
956 hw->subsystem_vendor_id = pdev->subsystem_vendor;
957 hw->subsystem_device_id = pdev->subsystem_device;
958
959 /* setup the private structure */
960 hw->back = adapter;
961 /* Copy the default MAC, PHY and NVM function pointers */
962 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
963 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
964 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
965 /* Initialize skew-specific constants */
966 err = ei->get_invariants(hw);
967 if (err)
968 goto err_hw_init;
969
970 err = igb_sw_init(adapter);
971 if (err)
972 goto err_sw_init;
973
974 igb_get_bus_info_pcie(hw);
975
976 hw->phy.autoneg_wait_to_complete = false;
977 hw->mac.adaptive_ifs = true;
978
979 /* Copper options */
980 if (hw->phy.media_type == e1000_media_type_copper) {
981 hw->phy.mdix = AUTO_ALL_MODES;
982 hw->phy.disable_polarity_correction = false;
983 hw->phy.ms_type = e1000_ms_hw_default;
984 }
985
986 if (igb_check_reset_block(hw))
987 dev_info(&pdev->dev,
988 "PHY reset is blocked due to SOL/IDER session.\n");
989
990 netdev->features = NETIF_F_SG |
991 NETIF_F_HW_CSUM |
992 NETIF_F_HW_VLAN_TX |
993 NETIF_F_HW_VLAN_RX |
994 NETIF_F_HW_VLAN_FILTER;
995
996 netdev->features |= NETIF_F_TSO;
997
998 netdev->features |= NETIF_F_TSO6;
999 if (pci_using_dac)
1000 netdev->features |= NETIF_F_HIGHDMA;
1001
1002 netdev->features |= NETIF_F_LLTX;
1003 adapter->en_mng_pt = igb_enable_mng_pass_thru(&adapter->hw);
1004
1005 /* before reading the NVM, reset the controller to put the device in a
1006 * known good starting state */
1007 hw->mac.ops.reset_hw(hw);
1008
1009 /* make sure the NVM is good */
1010 if (igb_validate_nvm_checksum(hw) < 0) {
1011 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
1012 err = -EIO;
1013 goto err_eeprom;
1014 }
1015
1016 /* copy the MAC address out of the NVM */
1017 if (hw->mac.ops.read_mac_addr(hw))
1018 dev_err(&pdev->dev, "NVM Read Error\n");
1019
1020 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
1021 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);
1022
1023 if (!is_valid_ether_addr(netdev->perm_addr)) {
1024 dev_err(&pdev->dev, "Invalid MAC Address\n");
1025 err = -EIO;
1026 goto err_eeprom;
1027 }
1028
1029 init_timer(&adapter->watchdog_timer);
1030 adapter->watchdog_timer.function = &igb_watchdog;
1031 adapter->watchdog_timer.data = (unsigned long) adapter;
1032
1033 init_timer(&adapter->phy_info_timer);
1034 adapter->phy_info_timer.function = &igb_update_phy_info;
1035 adapter->phy_info_timer.data = (unsigned long) adapter;
1036
1037 INIT_WORK(&adapter->reset_task, igb_reset_task);
1038 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);
1039
1040 /* Initialize link & ring properties that are user-changeable */
1041 adapter->tx_ring->count = 256;
1042 for (i = 0; i < adapter->num_tx_queues; i++)
1043 adapter->tx_ring[i].count = adapter->tx_ring->count;
1044 adapter->rx_ring->count = 256;
1045 for (i = 0; i < adapter->num_rx_queues; i++)
1046 adapter->rx_ring[i].count = adapter->rx_ring->count;
1047
1048 adapter->fc_autoneg = true;
1049 hw->mac.autoneg = true;
1050 hw->phy.autoneg_advertised = 0x2f;
1051
1052 hw->fc.original_type = e1000_fc_default;
1053 hw->fc.type = e1000_fc_default;
1054
1055 adapter->itr_setting = 3;
1056 adapter->itr = IGB_START_ITR;
1057
1058 igb_validate_mdi_setting(hw);
1059
1060 adapter->rx_csum = 1;
1061
1062 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
1063 * enable the ACPI Magic Packet filter
1064 */
1065
1066 if (hw->bus.func == 0 ||
1067 hw->device_id == E1000_DEV_ID_82575EB_COPPER)
1068 hw->nvm.ops.read_nvm(hw, NVM_INIT_CONTROL3_PORT_A, 1,
1069 &eeprom_data);
1070
1071 if (eeprom_data & eeprom_apme_mask)
1072 adapter->eeprom_wol |= E1000_WUFC_MAG;
1073
1074 /* now that we have the eeprom settings, apply the special cases where
1075 * the eeprom may be wrong or the board simply won't support wake on
1076 * lan on a particular port */
1077 switch (pdev->device) {
1078 case E1000_DEV_ID_82575GB_QUAD_COPPER:
1079 adapter->eeprom_wol = 0;
1080 break;
1081 case E1000_DEV_ID_82575EB_FIBER_SERDES:
1082 /* Wake events only supported on port A for dual fiber
1083 * regardless of eeprom setting */
1084 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
1085 adapter->eeprom_wol = 0;
1086 break;
1087 }
1088
1089 /* initialize the wol settings based on the eeprom settings */
1090 adapter->wol = adapter->eeprom_wol;
1091
1092 /* reset the hardware with the new settings */
1093 igb_reset(adapter);
1094
1095 /* let the f/w know that the h/w is now under the control of the
1096 * driver. */
1097 igb_get_hw_control(adapter);
1098
1099 /* tell the stack to leave us alone until igb_open() is called */
1100 netif_carrier_off(netdev);
1101 netif_stop_queue(netdev);
1102
1103 strcpy(netdev->name, "eth%d");
1104 err = register_netdev(netdev);
1105 if (err)
1106 goto err_register;
1107
1108 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
1109 /* print bus type/speed/width info */
1110 dev_info(&pdev->dev,
1111 "%s: (PCIe:%s:%s) %02x:%02x:%02x:%02x:%02x:%02x\n",
1112 netdev->name,
1113 ((hw->bus.speed == e1000_bus_speed_2500)
1114 ? "2.5Gb/s" : "unknown"),
1115 ((hw->bus.width == e1000_bus_width_pcie_x4)
1116 ? "Width x4" : (hw->bus.width == e1000_bus_width_pcie_x1)
1117 ? "Width x1" : "unknown"),
1118 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
1119 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
1120
1121 igb_read_part_num(hw, &part_num);
1122 dev_info(&pdev->dev, "%s: PBA No: %06x-%03x\n", netdev->name,
1123 (part_num >> 8), (part_num & 0xff));
1124
1125 dev_info(&pdev->dev,
1126 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
1127 adapter->msix_entries ? "MSI-X" :
1128 adapter->msi_enabled ? "MSI" : "legacy",
1129 adapter->num_rx_queues, adapter->num_tx_queues);
1130
1131 cards_found++;
1132 return 0;
1133
1134 err_register:
1135 igb_release_hw_control(adapter);
1136 err_eeprom:
1137 if (!igb_check_reset_block(hw))
1138 hw->phy.ops.reset_phy(hw);
1139
1140 if (hw->flash_address)
1141 iounmap(hw->flash_address);
1142
1143 igb_remove_device(hw);
1144 kfree(adapter->tx_ring);
1145 kfree(adapter->rx_ring);
1146 err_sw_init:
1147 err_hw_init:
1148 iounmap(hw->hw_addr);
1149 err_ioremap:
1150 free_netdev(netdev);
1151 err_alloc_etherdev:
1152 pci_release_regions(pdev);
1153 err_pci_reg:
1154 err_dma:
1155 pci_disable_device(pdev);
1156 return err;
1157 }
1158
1159 /**
1160 * igb_remove - Device Removal Routine
1161 * @pdev: PCI device information struct
1162 *
1163 * igb_remove is called by the PCI subsystem to alert the driver
1164 * that it should release a PCI device. The could be caused by a
1165 * Hot-Plug event, or because the driver is going to be removed from
1166 * memory.
1167 **/
1168 static void __devexit igb_remove(struct pci_dev *pdev)
1169 {
1170 struct net_device *netdev = pci_get_drvdata(pdev);
1171 struct igb_adapter *adapter = netdev_priv(netdev);
1172
1173 /* flush_scheduled work may reschedule our watchdog task, so
1174 * explicitly disable watchdog tasks from being rescheduled */
1175 set_bit(__IGB_DOWN, &adapter->state);
1176 del_timer_sync(&adapter->watchdog_timer);
1177 del_timer_sync(&adapter->phy_info_timer);
1178
1179 flush_scheduled_work();
1180
1181
1182 igb_release_manageability(adapter);
1183
1184 /* Release control of h/w to f/w. If f/w is AMT enabled, this
1185 * would have already happened in close and is redundant. */
1186 igb_release_hw_control(adapter);
1187
1188 unregister_netdev(netdev);
1189
1190 if (!igb_check_reset_block(&adapter->hw))
1191 adapter->hw.phy.ops.reset_phy(&adapter->hw);
1192
1193 igb_remove_device(&adapter->hw);
1194 igb_reset_interrupt_capability(adapter);
1195
1196 kfree(adapter->tx_ring);
1197 kfree(adapter->rx_ring);
1198
1199 iounmap(adapter->hw.hw_addr);
1200 if (adapter->hw.flash_address)
1201 iounmap(adapter->hw.flash_address);
1202 pci_release_regions(pdev);
1203
1204 free_netdev(netdev);
1205
1206 pci_disable_device(pdev);
1207 }
1208
1209 /**
1210 * igb_sw_init - Initialize general software structures (struct igb_adapter)
1211 * @adapter: board private structure to initialize
1212 *
1213 * igb_sw_init initializes the Adapter private data structure.
1214 * Fields are initialized based on PCI device information and
1215 * OS network device settings (MTU size).
1216 **/
1217 static int __devinit igb_sw_init(struct igb_adapter *adapter)
1218 {
1219 struct e1000_hw *hw = &adapter->hw;
1220 struct net_device *netdev = adapter->netdev;
1221 struct pci_dev *pdev = adapter->pdev;
1222
1223 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
1224
1225 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1226 adapter->rx_ps_hdr_size = 0; /* disable packet split */
1227 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1228 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
1229
1230 /* Number of supported queues. */
1231 /* Having more queues than CPUs doesn't make sense. */
1232 adapter->num_tx_queues = 1;
1233 adapter->num_rx_queues = min(IGB_MAX_RX_QUEUES, num_online_cpus());
1234
1235 igb_set_interrupt_capability(adapter);
1236
1237 if (igb_alloc_queues(adapter)) {
1238 dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
1239 return -ENOMEM;
1240 }
1241
1242 /* Explicitly disable IRQ since the NIC can be in any state. */
1243 igb_irq_disable(adapter);
1244
1245 set_bit(__IGB_DOWN, &adapter->state);
1246 return 0;
1247 }
1248
1249 /**
1250 * igb_open - Called when a network interface is made active
1251 * @netdev: network interface device structure
1252 *
1253 * Returns 0 on success, negative value on failure
1254 *
1255 * The open entry point is called when a network interface is made
1256 * active by the system (IFF_UP). At this point all resources needed
1257 * for transmit and receive operations are allocated, the interrupt
1258 * handler is registered with the OS, the watchdog timer is started,
1259 * and the stack is notified that the interface is ready.
1260 **/
1261 static int igb_open(struct net_device *netdev)
1262 {
1263 struct igb_adapter *adapter = netdev_priv(netdev);
1264 struct e1000_hw *hw = &adapter->hw;
1265 int err;
1266 int i;
1267
1268 /* disallow open during test */
1269 if (test_bit(__IGB_TESTING, &adapter->state))
1270 return -EBUSY;
1271
1272 /* allocate transmit descriptors */
1273 err = igb_setup_all_tx_resources(adapter);
1274 if (err)
1275 goto err_setup_tx;
1276
1277 /* allocate receive descriptors */
1278 err = igb_setup_all_rx_resources(adapter);
1279 if (err)
1280 goto err_setup_rx;
1281
1282 /* e1000_power_up_phy(adapter); */
1283
1284 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
1285 if ((adapter->hw.mng_cookie.status &
1286 E1000_MNG_DHCP_COOKIE_STATUS_VLAN))
1287 igb_update_mng_vlan(adapter);
1288
1289 /* before we allocate an interrupt, we must be ready to handle it.
1290 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
1291 * as soon as we call pci_request_irq, so we have to setup our
1292 * clean_rx handler before we do so. */
1293 igb_configure(adapter);
1294
1295 err = igb_request_irq(adapter);
1296 if (err)
1297 goto err_req_irq;
1298
1299 /* From here on the code is the same as igb_up() */
1300 clear_bit(__IGB_DOWN, &adapter->state);
1301
1302 napi_enable(&adapter->napi);
1303 if (adapter->msix_entries)
1304 for (i = 0; i < adapter->num_rx_queues; i++)
1305 napi_enable(&adapter->rx_ring[i].napi);
1306
1307 igb_irq_enable(adapter);
1308
1309 /* Clear any pending interrupts. */
1310 rd32(E1000_ICR);
1311 /* Fire a link status change interrupt to start the watchdog. */
1312 wr32(E1000_ICS, E1000_ICS_LSC);
1313
1314 return 0;
1315
1316 err_req_irq:
1317 igb_release_hw_control(adapter);
1318 /* e1000_power_down_phy(adapter); */
1319 igb_free_all_rx_resources(adapter);
1320 err_setup_rx:
1321 igb_free_all_tx_resources(adapter);
1322 err_setup_tx:
1323 igb_reset(adapter);
1324
1325 return err;
1326 }
1327
1328 /**
1329 * igb_close - Disables a network interface
1330 * @netdev: network interface device structure
1331 *
1332 * Returns 0, this is not allowed to fail
1333 *
1334 * The close entry point is called when an interface is de-activated
1335 * by the OS. The hardware is still under the driver's control, but
1336 * needs to be disabled. A global MAC reset is issued to stop the
1337 * hardware, and all transmit and receive resources are freed.
1338 **/
1339 static int igb_close(struct net_device *netdev)
1340 {
1341 struct igb_adapter *adapter = netdev_priv(netdev);
1342
1343 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
1344 igb_down(adapter);
1345
1346 igb_free_irq(adapter);
1347
1348 igb_free_all_tx_resources(adapter);
1349 igb_free_all_rx_resources(adapter);
1350
1351 /* kill manageability vlan ID if supported, but not if a vlan with
1352 * the same ID is registered on the host OS (let 8021q kill it) */
1353 if ((adapter->hw.mng_cookie.status &
1354 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
1355 !(adapter->vlgrp &&
1356 vlan_group_get_device(adapter->vlgrp, adapter->mng_vlan_id)))
1357 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
1358
1359 return 0;
1360 }
1361
1362 /**
1363 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
1364 * @adapter: board private structure
1365 * @tx_ring: tx descriptor ring (for a specific queue) to setup
1366 *
1367 * Return 0 on success, negative on failure
1368 **/
1369
1370 int igb_setup_tx_resources(struct igb_adapter *adapter,
1371 struct igb_ring *tx_ring)
1372 {
1373 struct pci_dev *pdev = adapter->pdev;
1374 int size;
1375
1376 size = sizeof(struct igb_buffer) * tx_ring->count;
1377 tx_ring->buffer_info = vmalloc(size);
1378 if (!tx_ring->buffer_info)
1379 goto err;
1380 memset(tx_ring->buffer_info, 0, size);
1381
1382 /* round up to nearest 4K */
1383 tx_ring->size = tx_ring->count * sizeof(struct e1000_tx_desc)
1384 + sizeof(u32);
1385 tx_ring->size = ALIGN(tx_ring->size, 4096);
1386
1387 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1388 &tx_ring->dma);
1389
1390 if (!tx_ring->desc)
1391 goto err;
1392
1393 tx_ring->adapter = adapter;
1394 tx_ring->next_to_use = 0;
1395 tx_ring->next_to_clean = 0;
1396 spin_lock_init(&tx_ring->tx_clean_lock);
1397 spin_lock_init(&tx_ring->tx_lock);
1398 return 0;
1399
1400 err:
1401 vfree(tx_ring->buffer_info);
1402 dev_err(&adapter->pdev->dev,
1403 "Unable to allocate memory for the transmit descriptor ring\n");
1404 return -ENOMEM;
1405 }
1406
1407 /**
1408 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
1409 * (Descriptors) for all queues
1410 * @adapter: board private structure
1411 *
1412 * Return 0 on success, negative on failure
1413 **/
1414 static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
1415 {
1416 int i, err = 0;
1417
1418 for (i = 0; i < adapter->num_tx_queues; i++) {
1419 err = igb_setup_tx_resources(adapter, &adapter->tx_ring[i]);
1420 if (err) {
1421 dev_err(&adapter->pdev->dev,
1422 "Allocation for Tx Queue %u failed\n", i);
1423 for (i--; i >= 0; i--)
1424 igb_free_tx_resources(adapter,
1425 &adapter->tx_ring[i]);
1426 break;
1427 }
1428 }
1429
1430 return err;
1431 }
1432
1433 /**
1434 * igb_configure_tx - Configure transmit Unit after Reset
1435 * @adapter: board private structure
1436 *
1437 * Configure the Tx unit of the MAC after a reset.
1438 **/
1439 static void igb_configure_tx(struct igb_adapter *adapter)
1440 {
1441 u64 tdba, tdwba;
1442 struct e1000_hw *hw = &adapter->hw;
1443 u32 tctl;
1444 u32 txdctl, txctrl;
1445 int i;
1446
1447 for (i = 0; i < adapter->num_tx_queues; i++) {
1448 struct igb_ring *ring = &(adapter->tx_ring[i]);
1449
1450 wr32(E1000_TDLEN(i),
1451 ring->count * sizeof(struct e1000_tx_desc));
1452 tdba = ring->dma;
1453 wr32(E1000_TDBAL(i),
1454 tdba & 0x00000000ffffffffULL);
1455 wr32(E1000_TDBAH(i), tdba >> 32);
1456
1457 tdwba = ring->dma + ring->count * sizeof(struct e1000_tx_desc);
1458 tdwba |= 1; /* enable head wb */
1459 wr32(E1000_TDWBAL(i),
1460 tdwba & 0x00000000ffffffffULL);
1461 wr32(E1000_TDWBAH(i), tdwba >> 32);
1462
1463 ring->head = E1000_TDH(i);
1464 ring->tail = E1000_TDT(i);
1465 writel(0, hw->hw_addr + ring->tail);
1466 writel(0, hw->hw_addr + ring->head);
1467 txdctl = rd32(E1000_TXDCTL(i));
1468 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1469 wr32(E1000_TXDCTL(i), txdctl);
1470
1471 /* Turn off Relaxed Ordering on head write-backs. The
1472 * writebacks MUST be delivered in order or it will
1473 * completely screw up our bookeeping.
1474 */
1475 txctrl = rd32(E1000_DCA_TXCTRL(i));
1476 txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1477 wr32(E1000_DCA_TXCTRL(i), txctrl);
1478 }
1479
1480
1481
1482 /* Use the default values for the Tx Inter Packet Gap (IPG) timer */
1483
1484 /* Program the Transmit Control Register */
1485
1486 tctl = rd32(E1000_TCTL);
1487 tctl &= ~E1000_TCTL_CT;
1488 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
1489 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
1490
1491 igb_config_collision_dist(hw);
1492
1493 /* Setup Transmit Descriptor Settings for eop descriptor */
1494 adapter->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_RS;
1495
1496 /* Enable transmits */
1497 tctl |= E1000_TCTL_EN;
1498
1499 wr32(E1000_TCTL, tctl);
1500 }
1501
1502 /**
1503 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
1504 * @adapter: board private structure
1505 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1506 *
1507 * Returns 0 on success, negative on failure
1508 **/
1509
1510 int igb_setup_rx_resources(struct igb_adapter *adapter,
1511 struct igb_ring *rx_ring)
1512 {
1513 struct pci_dev *pdev = adapter->pdev;
1514 int size, desc_len;
1515
1516 size = sizeof(struct igb_buffer) * rx_ring->count;
1517 rx_ring->buffer_info = vmalloc(size);
1518 if (!rx_ring->buffer_info)
1519 goto err;
1520 memset(rx_ring->buffer_info, 0, size);
1521
1522 desc_len = sizeof(union e1000_adv_rx_desc);
1523
1524 /* Round up to nearest 4K */
1525 rx_ring->size = rx_ring->count * desc_len;
1526 rx_ring->size = ALIGN(rx_ring->size, 4096);
1527
1528 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1529 &rx_ring->dma);
1530
1531 if (!rx_ring->desc)
1532 goto err;
1533
1534 rx_ring->next_to_clean = 0;
1535 rx_ring->next_to_use = 0;
1536 rx_ring->pending_skb = NULL;
1537
1538 rx_ring->adapter = adapter;
1539 /* FIXME: do we want to setup ring->napi->poll here? */
1540 rx_ring->napi.poll = adapter->napi.poll;
1541
1542 return 0;
1543
1544 err:
1545 vfree(rx_ring->buffer_info);
1546 dev_err(&adapter->pdev->dev, "Unable to allocate memory for "
1547 "the receive descriptor ring\n");
1548 return -ENOMEM;
1549 }
1550
1551 /**
1552 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
1553 * (Descriptors) for all queues
1554 * @adapter: board private structure
1555 *
1556 * Return 0 on success, negative on failure
1557 **/
1558 static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
1559 {
1560 int i, err = 0;
1561
1562 for (i = 0; i < adapter->num_rx_queues; i++) {
1563 err = igb_setup_rx_resources(adapter, &adapter->rx_ring[i]);
1564 if (err) {
1565 dev_err(&adapter->pdev->dev,
1566 "Allocation for Rx Queue %u failed\n", i);
1567 for (i--; i >= 0; i--)
1568 igb_free_rx_resources(adapter,
1569 &adapter->rx_ring[i]);
1570 break;
1571 }
1572 }
1573
1574 return err;
1575 }
1576
1577 /**
1578 * igb_setup_rctl - configure the receive control registers
1579 * @adapter: Board private structure
1580 **/
1581 static void igb_setup_rctl(struct igb_adapter *adapter)
1582 {
1583 struct e1000_hw *hw = &adapter->hw;
1584 u32 rctl;
1585 u32 srrctl = 0;
1586 int i;
1587
1588 rctl = rd32(E1000_RCTL);
1589
1590 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
1591
1592 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM |
1593 E1000_RCTL_LBM_NO | E1000_RCTL_RDMTS_HALF |
1594 (adapter->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
1595
1596 /* disable the stripping of CRC because it breaks
1597 * BMC firmware connected over SMBUS
1598 rctl |= E1000_RCTL_SECRC;
1599 */
1600
1601 rctl &= ~E1000_RCTL_SBP;
1602
1603 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1604 rctl &= ~E1000_RCTL_LPE;
1605 else
1606 rctl |= E1000_RCTL_LPE;
1607 if (adapter->rx_buffer_len <= IGB_RXBUFFER_2048) {
1608 /* Setup buffer sizes */
1609 rctl &= ~E1000_RCTL_SZ_4096;
1610 rctl |= E1000_RCTL_BSEX;
1611 switch (adapter->rx_buffer_len) {
1612 case IGB_RXBUFFER_256:
1613 rctl |= E1000_RCTL_SZ_256;
1614 rctl &= ~E1000_RCTL_BSEX;
1615 break;
1616 case IGB_RXBUFFER_512:
1617 rctl |= E1000_RCTL_SZ_512;
1618 rctl &= ~E1000_RCTL_BSEX;
1619 break;
1620 case IGB_RXBUFFER_1024:
1621 rctl |= E1000_RCTL_SZ_1024;
1622 rctl &= ~E1000_RCTL_BSEX;
1623 break;
1624 case IGB_RXBUFFER_2048:
1625 default:
1626 rctl |= E1000_RCTL_SZ_2048;
1627 rctl &= ~E1000_RCTL_BSEX;
1628 break;
1629 case IGB_RXBUFFER_4096:
1630 rctl |= E1000_RCTL_SZ_4096;
1631 break;
1632 case IGB_RXBUFFER_8192:
1633 rctl |= E1000_RCTL_SZ_8192;
1634 break;
1635 case IGB_RXBUFFER_16384:
1636 rctl |= E1000_RCTL_SZ_16384;
1637 break;
1638 }
1639 } else {
1640 rctl &= ~E1000_RCTL_BSEX;
1641 srrctl = adapter->rx_buffer_len >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1642 }
1643
1644 /* 82575 and greater support packet-split where the protocol
1645 * header is placed in skb->data and the packet data is
1646 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
1647 * In the case of a non-split, skb->data is linearly filled,
1648 * followed by the page buffers. Therefore, skb->data is
1649 * sized to hold the largest protocol header.
1650 */
1651 /* allocations using alloc_page take too long for regular MTU
1652 * so only enable packet split for jumbo frames */
1653 if (rctl & E1000_RCTL_LPE) {
1654 adapter->rx_ps_hdr_size = IGB_RXBUFFER_128;
1655 srrctl = adapter->rx_ps_hdr_size <<
1656 E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
1657 /* buffer size is ALWAYS one page */
1658 srrctl |= PAGE_SIZE >> E1000_SRRCTL_BSIZEPKT_SHIFT;
1659 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1660 } else {
1661 adapter->rx_ps_hdr_size = 0;
1662 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
1663 }
1664
1665 for (i = 0; i < adapter->num_rx_queues; i++)
1666 wr32(E1000_SRRCTL(i), srrctl);
1667
1668 wr32(E1000_RCTL, rctl);
1669 }
1670
1671 /**
1672 * igb_configure_rx - Configure receive Unit after Reset
1673 * @adapter: board private structure
1674 *
1675 * Configure the Rx unit of the MAC after a reset.
1676 **/
1677 static void igb_configure_rx(struct igb_adapter *adapter)
1678 {
1679 u64 rdba;
1680 struct e1000_hw *hw = &adapter->hw;
1681 u32 rctl, rxcsum;
1682 u32 rxdctl;
1683 int i;
1684
1685 /* disable receives while setting up the descriptors */
1686 rctl = rd32(E1000_RCTL);
1687 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
1688 wrfl();
1689 mdelay(10);
1690
1691 if (adapter->itr_setting > 3)
1692 wr32(E1000_ITR,
1693 1000000000 / (adapter->itr * 256));
1694
1695 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1696 * the Base and Length of the Rx Descriptor Ring */
1697 for (i = 0; i < adapter->num_rx_queues; i++) {
1698 struct igb_ring *ring = &(adapter->rx_ring[i]);
1699 rdba = ring->dma;
1700 wr32(E1000_RDBAL(i),
1701 rdba & 0x00000000ffffffffULL);
1702 wr32(E1000_RDBAH(i), rdba >> 32);
1703 wr32(E1000_RDLEN(i),
1704 ring->count * sizeof(union e1000_adv_rx_desc));
1705
1706 ring->head = E1000_RDH(i);
1707 ring->tail = E1000_RDT(i);
1708 writel(0, hw->hw_addr + ring->tail);
1709 writel(0, hw->hw_addr + ring->head);
1710
1711 rxdctl = rd32(E1000_RXDCTL(i));
1712 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
1713 rxdctl &= 0xFFF00000;
1714 rxdctl |= IGB_RX_PTHRESH;
1715 rxdctl |= IGB_RX_HTHRESH << 8;
1716 rxdctl |= IGB_RX_WTHRESH << 16;
1717 wr32(E1000_RXDCTL(i), rxdctl);
1718 }
1719
1720 if (adapter->num_rx_queues > 1) {
1721 u32 random[10];
1722 u32 mrqc;
1723 u32 j, shift;
1724 union e1000_reta {
1725 u32 dword;
1726 u8 bytes[4];
1727 } reta;
1728
1729 get_random_bytes(&random[0], 40);
1730
1731 shift = 6;
1732 for (j = 0; j < (32 * 4); j++) {
1733 reta.bytes[j & 3] =
1734 (j % adapter->num_rx_queues) << shift;
1735 if ((j & 3) == 3)
1736 writel(reta.dword,
1737 hw->hw_addr + E1000_RETA(0) + (j & ~3));
1738 }
1739 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
1740
1741 /* Fill out hash function seeds */
1742 for (j = 0; j < 10; j++)
1743 array_wr32(E1000_RSSRK(0), j, random[j]);
1744
1745 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
1746 E1000_MRQC_RSS_FIELD_IPV4_TCP);
1747 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
1748 E1000_MRQC_RSS_FIELD_IPV6_TCP);
1749 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4_UDP |
1750 E1000_MRQC_RSS_FIELD_IPV6_UDP);
1751 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
1752 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
1753
1754
1755 wr32(E1000_MRQC, mrqc);
1756
1757 /* Multiqueue and raw packet checksumming are mutually
1758 * exclusive. Note that this not the same as TCP/IP
1759 * checksumming, which works fine. */
1760 rxcsum = rd32(E1000_RXCSUM);
1761 rxcsum |= E1000_RXCSUM_PCSD;
1762 wr32(E1000_RXCSUM, rxcsum);
1763 } else {
1764 /* Enable Receive Checksum Offload for TCP and UDP */
1765 rxcsum = rd32(E1000_RXCSUM);
1766 if (adapter->rx_csum) {
1767 rxcsum |= E1000_RXCSUM_TUOFL;
1768
1769 /* Enable IPv4 payload checksum for UDP fragments
1770 * Must be used in conjunction with packet-split. */
1771 if (adapter->rx_ps_hdr_size)
1772 rxcsum |= E1000_RXCSUM_IPPCSE;
1773 } else {
1774 rxcsum &= ~E1000_RXCSUM_TUOFL;
1775 /* don't need to clear IPPCSE as it defaults to 0 */
1776 }
1777 wr32(E1000_RXCSUM, rxcsum);
1778 }
1779
1780 if (adapter->vlgrp)
1781 wr32(E1000_RLPML,
1782 adapter->max_frame_size + VLAN_TAG_SIZE);
1783 else
1784 wr32(E1000_RLPML, adapter->max_frame_size);
1785
1786 /* Enable Receives */
1787 wr32(E1000_RCTL, rctl);
1788 }
1789
1790 /**
1791 * igb_free_tx_resources - Free Tx Resources per Queue
1792 * @adapter: board private structure
1793 * @tx_ring: Tx descriptor ring for a specific queue
1794 *
1795 * Free all transmit software resources
1796 **/
1797 static void igb_free_tx_resources(struct igb_adapter *adapter,
1798 struct igb_ring *tx_ring)
1799 {
1800 struct pci_dev *pdev = adapter->pdev;
1801
1802 igb_clean_tx_ring(adapter, tx_ring);
1803
1804 vfree(tx_ring->buffer_info);
1805 tx_ring->buffer_info = NULL;
1806
1807 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1808
1809 tx_ring->desc = NULL;
1810 }
1811
1812 /**
1813 * igb_free_all_tx_resources - Free Tx Resources for All Queues
1814 * @adapter: board private structure
1815 *
1816 * Free all transmit software resources
1817 **/
1818 static void igb_free_all_tx_resources(struct igb_adapter *adapter)
1819 {
1820 int i;
1821
1822 for (i = 0; i < adapter->num_tx_queues; i++)
1823 igb_free_tx_resources(adapter, &adapter->tx_ring[i]);
1824 }
1825
1826 static void igb_unmap_and_free_tx_resource(struct igb_adapter *adapter,
1827 struct igb_buffer *buffer_info)
1828 {
1829 if (buffer_info->dma) {
1830 pci_unmap_page(adapter->pdev,
1831 buffer_info->dma,
1832 buffer_info->length,
1833 PCI_DMA_TODEVICE);
1834 buffer_info->dma = 0;
1835 }
1836 if (buffer_info->skb) {
1837 dev_kfree_skb_any(buffer_info->skb);
1838 buffer_info->skb = NULL;
1839 }
1840 buffer_info->time_stamp = 0;
1841 /* buffer_info must be completely set up in the transmit path */
1842 }
1843
1844 /**
1845 * igb_clean_tx_ring - Free Tx Buffers
1846 * @adapter: board private structure
1847 * @tx_ring: ring to be cleaned
1848 **/
1849 static void igb_clean_tx_ring(struct igb_adapter *adapter,
1850 struct igb_ring *tx_ring)
1851 {
1852 struct igb_buffer *buffer_info;
1853 unsigned long size;
1854 unsigned int i;
1855
1856 if (!tx_ring->buffer_info)
1857 return;
1858 /* Free all the Tx ring sk_buffs */
1859
1860 for (i = 0; i < tx_ring->count; i++) {
1861 buffer_info = &tx_ring->buffer_info[i];
1862 igb_unmap_and_free_tx_resource(adapter, buffer_info);
1863 }
1864
1865 size = sizeof(struct igb_buffer) * tx_ring->count;
1866 memset(tx_ring->buffer_info, 0, size);
1867
1868 /* Zero out the descriptor ring */
1869
1870 memset(tx_ring->desc, 0, tx_ring->size);
1871
1872 tx_ring->next_to_use = 0;
1873 tx_ring->next_to_clean = 0;
1874
1875 writel(0, adapter->hw.hw_addr + tx_ring->head);
1876 writel(0, adapter->hw.hw_addr + tx_ring->tail);
1877 }
1878
1879 /**
1880 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
1881 * @adapter: board private structure
1882 **/
1883 static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
1884 {
1885 int i;
1886
1887 for (i = 0; i < adapter->num_tx_queues; i++)
1888 igb_clean_tx_ring(adapter, &adapter->tx_ring[i]);
1889 }
1890
1891 /**
1892 * igb_free_rx_resources - Free Rx Resources
1893 * @adapter: board private structure
1894 * @rx_ring: ring to clean the resources from
1895 *
1896 * Free all receive software resources
1897 **/
1898 static void igb_free_rx_resources(struct igb_adapter *adapter,
1899 struct igb_ring *rx_ring)
1900 {
1901 struct pci_dev *pdev = adapter->pdev;
1902
1903 igb_clean_rx_ring(adapter, rx_ring);
1904
1905 vfree(rx_ring->buffer_info);
1906 rx_ring->buffer_info = NULL;
1907
1908 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1909
1910 rx_ring->desc = NULL;
1911 }
1912
1913 /**
1914 * igb_free_all_rx_resources - Free Rx Resources for All Queues
1915 * @adapter: board private structure
1916 *
1917 * Free all receive software resources
1918 **/
1919 static void igb_free_all_rx_resources(struct igb_adapter *adapter)
1920 {
1921 int i;
1922
1923 for (i = 0; i < adapter->num_rx_queues; i++)
1924 igb_free_rx_resources(adapter, &adapter->rx_ring[i]);
1925 }
1926
1927 /**
1928 * igb_clean_rx_ring - Free Rx Buffers per Queue
1929 * @adapter: board private structure
1930 * @rx_ring: ring to free buffers from
1931 **/
1932 static void igb_clean_rx_ring(struct igb_adapter *adapter,
1933 struct igb_ring *rx_ring)
1934 {
1935 struct igb_buffer *buffer_info;
1936 struct pci_dev *pdev = adapter->pdev;
1937 unsigned long size;
1938 unsigned int i;
1939
1940 if (!rx_ring->buffer_info)
1941 return;
1942 /* Free all the Rx ring sk_buffs */
1943 for (i = 0; i < rx_ring->count; i++) {
1944 buffer_info = &rx_ring->buffer_info[i];
1945 if (buffer_info->dma) {
1946 if (adapter->rx_ps_hdr_size)
1947 pci_unmap_single(pdev, buffer_info->dma,
1948 adapter->rx_ps_hdr_size,
1949 PCI_DMA_FROMDEVICE);
1950 else
1951 pci_unmap_single(pdev, buffer_info->dma,
1952 adapter->rx_buffer_len,
1953 PCI_DMA_FROMDEVICE);
1954 buffer_info->dma = 0;
1955 }
1956
1957 if (buffer_info->skb) {
1958 dev_kfree_skb(buffer_info->skb);
1959 buffer_info->skb = NULL;
1960 }
1961 if (buffer_info->page) {
1962 pci_unmap_page(pdev, buffer_info->page_dma,
1963 PAGE_SIZE, PCI_DMA_FROMDEVICE);
1964 put_page(buffer_info->page);
1965 buffer_info->page = NULL;
1966 buffer_info->page_dma = 0;
1967 }
1968 }
1969
1970 /* there also may be some cached data from a chained receive */
1971 if (rx_ring->pending_skb) {
1972 dev_kfree_skb(rx_ring->pending_skb);
1973 rx_ring->pending_skb = NULL;
1974 }
1975
1976 size = sizeof(struct igb_buffer) * rx_ring->count;
1977 memset(rx_ring->buffer_info, 0, size);
1978
1979 /* Zero out the descriptor ring */
1980 memset(rx_ring->desc, 0, rx_ring->size);
1981
1982 rx_ring->next_to_clean = 0;
1983 rx_ring->next_to_use = 0;
1984
1985 writel(0, adapter->hw.hw_addr + rx_ring->head);
1986 writel(0, adapter->hw.hw_addr + rx_ring->tail);
1987 }
1988
1989 /**
1990 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
1991 * @adapter: board private structure
1992 **/
1993 static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
1994 {
1995 int i;
1996
1997 for (i = 0; i < adapter->num_rx_queues; i++)
1998 igb_clean_rx_ring(adapter, &adapter->rx_ring[i]);
1999 }
2000
2001 /**
2002 * igb_set_mac - Change the Ethernet Address of the NIC
2003 * @netdev: network interface device structure
2004 * @p: pointer to an address structure
2005 *
2006 * Returns 0 on success, negative on failure
2007 **/
2008 static int igb_set_mac(struct net_device *netdev, void *p)
2009 {
2010 struct igb_adapter *adapter = netdev_priv(netdev);
2011 struct sockaddr *addr = p;
2012
2013 if (!is_valid_ether_addr(addr->sa_data))
2014 return -EADDRNOTAVAIL;
2015
2016 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2017 memcpy(adapter->hw.mac.addr, addr->sa_data, netdev->addr_len);
2018
2019 adapter->hw.mac.ops.rar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2020
2021 return 0;
2022 }
2023
2024 /**
2025 * igb_set_multi - Multicast and Promiscuous mode set
2026 * @netdev: network interface device structure
2027 *
2028 * The set_multi entry point is called whenever the multicast address
2029 * list or the network interface flags are updated. This routine is
2030 * responsible for configuring the hardware for proper multicast,
2031 * promiscuous mode, and all-multi behavior.
2032 **/
2033 static void igb_set_multi(struct net_device *netdev)
2034 {
2035 struct igb_adapter *adapter = netdev_priv(netdev);
2036 struct e1000_hw *hw = &adapter->hw;
2037 struct e1000_mac_info *mac = &hw->mac;
2038 struct dev_mc_list *mc_ptr;
2039 u8 *mta_list;
2040 u32 rctl;
2041 int i;
2042
2043 /* Check for Promiscuous and All Multicast modes */
2044
2045 rctl = rd32(E1000_RCTL);
2046
2047 if (netdev->flags & IFF_PROMISC)
2048 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
2049 else if (netdev->flags & IFF_ALLMULTI) {
2050 rctl |= E1000_RCTL_MPE;
2051 rctl &= ~E1000_RCTL_UPE;
2052 } else
2053 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE);
2054
2055 wr32(E1000_RCTL, rctl);
2056
2057 if (!netdev->mc_count) {
2058 /* nothing to program, so clear mc list */
2059 igb_update_mc_addr_list(hw, NULL, 0, 1,
2060 mac->rar_entry_count);
2061 return;
2062 }
2063
2064 mta_list = kzalloc(netdev->mc_count * 6, GFP_ATOMIC);
2065 if (!mta_list)
2066 return;
2067
2068 /* The shared function expects a packed array of only addresses. */
2069 mc_ptr = netdev->mc_list;
2070
2071 for (i = 0; i < netdev->mc_count; i++) {
2072 if (!mc_ptr)
2073 break;
2074 memcpy(mta_list + (i*ETH_ALEN), mc_ptr->dmi_addr, ETH_ALEN);
2075 mc_ptr = mc_ptr->next;
2076 }
2077 igb_update_mc_addr_list(hw, mta_list, i, 1, mac->rar_entry_count);
2078 kfree(mta_list);
2079 }
2080
2081 /* Need to wait a few seconds after link up to get diagnostic information from
2082 * the phy */
2083 static void igb_update_phy_info(unsigned long data)
2084 {
2085 struct igb_adapter *adapter = (struct igb_adapter *) data;
2086 adapter->hw.phy.ops.get_phy_info(&adapter->hw);
2087 }
2088
2089 /**
2090 * igb_watchdog - Timer Call-back
2091 * @data: pointer to adapter cast into an unsigned long
2092 **/
2093 static void igb_watchdog(unsigned long data)
2094 {
2095 struct igb_adapter *adapter = (struct igb_adapter *)data;
2096 /* Do the rest outside of interrupt context */
2097 schedule_work(&adapter->watchdog_task);
2098 }
2099
2100 static void igb_watchdog_task(struct work_struct *work)
2101 {
2102 struct igb_adapter *adapter = container_of(work,
2103 struct igb_adapter, watchdog_task);
2104 struct e1000_hw *hw = &adapter->hw;
2105
2106 struct net_device *netdev = adapter->netdev;
2107 struct igb_ring *tx_ring = adapter->tx_ring;
2108 struct e1000_mac_info *mac = &adapter->hw.mac;
2109 u32 link;
2110 s32 ret_val;
2111
2112 if ((netif_carrier_ok(netdev)) &&
2113 (rd32(E1000_STATUS) & E1000_STATUS_LU))
2114 goto link_up;
2115
2116 ret_val = hw->mac.ops.check_for_link(&adapter->hw);
2117 if ((ret_val == E1000_ERR_PHY) &&
2118 (hw->phy.type == e1000_phy_igp_3) &&
2119 (rd32(E1000_CTRL) &
2120 E1000_PHY_CTRL_GBE_DISABLE))
2121 dev_info(&adapter->pdev->dev,
2122 "Gigabit has been disabled, downgrading speed\n");
2123
2124 if ((hw->phy.media_type == e1000_media_type_internal_serdes) &&
2125 !(rd32(E1000_TXCW) & E1000_TXCW_ANE))
2126 link = mac->serdes_has_link;
2127 else
2128 link = rd32(E1000_STATUS) &
2129 E1000_STATUS_LU;
2130
2131 if (link) {
2132 if (!netif_carrier_ok(netdev)) {
2133 u32 ctrl;
2134 hw->mac.ops.get_speed_and_duplex(&adapter->hw,
2135 &adapter->link_speed,
2136 &adapter->link_duplex);
2137
2138 ctrl = rd32(E1000_CTRL);
2139 dev_info(&adapter->pdev->dev,
2140 "NIC Link is Up %d Mbps %s, "
2141 "Flow Control: %s\n",
2142 adapter->link_speed,
2143 adapter->link_duplex == FULL_DUPLEX ?
2144 "Full Duplex" : "Half Duplex",
2145 ((ctrl & E1000_CTRL_TFCE) && (ctrl &
2146 E1000_CTRL_RFCE)) ? "RX/TX" : ((ctrl &
2147 E1000_CTRL_RFCE) ? "RX" : ((ctrl &
2148 E1000_CTRL_TFCE) ? "TX" : "None")));
2149
2150 /* tweak tx_queue_len according to speed/duplex and
2151 * adjust the timeout factor */
2152 netdev->tx_queue_len = adapter->tx_queue_len;
2153 adapter->tx_timeout_factor = 1;
2154 switch (adapter->link_speed) {
2155 case SPEED_10:
2156 netdev->tx_queue_len = 10;
2157 adapter->tx_timeout_factor = 14;
2158 break;
2159 case SPEED_100:
2160 netdev->tx_queue_len = 100;
2161 /* maybe add some timeout factor ? */
2162 break;
2163 }
2164
2165 netif_carrier_on(netdev);
2166 netif_wake_queue(netdev);
2167
2168 if (!test_bit(__IGB_DOWN, &adapter->state))
2169 mod_timer(&adapter->phy_info_timer,
2170 round_jiffies(jiffies + 2 * HZ));
2171 }
2172 } else {
2173 if (netif_carrier_ok(netdev)) {
2174 adapter->link_speed = 0;
2175 adapter->link_duplex = 0;
2176 dev_info(&adapter->pdev->dev, "NIC Link is Down\n");
2177 netif_carrier_off(netdev);
2178 netif_stop_queue(netdev);
2179 if (!test_bit(__IGB_DOWN, &adapter->state))
2180 mod_timer(&adapter->phy_info_timer,
2181 round_jiffies(jiffies + 2 * HZ));
2182 }
2183 }
2184
2185 link_up:
2186 igb_update_stats(adapter);
2187
2188 mac->tx_packet_delta = adapter->stats.tpt - adapter->tpt_old;
2189 adapter->tpt_old = adapter->stats.tpt;
2190 mac->collision_delta = adapter->stats.colc - adapter->colc_old;
2191 adapter->colc_old = adapter->stats.colc;
2192
2193 adapter->gorc = adapter->stats.gorc - adapter->gorc_old;
2194 adapter->gorc_old = adapter->stats.gorc;
2195 adapter->gotc = adapter->stats.gotc - adapter->gotc_old;
2196 adapter->gotc_old = adapter->stats.gotc;
2197
2198 igb_update_adaptive(&adapter->hw);
2199
2200 if (!netif_carrier_ok(netdev)) {
2201 if (IGB_DESC_UNUSED(tx_ring) + 1 < tx_ring->count) {
2202 /* We've lost link, so the controller stops DMA,
2203 * but we've got queued Tx work that's never going
2204 * to get done, so reset controller to flush Tx.
2205 * (Do the reset outside of interrupt context). */
2206 adapter->tx_timeout_count++;
2207 schedule_work(&adapter->reset_task);
2208 }
2209 }
2210
2211 /* Cause software interrupt to ensure rx ring is cleaned */
2212 wr32(E1000_ICS, E1000_ICS_RXDMT0);
2213
2214 /* Force detection of hung controller every watchdog period */
2215 tx_ring->detect_tx_hung = true;
2216
2217 /* Reset the timer */
2218 if (!test_bit(__IGB_DOWN, &adapter->state))
2219 mod_timer(&adapter->watchdog_timer,
2220 round_jiffies(jiffies + 2 * HZ));
2221 }
2222
2223 enum latency_range {
2224 lowest_latency = 0,
2225 low_latency = 1,
2226 bulk_latency = 2,
2227 latency_invalid = 255
2228 };
2229
2230
2231 static void igb_lower_rx_eitr(struct igb_adapter *adapter,
2232 struct igb_ring *rx_ring)
2233 {
2234 struct e1000_hw *hw = &adapter->hw;
2235 int new_val;
2236
2237 new_val = rx_ring->itr_val / 2;
2238 if (new_val < IGB_MIN_DYN_ITR)
2239 new_val = IGB_MIN_DYN_ITR;
2240
2241 if (new_val != rx_ring->itr_val) {
2242 rx_ring->itr_val = new_val;
2243 wr32(rx_ring->itr_register,
2244 1000000000 / (new_val * 256));
2245 }
2246 }
2247
2248 static void igb_raise_rx_eitr(struct igb_adapter *adapter,
2249 struct igb_ring *rx_ring)
2250 {
2251 struct e1000_hw *hw = &adapter->hw;
2252 int new_val;
2253
2254 new_val = rx_ring->itr_val * 2;
2255 if (new_val > IGB_MAX_DYN_ITR)
2256 new_val = IGB_MAX_DYN_ITR;
2257
2258 if (new_val != rx_ring->itr_val) {
2259 rx_ring->itr_val = new_val;
2260 wr32(rx_ring->itr_register,
2261 1000000000 / (new_val * 256));
2262 }
2263 }
2264
2265 /**
2266 * igb_update_itr - update the dynamic ITR value based on statistics
2267 * Stores a new ITR value based on packets and byte
2268 * counts during the last interrupt. The advantage of per interrupt
2269 * computation is faster updates and more accurate ITR for the current
2270 * traffic pattern. Constants in this function were computed
2271 * based on theoretical maximum wire speed and thresholds were set based
2272 * on testing data as well as attempting to minimize response time
2273 * while increasing bulk throughput.
2274 * this functionality is controlled by the InterruptThrottleRate module
2275 * parameter (see igb_param.c)
2276 * NOTE: These calculations are only valid when operating in a single-
2277 * queue environment.
2278 * @adapter: pointer to adapter
2279 * @itr_setting: current adapter->itr
2280 * @packets: the number of packets during this measurement interval
2281 * @bytes: the number of bytes during this measurement interval
2282 **/
2283 static unsigned int igb_update_itr(struct igb_adapter *adapter, u16 itr_setting,
2284 int packets, int bytes)
2285 {
2286 unsigned int retval = itr_setting;
2287
2288 if (packets == 0)
2289 goto update_itr_done;
2290
2291 switch (itr_setting) {
2292 case lowest_latency:
2293 /* handle TSO and jumbo frames */
2294 if (bytes/packets > 8000)
2295 retval = bulk_latency;
2296 else if ((packets < 5) && (bytes > 512))
2297 retval = low_latency;
2298 break;
2299 case low_latency: /* 50 usec aka 20000 ints/s */
2300 if (bytes > 10000) {
2301 /* this if handles the TSO accounting */
2302 if (bytes/packets > 8000) {
2303 retval = bulk_latency;
2304 } else if ((packets < 10) || ((bytes/packets) > 1200)) {
2305 retval = bulk_latency;
2306 } else if ((packets > 35)) {
2307 retval = lowest_latency;
2308 }
2309 } else if (bytes/packets > 2000) {
2310 retval = bulk_latency;
2311 } else if (packets <= 2 && bytes < 512) {
2312 retval = lowest_latency;
2313 }
2314 break;
2315 case bulk_latency: /* 250 usec aka 4000 ints/s */
2316 if (bytes > 25000) {
2317 if (packets > 35)
2318 retval = low_latency;
2319 } else if (bytes < 6000) {
2320 retval = low_latency;
2321 }
2322 break;
2323 }
2324
2325 update_itr_done:
2326 return retval;
2327 }
2328
2329 static void igb_set_itr(struct igb_adapter *adapter, u16 itr_register,
2330 int rx_only)
2331 {
2332 u16 current_itr;
2333 u32 new_itr = adapter->itr;
2334
2335 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2336 if (adapter->link_speed != SPEED_1000) {
2337 current_itr = 0;
2338 new_itr = 4000;
2339 goto set_itr_now;
2340 }
2341
2342 adapter->rx_itr = igb_update_itr(adapter,
2343 adapter->rx_itr,
2344 adapter->rx_ring->total_packets,
2345 adapter->rx_ring->total_bytes);
2346 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2347 if (adapter->itr_setting == 3 && adapter->rx_itr == lowest_latency)
2348 adapter->rx_itr = low_latency;
2349
2350 if (!rx_only) {
2351 adapter->tx_itr = igb_update_itr(adapter,
2352 adapter->tx_itr,
2353 adapter->tx_ring->total_packets,
2354 adapter->tx_ring->total_bytes);
2355 /* conservative mode (itr 3) eliminates the
2356 * lowest_latency setting */
2357 if (adapter->itr_setting == 3 &&
2358 adapter->tx_itr == lowest_latency)
2359 adapter->tx_itr = low_latency;
2360
2361 current_itr = max(adapter->rx_itr, adapter->tx_itr);
2362 } else {
2363 current_itr = adapter->rx_itr;
2364 }
2365
2366 switch (current_itr) {
2367 /* counts and packets in update_itr are dependent on these numbers */
2368 case lowest_latency:
2369 new_itr = 70000;
2370 break;
2371 case low_latency:
2372 new_itr = 20000; /* aka hwitr = ~200 */
2373 break;
2374 case bulk_latency:
2375 new_itr = 4000;
2376 break;
2377 default:
2378 break;
2379 }
2380
2381 set_itr_now:
2382 if (new_itr != adapter->itr) {
2383 /* this attempts to bias the interrupt rate towards Bulk
2384 * by adding intermediate steps when interrupt rate is
2385 * increasing */
2386 new_itr = new_itr > adapter->itr ?
2387 min(adapter->itr + (new_itr >> 2), new_itr) :
2388 new_itr;
2389 /* Don't write the value here; it resets the adapter's
2390 * internal timer, and causes us to delay far longer than
2391 * we should between interrupts. Instead, we write the ITR
2392 * value at the beginning of the next interrupt so the timing
2393 * ends up being correct.
2394 */
2395 adapter->itr = new_itr;
2396 adapter->set_itr = 1;
2397 }
2398
2399 return;
2400 }
2401
2402
2403 #define IGB_TX_FLAGS_CSUM 0x00000001
2404 #define IGB_TX_FLAGS_VLAN 0x00000002
2405 #define IGB_TX_FLAGS_TSO 0x00000004
2406 #define IGB_TX_FLAGS_IPV4 0x00000008
2407 #define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
2408 #define IGB_TX_FLAGS_VLAN_SHIFT 16
2409
2410 static inline int igb_tso_adv(struct igb_adapter *adapter,
2411 struct igb_ring *tx_ring,
2412 struct sk_buff *skb, u32 tx_flags, u8 *hdr_len)
2413 {
2414 struct e1000_adv_tx_context_desc *context_desc;
2415 unsigned int i;
2416 int err;
2417 struct igb_buffer *buffer_info;
2418 u32 info = 0, tu_cmd = 0;
2419 u32 mss_l4len_idx, l4len;
2420 *hdr_len = 0;
2421
2422 if (skb_header_cloned(skb)) {
2423 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2424 if (err)
2425 return err;
2426 }
2427
2428 l4len = tcp_hdrlen(skb);
2429 *hdr_len += l4len;
2430
2431 if (skb->protocol == htons(ETH_P_IP)) {
2432 struct iphdr *iph = ip_hdr(skb);
2433 iph->tot_len = 0;
2434 iph->check = 0;
2435 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2436 iph->daddr, 0,
2437 IPPROTO_TCP,
2438 0);
2439 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
2440 ipv6_hdr(skb)->payload_len = 0;
2441 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2442 &ipv6_hdr(skb)->daddr,
2443 0, IPPROTO_TCP, 0);
2444 }
2445
2446 i = tx_ring->next_to_use;
2447
2448 buffer_info = &tx_ring->buffer_info[i];
2449 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2450 /* VLAN MACLEN IPLEN */
2451 if (tx_flags & IGB_TX_FLAGS_VLAN)
2452 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2453 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2454 *hdr_len += skb_network_offset(skb);
2455 info |= skb_network_header_len(skb);
2456 *hdr_len += skb_network_header_len(skb);
2457 context_desc->vlan_macip_lens = cpu_to_le32(info);
2458
2459 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
2460 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2461
2462 if (skb->protocol == htons(ETH_P_IP))
2463 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2464 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2465
2466 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2467
2468 /* MSS L4LEN IDX */
2469 mss_l4len_idx = (skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT);
2470 mss_l4len_idx |= (l4len << E1000_ADVTXD_L4LEN_SHIFT);
2471
2472 /* Context index must be unique per ring. Luckily, so is the interrupt
2473 * mask value. */
2474 mss_l4len_idx |= tx_ring->eims_value >> 4;
2475
2476 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
2477 context_desc->seqnum_seed = 0;
2478
2479 buffer_info->time_stamp = jiffies;
2480 buffer_info->dma = 0;
2481 i++;
2482 if (i == tx_ring->count)
2483 i = 0;
2484
2485 tx_ring->next_to_use = i;
2486
2487 return true;
2488 }
2489
2490 static inline bool igb_tx_csum_adv(struct igb_adapter *adapter,
2491 struct igb_ring *tx_ring,
2492 struct sk_buff *skb, u32 tx_flags)
2493 {
2494 struct e1000_adv_tx_context_desc *context_desc;
2495 unsigned int i;
2496 struct igb_buffer *buffer_info;
2497 u32 info = 0, tu_cmd = 0;
2498
2499 if ((skb->ip_summed == CHECKSUM_PARTIAL) ||
2500 (tx_flags & IGB_TX_FLAGS_VLAN)) {
2501 i = tx_ring->next_to_use;
2502 buffer_info = &tx_ring->buffer_info[i];
2503 context_desc = E1000_TX_CTXTDESC_ADV(*tx_ring, i);
2504
2505 if (tx_flags & IGB_TX_FLAGS_VLAN)
2506 info |= (tx_flags & IGB_TX_FLAGS_VLAN_MASK);
2507 info |= (skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT);
2508 if (skb->ip_summed == CHECKSUM_PARTIAL)
2509 info |= skb_network_header_len(skb);
2510
2511 context_desc->vlan_macip_lens = cpu_to_le32(info);
2512
2513 tu_cmd |= (E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT);
2514
2515 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2516 if (skb->protocol == htons(ETH_P_IP))
2517 tu_cmd |= E1000_ADVTXD_TUCMD_IPV4;
2518 if (skb->sk && (skb->sk->sk_protocol == IPPROTO_TCP))
2519 tu_cmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
2520 }
2521
2522 context_desc->type_tucmd_mlhl = cpu_to_le32(tu_cmd);
2523 context_desc->seqnum_seed = 0;
2524 context_desc->mss_l4len_idx =
2525 cpu_to_le32(tx_ring->eims_value >> 4);
2526
2527 buffer_info->time_stamp = jiffies;
2528 buffer_info->dma = 0;
2529
2530 i++;
2531 if (i == tx_ring->count)
2532 i = 0;
2533 tx_ring->next_to_use = i;
2534
2535 return true;
2536 }
2537
2538
2539 return false;
2540 }
2541
2542 #define IGB_MAX_TXD_PWR 16
2543 #define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR)
2544
2545 static inline int igb_tx_map_adv(struct igb_adapter *adapter,
2546 struct igb_ring *tx_ring,
2547 struct sk_buff *skb)
2548 {
2549 struct igb_buffer *buffer_info;
2550 unsigned int len = skb_headlen(skb);
2551 unsigned int count = 0, i;
2552 unsigned int f;
2553
2554 i = tx_ring->next_to_use;
2555
2556 buffer_info = &tx_ring->buffer_info[i];
2557 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2558 buffer_info->length = len;
2559 /* set time_stamp *before* dma to help avoid a possible race */
2560 buffer_info->time_stamp = jiffies;
2561 buffer_info->dma = pci_map_single(adapter->pdev, skb->data, len,
2562 PCI_DMA_TODEVICE);
2563 count++;
2564 i++;
2565 if (i == tx_ring->count)
2566 i = 0;
2567
2568 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) {
2569 struct skb_frag_struct *frag;
2570
2571 frag = &skb_shinfo(skb)->frags[f];
2572 len = frag->size;
2573
2574 buffer_info = &tx_ring->buffer_info[i];
2575 BUG_ON(len >= IGB_MAX_DATA_PER_TXD);
2576 buffer_info->length = len;
2577 buffer_info->time_stamp = jiffies;
2578 buffer_info->dma = pci_map_page(adapter->pdev,
2579 frag->page,
2580 frag->page_offset,
2581 len,
2582 PCI_DMA_TODEVICE);
2583
2584 count++;
2585 i++;
2586 if (i == tx_ring->count)
2587 i = 0;
2588 }
2589
2590 i = (i == 0) ? tx_ring->count - 1 : i - 1;
2591 tx_ring->buffer_info[i].skb = skb;
2592
2593 return count;
2594 }
2595
2596 static inline void igb_tx_queue_adv(struct igb_adapter *adapter,
2597 struct igb_ring *tx_ring,
2598 int tx_flags, int count, u32 paylen,
2599 u8 hdr_len)
2600 {
2601 union e1000_adv_tx_desc *tx_desc = NULL;
2602 struct igb_buffer *buffer_info;
2603 u32 olinfo_status = 0, cmd_type_len;
2604 unsigned int i;
2605
2606 cmd_type_len = (E1000_ADVTXD_DTYP_DATA | E1000_ADVTXD_DCMD_IFCS |
2607 E1000_ADVTXD_DCMD_DEXT);
2608
2609 if (tx_flags & IGB_TX_FLAGS_VLAN)
2610 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2611
2612 if (tx_flags & IGB_TX_FLAGS_TSO) {
2613 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2614
2615 /* insert tcp checksum */
2616 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2617
2618 /* insert ip checksum */
2619 if (tx_flags & IGB_TX_FLAGS_IPV4)
2620 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2621
2622 } else if (tx_flags & IGB_TX_FLAGS_CSUM) {
2623 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2624 }
2625
2626 if (tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_TSO |
2627 IGB_TX_FLAGS_VLAN))
2628 olinfo_status |= tx_ring->eims_value >> 4;
2629
2630 olinfo_status |= ((paylen - hdr_len) << E1000_ADVTXD_PAYLEN_SHIFT);
2631
2632 i = tx_ring->next_to_use;
2633 while (count--) {
2634 buffer_info = &tx_ring->buffer_info[i];
2635 tx_desc = E1000_TX_DESC_ADV(*tx_ring, i);
2636 tx_desc->read.buffer_addr = cpu_to_le64(buffer_info->dma);
2637 tx_desc->read.cmd_type_len =
2638 cpu_to_le32(cmd_type_len | buffer_info->length);
2639 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
2640 i++;
2641 if (i == tx_ring->count)
2642 i = 0;
2643 }
2644
2645 tx_desc->read.cmd_type_len |= cpu_to_le32(adapter->txd_cmd);
2646 /* Force memory writes to complete before letting h/w
2647 * know there are new descriptors to fetch. (Only
2648 * applicable for weak-ordered memory model archs,
2649 * such as IA-64). */
2650 wmb();
2651
2652 tx_ring->next_to_use = i;
2653 writel(i, adapter->hw.hw_addr + tx_ring->tail);
2654 /* we need this if more than one processor can write to our tail
2655 * at a time, it syncronizes IO on IA64/Altix systems */
2656 mmiowb();
2657 }
2658
2659 static int __igb_maybe_stop_tx(struct net_device *netdev,
2660 struct igb_ring *tx_ring, int size)
2661 {
2662 struct igb_adapter *adapter = netdev_priv(netdev);
2663
2664 netif_stop_queue(netdev);
2665 /* Herbert's original patch had:
2666 * smp_mb__after_netif_stop_queue();
2667 * but since that doesn't exist yet, just open code it. */
2668 smp_mb();
2669
2670 /* We need to check again in a case another CPU has just
2671 * made room available. */
2672 if (IGB_DESC_UNUSED(tx_ring) < size)
2673 return -EBUSY;
2674
2675 /* A reprieve! */
2676 netif_start_queue(netdev);
2677 ++adapter->restart_queue;
2678 return 0;
2679 }
2680
2681 static int igb_maybe_stop_tx(struct net_device *netdev,
2682 struct igb_ring *tx_ring, int size)
2683 {
2684 if (IGB_DESC_UNUSED(tx_ring) >= size)
2685 return 0;
2686 return __igb_maybe_stop_tx(netdev, tx_ring, size);
2687 }
2688
2689 #define TXD_USE_COUNT(S) (((S) >> (IGB_MAX_TXD_PWR)) + 1)
2690
2691 static int igb_xmit_frame_ring_adv(struct sk_buff *skb,
2692 struct net_device *netdev,
2693 struct igb_ring *tx_ring)
2694 {
2695 struct igb_adapter *adapter = netdev_priv(netdev);
2696 unsigned int tx_flags = 0;
2697 unsigned int len;
2698 unsigned long irq_flags;
2699 u8 hdr_len = 0;
2700 int tso = 0;
2701
2702 len = skb_headlen(skb);
2703
2704 if (test_bit(__IGB_DOWN, &adapter->state)) {
2705 dev_kfree_skb_any(skb);
2706 return NETDEV_TX_OK;
2707 }
2708
2709 if (skb->len <= 0) {
2710 dev_kfree_skb_any(skb);
2711 return NETDEV_TX_OK;
2712 }
2713
2714 if (!spin_trylock_irqsave(&tx_ring->tx_lock, irq_flags))
2715 /* Collision - tell upper layer to requeue */
2716 return NETDEV_TX_LOCKED;
2717
2718 /* need: 1 descriptor per page,
2719 * + 2 desc gap to keep tail from touching head,
2720 * + 1 desc for skb->data,
2721 * + 1 desc for context descriptor,
2722 * otherwise try next time */
2723 if (igb_maybe_stop_tx(netdev, tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
2724 /* this is a hard error */
2725 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2726 return NETDEV_TX_BUSY;
2727 }
2728
2729 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
2730 tx_flags |= IGB_TX_FLAGS_VLAN;
2731 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
2732 }
2733
2734 tso = skb_is_gso(skb) ? igb_tso_adv(adapter, tx_ring, skb, tx_flags,
2735 &hdr_len) : 0;
2736
2737 if (tso < 0) {
2738 dev_kfree_skb_any(skb);
2739 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2740 return NETDEV_TX_OK;
2741 }
2742
2743 if (tso)
2744 tx_flags |= IGB_TX_FLAGS_TSO;
2745 else if (igb_tx_csum_adv(adapter, tx_ring, skb, tx_flags))
2746 if (skb->ip_summed == CHECKSUM_PARTIAL)
2747 tx_flags |= IGB_TX_FLAGS_CSUM;
2748
2749 if (skb->protocol == htons(ETH_P_IP))
2750 tx_flags |= IGB_TX_FLAGS_IPV4;
2751
2752 igb_tx_queue_adv(adapter, tx_ring, tx_flags,
2753 igb_tx_map_adv(adapter, tx_ring, skb),
2754 skb->len, hdr_len);
2755
2756 netdev->trans_start = jiffies;
2757
2758 /* Make sure there is space in the ring for the next send. */
2759 igb_maybe_stop_tx(netdev, tx_ring, MAX_SKB_FRAGS + 4);
2760
2761 spin_unlock_irqrestore(&tx_ring->tx_lock, irq_flags);
2762 return NETDEV_TX_OK;
2763 }
2764
2765 static int igb_xmit_frame_adv(struct sk_buff *skb, struct net_device *netdev)
2766 {
2767 struct igb_adapter *adapter = netdev_priv(netdev);
2768 struct igb_ring *tx_ring = &adapter->tx_ring[0];
2769
2770 /* This goes back to the question of how to logically map a tx queue
2771 * to a flow. Right now, performance is impacted slightly negatively
2772 * if using multiple tx queues. If the stack breaks away from a
2773 * single qdisc implementation, we can look at this again. */
2774 return (igb_xmit_frame_ring_adv(skb, netdev, tx_ring));
2775 }
2776
2777 /**
2778 * igb_tx_timeout - Respond to a Tx Hang
2779 * @netdev: network interface device structure
2780 **/
2781 static void igb_tx_timeout(struct net_device *netdev)
2782 {
2783 struct igb_adapter *adapter = netdev_priv(netdev);
2784 struct e1000_hw *hw = &adapter->hw;
2785
2786 /* Do the reset outside of interrupt context */
2787 adapter->tx_timeout_count++;
2788 schedule_work(&adapter->reset_task);
2789 wr32(E1000_EICS, adapter->eims_enable_mask &
2790 ~(E1000_EIMS_TCP_TIMER | E1000_EIMS_OTHER));
2791 }
2792
2793 static void igb_reset_task(struct work_struct *work)
2794 {
2795 struct igb_adapter *adapter;
2796 adapter = container_of(work, struct igb_adapter, reset_task);
2797
2798 igb_reinit_locked(adapter);
2799 }
2800
2801 /**
2802 * igb_get_stats - Get System Network Statistics
2803 * @netdev: network interface device structure
2804 *
2805 * Returns the address of the device statistics structure.
2806 * The statistics are actually updated from the timer callback.
2807 **/
2808 static struct net_device_stats *
2809 igb_get_stats(struct net_device *netdev)
2810 {
2811 struct igb_adapter *adapter = netdev_priv(netdev);
2812
2813 /* only return the current stats */
2814 return &adapter->net_stats;
2815 }
2816
2817 /**
2818 * igb_change_mtu - Change the Maximum Transfer Unit
2819 * @netdev: network interface device structure
2820 * @new_mtu: new value for maximum frame size
2821 *
2822 * Returns 0 on success, negative on failure
2823 **/
2824 static int igb_change_mtu(struct net_device *netdev, int new_mtu)
2825 {
2826 struct igb_adapter *adapter = netdev_priv(netdev);
2827 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2828
2829 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2830 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2831 dev_err(&adapter->pdev->dev, "Invalid MTU setting\n");
2832 return -EINVAL;
2833 }
2834
2835 #define MAX_STD_JUMBO_FRAME_SIZE 9234
2836 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
2837 dev_err(&adapter->pdev->dev, "MTU > 9216 not supported.\n");
2838 return -EINVAL;
2839 }
2840
2841 while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
2842 msleep(1);
2843 /* igb_down has a dependency on max_frame_size */
2844 adapter->max_frame_size = max_frame;
2845 if (netif_running(netdev))
2846 igb_down(adapter);
2847
2848 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
2849 * means we reserve 2 more, this pushes us to allocate from the next
2850 * larger slab size.
2851 * i.e. RXBUFFER_2048 --> size-4096 slab
2852 */
2853
2854 if (max_frame <= IGB_RXBUFFER_256)
2855 adapter->rx_buffer_len = IGB_RXBUFFER_256;
2856 else if (max_frame <= IGB_RXBUFFER_512)
2857 adapter->rx_buffer_len = IGB_RXBUFFER_512;
2858 else if (max_frame <= IGB_RXBUFFER_1024)
2859 adapter->rx_buffer_len = IGB_RXBUFFER_1024;
2860 else if (max_frame <= IGB_RXBUFFER_2048)
2861 adapter->rx_buffer_len = IGB_RXBUFFER_2048;
2862 else
2863 adapter->rx_buffer_len = IGB_RXBUFFER_4096;
2864 /* adjust allocation if LPE protects us, and we aren't using SBP */
2865 if ((max_frame == ETH_FRAME_LEN + ETH_FCS_LEN) ||
2866 (max_frame == MAXIMUM_ETHERNET_VLAN_SIZE))
2867 adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2868
2869 dev_info(&adapter->pdev->dev, "changing MTU from %d to %d\n",
2870 netdev->mtu, new_mtu);
2871 netdev->mtu = new_mtu;
2872
2873 if (netif_running(netdev))
2874 igb_up(adapter);
2875 else
2876 igb_reset(adapter);
2877
2878 clear_bit(__IGB_RESETTING, &adapter->state);
2879
2880 return 0;
2881 }
2882
2883 /**
2884 * igb_update_stats - Update the board statistics counters
2885 * @adapter: board private structure
2886 **/
2887
2888 void igb_update_stats(struct igb_adapter *adapter)
2889 {
2890 struct e1000_hw *hw = &adapter->hw;
2891 struct pci_dev *pdev = adapter->pdev;
2892 u16 phy_tmp;
2893
2894 #define PHY_IDLE_ERROR_COUNT_MASK 0x00FF
2895
2896 /*
2897 * Prevent stats update while adapter is being reset, or if the pci
2898 * connection is down.
2899 */
2900 if (adapter->link_speed == 0)
2901 return;
2902 if (pci_channel_offline(pdev))
2903 return;
2904
2905 adapter->stats.crcerrs += rd32(E1000_CRCERRS);
2906 adapter->stats.gprc += rd32(E1000_GPRC);
2907 adapter->stats.gorc += rd32(E1000_GORCL);
2908 rd32(E1000_GORCH); /* clear GORCL */
2909 adapter->stats.bprc += rd32(E1000_BPRC);
2910 adapter->stats.mprc += rd32(E1000_MPRC);
2911 adapter->stats.roc += rd32(E1000_ROC);
2912
2913 adapter->stats.prc64 += rd32(E1000_PRC64);
2914 adapter->stats.prc127 += rd32(E1000_PRC127);
2915 adapter->stats.prc255 += rd32(E1000_PRC255);
2916 adapter->stats.prc511 += rd32(E1000_PRC511);
2917 adapter->stats.prc1023 += rd32(E1000_PRC1023);
2918 adapter->stats.prc1522 += rd32(E1000_PRC1522);
2919 adapter->stats.symerrs += rd32(E1000_SYMERRS);
2920 adapter->stats.sec += rd32(E1000_SEC);
2921
2922 adapter->stats.mpc += rd32(E1000_MPC);
2923 adapter->stats.scc += rd32(E1000_SCC);
2924 adapter->stats.ecol += rd32(E1000_ECOL);
2925 adapter->stats.mcc += rd32(E1000_MCC);
2926 adapter->stats.latecol += rd32(E1000_LATECOL);
2927 adapter->stats.dc += rd32(E1000_DC);
2928 adapter->stats.rlec += rd32(E1000_RLEC);
2929 adapter->stats.xonrxc += rd32(E1000_XONRXC);
2930 adapter->stats.xontxc += rd32(E1000_XONTXC);
2931 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
2932 adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
2933 adapter->stats.fcruc += rd32(E1000_FCRUC);
2934 adapter->stats.gptc += rd32(E1000_GPTC);
2935 adapter->stats.gotc += rd32(E1000_GOTCL);
2936 rd32(E1000_GOTCH); /* clear GOTCL */
2937 adapter->stats.rnbc += rd32(E1000_RNBC);
2938 adapter->stats.ruc += rd32(E1000_RUC);
2939 adapter->stats.rfc += rd32(E1000_RFC);
2940 adapter->stats.rjc += rd32(E1000_RJC);
2941 adapter->stats.tor += rd32(E1000_TORH);
2942 adapter->stats.tot += rd32(E1000_TOTH);
2943 adapter->stats.tpr += rd32(E1000_TPR);
2944
2945 adapter->stats.ptc64 += rd32(E1000_PTC64);
2946 adapter->stats.ptc127 += rd32(E1000_PTC127);
2947 adapter->stats.ptc255 += rd32(E1000_PTC255);
2948 adapter->stats.ptc511 += rd32(E1000_PTC511);
2949 adapter->stats.ptc1023 += rd32(E1000_PTC1023);
2950 adapter->stats.ptc1522 += rd32(E1000_PTC1522);
2951
2952 adapter->stats.mptc += rd32(E1000_MPTC);
2953 adapter->stats.bptc += rd32(E1000_BPTC);
2954
2955 /* used for adaptive IFS */
2956
2957 hw->mac.tx_packet_delta = rd32(E1000_TPT);
2958 adapter->stats.tpt += hw->mac.tx_packet_delta;
2959 hw->mac.collision_delta = rd32(E1000_COLC);
2960 adapter->stats.colc += hw->mac.collision_delta;
2961
2962 adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
2963 adapter->stats.rxerrc += rd32(E1000_RXERRC);
2964 adapter->stats.tncrs += rd32(E1000_TNCRS);
2965 adapter->stats.tsctc += rd32(E1000_TSCTC);
2966 adapter->stats.tsctfc += rd32(E1000_TSCTFC);
2967
2968 adapter->stats.iac += rd32(E1000_IAC);
2969 adapter->stats.icrxoc += rd32(E1000_ICRXOC);
2970 adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
2971 adapter->stats.icrxatc += rd32(E1000_ICRXATC);
2972 adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
2973 adapter->stats.ictxatc += rd32(E1000_ICTXATC);
2974 adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
2975 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
2976 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);
2977
2978 /* Fill out the OS statistics structure */
2979 adapter->net_stats.multicast = adapter->stats.mprc;
2980 adapter->net_stats.collisions = adapter->stats.colc;
2981
2982 /* Rx Errors */
2983
2984 /* RLEC on some newer hardware can be incorrect so build
2985 * our own version based on RUC and ROC */
2986 adapter->net_stats.rx_errors = adapter->stats.rxerrc +
2987 adapter->stats.crcerrs + adapter->stats.algnerrc +
2988 adapter->stats.ruc + adapter->stats.roc +
2989 adapter->stats.cexterr;
2990 adapter->net_stats.rx_length_errors = adapter->stats.ruc +
2991 adapter->stats.roc;
2992 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
2993 adapter->net_stats.rx_frame_errors = adapter->stats.algnerrc;
2994 adapter->net_stats.rx_missed_errors = adapter->stats.mpc;
2995
2996 /* Tx Errors */
2997 adapter->net_stats.tx_errors = adapter->stats.ecol +
2998 adapter->stats.latecol;
2999 adapter->net_stats.tx_aborted_errors = adapter->stats.ecol;
3000 adapter->net_stats.tx_window_errors = adapter->stats.latecol;
3001 adapter->net_stats.tx_carrier_errors = adapter->stats.tncrs;
3002
3003 /* Tx Dropped needs to be maintained elsewhere */
3004
3005 /* Phy Stats */
3006 if (hw->phy.media_type == e1000_media_type_copper) {
3007 if ((adapter->link_speed == SPEED_1000) &&
3008 (!hw->phy.ops.read_phy_reg(hw, PHY_1000T_STATUS,
3009 &phy_tmp))) {
3010 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
3011 adapter->phy_stats.idle_errors += phy_tmp;
3012 }
3013 }
3014
3015 /* Management Stats */
3016 adapter->stats.mgptc += rd32(E1000_MGTPTC);
3017 adapter->stats.mgprc += rd32(E1000_MGTPRC);
3018 adapter->stats.mgpdc += rd32(E1000_MGTPDC);
3019 }
3020
3021
3022 static irqreturn_t igb_msix_other(int irq, void *data)
3023 {
3024 struct net_device *netdev = data;
3025 struct igb_adapter *adapter = netdev_priv(netdev);
3026 struct e1000_hw *hw = &adapter->hw;
3027 u32 eicr;
3028 /* disable interrupts from the "other" bit, avoid re-entry */
3029 wr32(E1000_EIMC, E1000_EIMS_OTHER);
3030
3031 eicr = rd32(E1000_EICR);
3032
3033 if (eicr & E1000_EIMS_OTHER) {
3034 u32 icr = rd32(E1000_ICR);
3035 /* reading ICR causes bit 31 of EICR to be cleared */
3036 if (!(icr & E1000_ICR_LSC))
3037 goto no_link_interrupt;
3038 hw->mac.get_link_status = 1;
3039 /* guard against interrupt when we're going down */
3040 if (!test_bit(__IGB_DOWN, &adapter->state))
3041 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3042 }
3043
3044 no_link_interrupt:
3045 wr32(E1000_IMS, E1000_IMS_LSC);
3046 wr32(E1000_EIMS, E1000_EIMS_OTHER);
3047
3048 return IRQ_HANDLED;
3049 }
3050
3051 static irqreturn_t igb_msix_tx(int irq, void *data)
3052 {
3053 struct igb_ring *tx_ring = data;
3054 struct igb_adapter *adapter = tx_ring->adapter;
3055 struct e1000_hw *hw = &adapter->hw;
3056
3057 if (!tx_ring->itr_val)
3058 wr32(E1000_EIMC, tx_ring->eims_value);
3059
3060 tx_ring->total_bytes = 0;
3061 tx_ring->total_packets = 0;
3062 if (!igb_clean_tx_irq(adapter, tx_ring))
3063 /* Ring was not completely cleaned, so fire another interrupt */
3064 wr32(E1000_EICS, tx_ring->eims_value);
3065
3066 if (!tx_ring->itr_val)
3067 wr32(E1000_EIMS, tx_ring->eims_value);
3068 return IRQ_HANDLED;
3069 }
3070
3071 static irqreturn_t igb_msix_rx(int irq, void *data)
3072 {
3073 struct igb_ring *rx_ring = data;
3074 struct igb_adapter *adapter = rx_ring->adapter;
3075 struct e1000_hw *hw = &adapter->hw;
3076
3077 if (!rx_ring->itr_val)
3078 wr32(E1000_EIMC, rx_ring->eims_value);
3079
3080 if (netif_rx_schedule_prep(adapter->netdev, &rx_ring->napi)) {
3081 rx_ring->total_bytes = 0;
3082 rx_ring->total_packets = 0;
3083 rx_ring->no_itr_adjust = 0;
3084 __netif_rx_schedule(adapter->netdev, &rx_ring->napi);
3085 } else {
3086 if (!rx_ring->no_itr_adjust) {
3087 igb_lower_rx_eitr(adapter, rx_ring);
3088 rx_ring->no_itr_adjust = 1;
3089 }
3090 }
3091
3092 return IRQ_HANDLED;
3093 }
3094
3095
3096 /**
3097 * igb_intr_msi - Interrupt Handler
3098 * @irq: interrupt number
3099 * @data: pointer to a network interface device structure
3100 **/
3101 static irqreturn_t igb_intr_msi(int irq, void *data)
3102 {
3103 struct net_device *netdev = data;
3104 struct igb_adapter *adapter = netdev_priv(netdev);
3105 struct napi_struct *napi = &adapter->napi;
3106 struct e1000_hw *hw = &adapter->hw;
3107 /* read ICR disables interrupts using IAM */
3108 u32 icr = rd32(E1000_ICR);
3109
3110 /* Write the ITR value calculated at the end of the
3111 * previous interrupt.
3112 */
3113 if (adapter->set_itr) {
3114 wr32(E1000_ITR,
3115 1000000000 / (adapter->itr * 256));
3116 adapter->set_itr = 0;
3117 }
3118
3119 /* read ICR disables interrupts using IAM */
3120 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3121 hw->mac.get_link_status = 1;
3122 if (!test_bit(__IGB_DOWN, &adapter->state))
3123 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3124 }
3125
3126 if (netif_rx_schedule_prep(netdev, napi)) {
3127 adapter->tx_ring->total_bytes = 0;
3128 adapter->tx_ring->total_packets = 0;
3129 adapter->rx_ring->total_bytes = 0;
3130 adapter->rx_ring->total_packets = 0;
3131 __netif_rx_schedule(netdev, napi);
3132 }
3133
3134 return IRQ_HANDLED;
3135 }
3136
3137 /**
3138 * igb_intr - Interrupt Handler
3139 * @irq: interrupt number
3140 * @data: pointer to a network interface device structure
3141 **/
3142 static irqreturn_t igb_intr(int irq, void *data)
3143 {
3144 struct net_device *netdev = data;
3145 struct igb_adapter *adapter = netdev_priv(netdev);
3146 struct napi_struct *napi = &adapter->napi;
3147 struct e1000_hw *hw = &adapter->hw;
3148 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
3149 * need for the IMC write */
3150 u32 icr = rd32(E1000_ICR);
3151 u32 eicr = 0;
3152 if (!icr)
3153 return IRQ_NONE; /* Not our interrupt */
3154
3155 /* Write the ITR value calculated at the end of the
3156 * previous interrupt.
3157 */
3158 if (adapter->set_itr) {
3159 wr32(E1000_ITR,
3160 1000000000 / (adapter->itr * 256));
3161 adapter->set_itr = 0;
3162 }
3163
3164 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
3165 * not set, then the adapter didn't send an interrupt */
3166 if (!(icr & E1000_ICR_INT_ASSERTED))
3167 return IRQ_NONE;
3168
3169 eicr = rd32(E1000_EICR);
3170
3171 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3172 hw->mac.get_link_status = 1;
3173 /* guard against interrupt when we're going down */
3174 if (!test_bit(__IGB_DOWN, &adapter->state))
3175 mod_timer(&adapter->watchdog_timer, jiffies + 1);
3176 }
3177
3178 if (netif_rx_schedule_prep(netdev, napi)) {
3179 adapter->tx_ring->total_bytes = 0;
3180 adapter->rx_ring->total_bytes = 0;
3181 adapter->tx_ring->total_packets = 0;
3182 adapter->rx_ring->total_packets = 0;
3183 __netif_rx_schedule(netdev, napi);
3184 }
3185
3186 return IRQ_HANDLED;
3187 }
3188
3189 /**
3190 * igb_clean - NAPI Rx polling callback
3191 * @adapter: board private structure
3192 **/
3193 static int igb_clean(struct napi_struct *napi, int budget)
3194 {
3195 struct igb_adapter *adapter = container_of(napi, struct igb_adapter,
3196 napi);
3197 struct net_device *netdev = adapter->netdev;
3198 int tx_clean_complete = 1, work_done = 0;
3199 int i;
3200
3201 /* Must NOT use netdev_priv macro here. */
3202 adapter = netdev->priv;
3203
3204 /* Keep link state information with original netdev */
3205 if (!netif_carrier_ok(netdev))
3206 goto quit_polling;
3207
3208 /* igb_clean is called per-cpu. This lock protects tx_ring[i] from
3209 * being cleaned by multiple cpus simultaneously. A failure obtaining
3210 * the lock means tx_ring[i] is currently being cleaned anyway. */
3211 for (i = 0; i < adapter->num_tx_queues; i++) {
3212 if (spin_trylock(&adapter->tx_ring[i].tx_clean_lock)) {
3213 tx_clean_complete &= igb_clean_tx_irq(adapter,
3214 &adapter->tx_ring[i]);
3215 spin_unlock(&adapter->tx_ring[i].tx_clean_lock);
3216 }
3217 }
3218
3219 for (i = 0; i < adapter->num_rx_queues; i++)
3220 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i], &work_done,
3221 adapter->rx_ring[i].napi.weight);
3222
3223 /* If no Tx and not enough Rx work done, exit the polling mode */
3224 if ((tx_clean_complete && (work_done < budget)) ||
3225 !netif_running(netdev)) {
3226 quit_polling:
3227 if (adapter->itr_setting & 3)
3228 igb_set_itr(adapter, E1000_ITR, false);
3229 netif_rx_complete(netdev, napi);
3230 if (!test_bit(__IGB_DOWN, &adapter->state))
3231 igb_irq_enable(adapter);
3232 return 0;
3233 }
3234
3235 return 1;
3236 }
3237
3238 static int igb_clean_rx_ring_msix(struct napi_struct *napi, int budget)
3239 {
3240 struct igb_ring *rx_ring = container_of(napi, struct igb_ring, napi);
3241 struct igb_adapter *adapter = rx_ring->adapter;
3242 struct e1000_hw *hw = &adapter->hw;
3243 struct net_device *netdev = adapter->netdev;
3244 int work_done = 0;
3245
3246 /* Keep link state information with original netdev */
3247 if (!netif_carrier_ok(netdev))
3248 goto quit_polling;
3249
3250 igb_clean_rx_irq_adv(adapter, rx_ring, &work_done, budget);
3251
3252
3253 /* If not enough Rx work done, exit the polling mode */
3254 if ((work_done == 0) || !netif_running(netdev)) {
3255 quit_polling:
3256 netif_rx_complete(netdev, napi);
3257
3258 wr32(E1000_EIMS, rx_ring->eims_value);
3259 if ((adapter->itr_setting & 3) && !rx_ring->no_itr_adjust &&
3260 (rx_ring->total_packets > IGB_DYN_ITR_PACKET_THRESHOLD)) {
3261 int mean_size = rx_ring->total_bytes /
3262 rx_ring->total_packets;
3263 if (mean_size < IGB_DYN_ITR_LENGTH_LOW)
3264 igb_raise_rx_eitr(adapter, rx_ring);
3265 else if (mean_size > IGB_DYN_ITR_LENGTH_HIGH)
3266 igb_lower_rx_eitr(adapter, rx_ring);
3267 }
3268 return 0;
3269 }
3270
3271 return 1;
3272 }
3273 /**
3274 * igb_clean_tx_irq - Reclaim resources after transmit completes
3275 * @adapter: board private structure
3276 * returns true if ring is completely cleaned
3277 **/
3278 static bool igb_clean_tx_irq(struct igb_adapter *adapter,
3279 struct igb_ring *tx_ring)
3280 {
3281 struct net_device *netdev = adapter->netdev;
3282 struct e1000_hw *hw = &adapter->hw;
3283 struct e1000_tx_desc *tx_desc;
3284 struct igb_buffer *buffer_info;
3285 struct sk_buff *skb;
3286 unsigned int i;
3287 u32 head, oldhead;
3288 unsigned int count = 0;
3289 bool cleaned = false;
3290 bool retval = true;
3291 unsigned int total_bytes = 0, total_packets = 0;
3292
3293 rmb();
3294 head = *(volatile u32 *)((struct e1000_tx_desc *)tx_ring->desc
3295 + tx_ring->count);
3296 head = le32_to_cpu(head);
3297 i = tx_ring->next_to_clean;
3298 while (1) {
3299 while (i != head) {
3300 cleaned = true;
3301 tx_desc = E1000_TX_DESC(*tx_ring, i);
3302 buffer_info = &tx_ring->buffer_info[i];
3303 skb = buffer_info->skb;
3304
3305 if (skb) {
3306 unsigned int segs, bytecount;
3307 /* gso_segs is currently only valid for tcp */
3308 segs = skb_shinfo(skb)->gso_segs ?: 1;
3309 /* multiply data chunks by size of headers */
3310 bytecount = ((segs - 1) * skb_headlen(skb)) +
3311 skb->len;
3312 total_packets += segs;
3313 total_bytes += bytecount;
3314 }
3315
3316 igb_unmap_and_free_tx_resource(adapter, buffer_info);
3317 tx_desc->upper.data = 0;
3318
3319 i++;
3320 if (i == tx_ring->count)
3321 i = 0;
3322
3323 count++;
3324 if (count == IGB_MAX_TX_CLEAN) {
3325 retval = false;
3326 goto done_cleaning;
3327 }
3328 }
3329 oldhead = head;
3330 rmb();
3331 head = *(volatile u32 *)((struct e1000_tx_desc *)tx_ring->desc
3332 + tx_ring->count);
3333 head = le32_to_cpu(head);
3334 if (head == oldhead)
3335 goto done_cleaning;
3336 } /* while (1) */
3337
3338 done_cleaning:
3339 tx_ring->next_to_clean = i;
3340
3341 if (unlikely(cleaned &&
3342 netif_carrier_ok(netdev) &&
3343 IGB_DESC_UNUSED(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
3344 /* Make sure that anybody stopping the queue after this
3345 * sees the new next_to_clean.
3346 */
3347 smp_mb();
3348 if (netif_queue_stopped(netdev) &&
3349 !(test_bit(__IGB_DOWN, &adapter->state))) {
3350 netif_wake_queue(netdev);
3351 ++adapter->restart_queue;
3352 }
3353 }
3354
3355 if (tx_ring->detect_tx_hung) {
3356 /* Detect a transmit hang in hardware, this serializes the
3357 * check with the clearing of time_stamp and movement of i */
3358 tx_ring->detect_tx_hung = false;
3359 if (tx_ring->buffer_info[i].time_stamp &&
3360 time_after(jiffies, tx_ring->buffer_info[i].time_stamp +
3361 (adapter->tx_timeout_factor * HZ))
3362 && !(rd32(E1000_STATUS) &
3363 E1000_STATUS_TXOFF)) {
3364
3365 tx_desc = E1000_TX_DESC(*tx_ring, i);
3366 /* detected Tx unit hang */
3367 dev_err(&adapter->pdev->dev,
3368 "Detected Tx Unit Hang\n"
3369 " Tx Queue <%lu>\n"
3370 " TDH <%x>\n"
3371 " TDT <%x>\n"
3372 " next_to_use <%x>\n"
3373 " next_to_clean <%x>\n"
3374 " head (WB) <%x>\n"
3375 "buffer_info[next_to_clean]\n"
3376 " time_stamp <%lx>\n"
3377 " jiffies <%lx>\n"
3378 " desc.status <%x>\n",
3379 (unsigned long)((tx_ring - adapter->tx_ring) /
3380 sizeof(struct igb_ring)),
3381 readl(adapter->hw.hw_addr + tx_ring->head),
3382 readl(adapter->hw.hw_addr + tx_ring->tail),
3383 tx_ring->next_to_use,
3384 tx_ring->next_to_clean,
3385 head,
3386 tx_ring->buffer_info[i].time_stamp,
3387 jiffies,
3388 tx_desc->upper.fields.status);
3389 netif_stop_queue(netdev);
3390 }
3391 }
3392 tx_ring->total_bytes += total_bytes;
3393 tx_ring->total_packets += total_packets;
3394 adapter->net_stats.tx_bytes += total_bytes;
3395 adapter->net_stats.tx_packets += total_packets;
3396 return retval;
3397 }
3398
3399
3400 /**
3401 * igb_receive_skb - helper function to handle rx indications
3402 * @adapter: board private structure
3403 * @status: descriptor status field as written by hardware
3404 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
3405 * @skb: pointer to sk_buff to be indicated to stack
3406 **/
3407 static void igb_receive_skb(struct igb_adapter *adapter, u8 status, u16 vlan,
3408 struct sk_buff *skb)
3409 {
3410 if (adapter->vlgrp && (status & E1000_RXD_STAT_VP))
3411 vlan_hwaccel_receive_skb(skb, adapter->vlgrp,
3412 le16_to_cpu(vlan) &
3413 E1000_RXD_SPC_VLAN_MASK);
3414 else
3415 netif_receive_skb(skb);
3416 }
3417
3418
3419 static inline void igb_rx_checksum_adv(struct igb_adapter *adapter,
3420 u32 status_err, struct sk_buff *skb)
3421 {
3422 skb->ip_summed = CHECKSUM_NONE;
3423
3424 /* Ignore Checksum bit is set or checksum is disabled through ethtool */
3425 if ((status_err & E1000_RXD_STAT_IXSM) || !adapter->rx_csum)
3426 return;
3427 /* TCP/UDP checksum error bit is set */
3428 if (status_err &
3429 (E1000_RXDEXT_STATERR_TCPE | E1000_RXDEXT_STATERR_IPE)) {
3430 /* let the stack verify checksum errors */
3431 adapter->hw_csum_err++;
3432 return;
3433 }
3434 /* It must be a TCP or UDP packet with a valid checksum */
3435 if (status_err & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS))
3436 skb->ip_summed = CHECKSUM_UNNECESSARY;
3437
3438 adapter->hw_csum_good++;
3439 }
3440
3441 static bool igb_clean_rx_irq_adv(struct igb_adapter *adapter,
3442 struct igb_ring *rx_ring,
3443 int *work_done, int budget)
3444 {
3445 struct net_device *netdev = adapter->netdev;
3446 struct pci_dev *pdev = adapter->pdev;
3447 union e1000_adv_rx_desc *rx_desc , *next_rxd;
3448 struct igb_buffer *buffer_info , *next_buffer;
3449 struct sk_buff *skb;
3450 unsigned int i, j;
3451 u32 length, hlen, staterr;
3452 bool cleaned = false;
3453 int cleaned_count = 0;
3454 unsigned int total_bytes = 0, total_packets = 0;
3455
3456 i = rx_ring->next_to_clean;
3457 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3458 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3459
3460 while (staterr & E1000_RXD_STAT_DD) {
3461 if (*work_done >= budget)
3462 break;
3463 (*work_done)++;
3464 buffer_info = &rx_ring->buffer_info[i];
3465
3466 /* HW will not DMA in data larger than the given buffer, even
3467 * if it parses the (NFS, of course) header to be larger. In
3468 * that case, it fills the header buffer and spills the rest
3469 * into the page.
3470 */
3471 hlen = le16_to_cpu((rx_desc->wb.lower.lo_dword.hdr_info &
3472 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT);
3473 if (hlen > adapter->rx_ps_hdr_size)
3474 hlen = adapter->rx_ps_hdr_size;
3475
3476 length = le16_to_cpu(rx_desc->wb.upper.length);
3477 cleaned = true;
3478 cleaned_count++;
3479
3480 if (rx_ring->pending_skb != NULL) {
3481 skb = rx_ring->pending_skb;
3482 rx_ring->pending_skb = NULL;
3483 j = rx_ring->pending_skb_page;
3484 } else {
3485 skb = buffer_info->skb;
3486 prefetch(skb->data - NET_IP_ALIGN);
3487 buffer_info->skb = NULL;
3488 if (hlen) {
3489 pci_unmap_single(pdev, buffer_info->dma,
3490 adapter->rx_ps_hdr_size +
3491 NET_IP_ALIGN,
3492 PCI_DMA_FROMDEVICE);
3493 skb_put(skb, hlen);
3494 } else {
3495 pci_unmap_single(pdev, buffer_info->dma,
3496 adapter->rx_buffer_len +
3497 NET_IP_ALIGN,
3498 PCI_DMA_FROMDEVICE);
3499 skb_put(skb, length);
3500 goto send_up;
3501 }
3502 j = 0;
3503 }
3504
3505 while (length) {
3506 pci_unmap_page(pdev, buffer_info->page_dma,
3507 PAGE_SIZE, PCI_DMA_FROMDEVICE);
3508 buffer_info->page_dma = 0;
3509 skb_fill_page_desc(skb, j, buffer_info->page,
3510 0, length);
3511 buffer_info->page = NULL;
3512
3513 skb->len += length;
3514 skb->data_len += length;
3515 skb->truesize += length;
3516 rx_desc->wb.upper.status_error = 0;
3517 if (staterr & E1000_RXD_STAT_EOP)
3518 break;
3519
3520 j++;
3521 cleaned_count++;
3522 i++;
3523 if (i == rx_ring->count)
3524 i = 0;
3525
3526 buffer_info = &rx_ring->buffer_info[i];
3527 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3528 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3529 length = le16_to_cpu(rx_desc->wb.upper.length);
3530 if (!(staterr & E1000_RXD_STAT_DD)) {
3531 rx_ring->pending_skb = skb;
3532 rx_ring->pending_skb_page = j;
3533 goto out;
3534 }
3535 }
3536 send_up:
3537 pskb_trim(skb, skb->len - 4);
3538 i++;
3539 if (i == rx_ring->count)
3540 i = 0;
3541 next_rxd = E1000_RX_DESC_ADV(*rx_ring, i);
3542 prefetch(next_rxd);
3543 next_buffer = &rx_ring->buffer_info[i];
3544
3545 if (staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) {
3546 dev_kfree_skb_irq(skb);
3547 goto next_desc;
3548 }
3549 rx_ring->no_itr_adjust |= (staterr & E1000_RXD_STAT_DYNINT);
3550
3551 total_bytes += skb->len;
3552 total_packets++;
3553
3554 igb_rx_checksum_adv(adapter, staterr, skb);
3555
3556 skb->protocol = eth_type_trans(skb, netdev);
3557
3558 igb_receive_skb(adapter, staterr, rx_desc->wb.upper.vlan, skb);
3559
3560 netdev->last_rx = jiffies;
3561
3562 next_desc:
3563 rx_desc->wb.upper.status_error = 0;
3564
3565 /* return some buffers to hardware, one at a time is too slow */
3566 if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
3567 igb_alloc_rx_buffers_adv(adapter, rx_ring,
3568 cleaned_count);
3569 cleaned_count = 0;
3570 }
3571
3572 /* use prefetched values */
3573 rx_desc = next_rxd;
3574 buffer_info = next_buffer;
3575
3576 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
3577 }
3578 out:
3579 rx_ring->next_to_clean = i;
3580 cleaned_count = IGB_DESC_UNUSED(rx_ring);
3581
3582 if (cleaned_count)
3583 igb_alloc_rx_buffers_adv(adapter, rx_ring, cleaned_count);
3584
3585 rx_ring->total_packets += total_packets;
3586 rx_ring->total_bytes += total_bytes;
3587 rx_ring->rx_stats.packets += total_packets;
3588 rx_ring->rx_stats.bytes += total_bytes;
3589 adapter->net_stats.rx_bytes += total_bytes;
3590 adapter->net_stats.rx_packets += total_packets;
3591 return cleaned;
3592 }
3593
3594
3595 /**
3596 * igb_alloc_rx_buffers_adv - Replace used receive buffers; packet split
3597 * @adapter: address of board private structure
3598 **/
3599 static void igb_alloc_rx_buffers_adv(struct igb_adapter *adapter,
3600 struct igb_ring *rx_ring,
3601 int cleaned_count)
3602 {
3603 struct net_device *netdev = adapter->netdev;
3604 struct pci_dev *pdev = adapter->pdev;
3605 union e1000_adv_rx_desc *rx_desc;
3606 struct igb_buffer *buffer_info;
3607 struct sk_buff *skb;
3608 unsigned int i;
3609
3610 i = rx_ring->next_to_use;
3611 buffer_info = &rx_ring->buffer_info[i];
3612
3613 while (cleaned_count--) {
3614 rx_desc = E1000_RX_DESC_ADV(*rx_ring, i);
3615
3616 if (adapter->rx_ps_hdr_size && !buffer_info->page) {
3617 buffer_info->page = alloc_page(GFP_ATOMIC);
3618 if (!buffer_info->page) {
3619 adapter->alloc_rx_buff_failed++;
3620 goto no_buffers;
3621 }
3622 buffer_info->page_dma =
3623 pci_map_page(pdev,
3624 buffer_info->page,
3625 0, PAGE_SIZE,
3626 PCI_DMA_FROMDEVICE);
3627 }
3628
3629 if (!buffer_info->skb) {
3630 int bufsz;
3631
3632 if (adapter->rx_ps_hdr_size)
3633 bufsz = adapter->rx_ps_hdr_size;
3634 else
3635 bufsz = adapter->rx_buffer_len;
3636 bufsz += NET_IP_ALIGN;
3637 skb = netdev_alloc_skb(netdev, bufsz);
3638
3639 if (!skb) {
3640 adapter->alloc_rx_buff_failed++;
3641 goto no_buffers;
3642 }
3643
3644 /* Make buffer alignment 2 beyond a 16 byte boundary
3645 * this will result in a 16 byte aligned IP header after
3646 * the 14 byte MAC header is removed
3647 */
3648 skb_reserve(skb, NET_IP_ALIGN);
3649
3650 buffer_info->skb = skb;
3651 buffer_info->dma = pci_map_single(pdev, skb->data,
3652 bufsz,
3653 PCI_DMA_FROMDEVICE);
3654
3655 }
3656 /* Refresh the desc even if buffer_addrs didn't change because
3657 * each write-back erases this info. */
3658 if (adapter->rx_ps_hdr_size) {
3659 rx_desc->read.pkt_addr =
3660 cpu_to_le64(buffer_info->page_dma);
3661 rx_desc->read.hdr_addr = cpu_to_le64(buffer_info->dma);
3662 } else {
3663 rx_desc->read.pkt_addr =
3664 cpu_to_le64(buffer_info->dma);
3665 rx_desc->read.hdr_addr = 0;
3666 }
3667
3668 i++;
3669 if (i == rx_ring->count)
3670 i = 0;
3671 buffer_info = &rx_ring->buffer_info[i];
3672 }
3673
3674 no_buffers:
3675 if (rx_ring->next_to_use != i) {
3676 rx_ring->next_to_use = i;
3677 if (i == 0)
3678 i = (rx_ring->count - 1);
3679 else
3680 i--;
3681
3682 /* Force memory writes to complete before letting h/w
3683 * know there are new descriptors to fetch. (Only
3684 * applicable for weak-ordered memory model archs,
3685 * such as IA-64). */
3686 wmb();
3687 writel(i, adapter->hw.hw_addr + rx_ring->tail);
3688 }
3689 }
3690
3691 /**
3692 * igb_mii_ioctl -
3693 * @netdev:
3694 * @ifreq:
3695 * @cmd:
3696 **/
3697 static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3698 {
3699 struct igb_adapter *adapter = netdev_priv(netdev);
3700 struct mii_ioctl_data *data = if_mii(ifr);
3701
3702 if (adapter->hw.phy.media_type != e1000_media_type_copper)
3703 return -EOPNOTSUPP;
3704
3705 switch (cmd) {
3706 case SIOCGMIIPHY:
3707 data->phy_id = adapter->hw.phy.addr;
3708 break;
3709 case SIOCGMIIREG:
3710 if (!capable(CAP_NET_ADMIN))
3711 return -EPERM;
3712 if (adapter->hw.phy.ops.read_phy_reg(&adapter->hw,
3713 data->reg_num
3714 & 0x1F, &data->val_out))
3715 return -EIO;
3716 break;
3717 case SIOCSMIIREG:
3718 default:
3719 return -EOPNOTSUPP;
3720 }
3721 return 0;
3722 }
3723
3724 /**
3725 * igb_ioctl -
3726 * @netdev:
3727 * @ifreq:
3728 * @cmd:
3729 **/
3730 static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
3731 {
3732 switch (cmd) {
3733 case SIOCGMIIPHY:
3734 case SIOCGMIIREG:
3735 case SIOCSMIIREG:
3736 return igb_mii_ioctl(netdev, ifr, cmd);
3737 default:
3738 return -EOPNOTSUPP;
3739 }
3740 }
3741
3742 static void igb_vlan_rx_register(struct net_device *netdev,
3743 struct vlan_group *grp)
3744 {
3745 struct igb_adapter *adapter = netdev_priv(netdev);
3746 struct e1000_hw *hw = &adapter->hw;
3747 u32 ctrl, rctl;
3748
3749 igb_irq_disable(adapter);
3750 adapter->vlgrp = grp;
3751
3752 if (grp) {
3753 /* enable VLAN tag insert/strip */
3754 ctrl = rd32(E1000_CTRL);
3755 ctrl |= E1000_CTRL_VME;
3756 wr32(E1000_CTRL, ctrl);
3757
3758 /* enable VLAN receive filtering */
3759 rctl = rd32(E1000_RCTL);
3760 rctl |= E1000_RCTL_VFE;
3761 rctl &= ~E1000_RCTL_CFIEN;
3762 wr32(E1000_RCTL, rctl);
3763 igb_update_mng_vlan(adapter);
3764 wr32(E1000_RLPML,
3765 adapter->max_frame_size + VLAN_TAG_SIZE);
3766 } else {
3767 /* disable VLAN tag insert/strip */
3768 ctrl = rd32(E1000_CTRL);
3769 ctrl &= ~E1000_CTRL_VME;
3770 wr32(E1000_CTRL, ctrl);
3771
3772 /* disable VLAN filtering */
3773 rctl = rd32(E1000_RCTL);
3774 rctl &= ~E1000_RCTL_VFE;
3775 wr32(E1000_RCTL, rctl);
3776 if (adapter->mng_vlan_id != (u16)IGB_MNG_VLAN_NONE) {
3777 igb_vlan_rx_kill_vid(netdev, adapter->mng_vlan_id);
3778 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
3779 }
3780 wr32(E1000_RLPML,
3781 adapter->max_frame_size);
3782 }
3783
3784 if (!test_bit(__IGB_DOWN, &adapter->state))
3785 igb_irq_enable(adapter);
3786 }
3787
3788 static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3789 {
3790 struct igb_adapter *adapter = netdev_priv(netdev);
3791 struct e1000_hw *hw = &adapter->hw;
3792 u32 vfta, index;
3793
3794 if ((adapter->hw.mng_cookie.status &
3795 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3796 (vid == adapter->mng_vlan_id))
3797 return;
3798 /* add VID to filter table */
3799 index = (vid >> 5) & 0x7F;
3800 vfta = array_rd32(E1000_VFTA, index);
3801 vfta |= (1 << (vid & 0x1F));
3802 igb_write_vfta(&adapter->hw, index, vfta);
3803 }
3804
3805 static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3806 {
3807 struct igb_adapter *adapter = netdev_priv(netdev);
3808 struct e1000_hw *hw = &adapter->hw;
3809 u32 vfta, index;
3810
3811 igb_irq_disable(adapter);
3812 vlan_group_set_device(adapter->vlgrp, vid, NULL);
3813
3814 if (!test_bit(__IGB_DOWN, &adapter->state))
3815 igb_irq_enable(adapter);
3816
3817 if ((adapter->hw.mng_cookie.status &
3818 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
3819 (vid == adapter->mng_vlan_id)) {
3820 /* release control to f/w */
3821 igb_release_hw_control(adapter);
3822 return;
3823 }
3824
3825 /* remove VID from filter table */
3826 index = (vid >> 5) & 0x7F;
3827 vfta = array_rd32(E1000_VFTA, index);
3828 vfta &= ~(1 << (vid & 0x1F));
3829 igb_write_vfta(&adapter->hw, index, vfta);
3830 }
3831
3832 static void igb_restore_vlan(struct igb_adapter *adapter)
3833 {
3834 igb_vlan_rx_register(adapter->netdev, adapter->vlgrp);
3835
3836 if (adapter->vlgrp) {
3837 u16 vid;
3838 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
3839 if (!vlan_group_get_device(adapter->vlgrp, vid))
3840 continue;
3841 igb_vlan_rx_add_vid(adapter->netdev, vid);
3842 }
3843 }
3844 }
3845
3846 int igb_set_spd_dplx(struct igb_adapter *adapter, u16 spddplx)
3847 {
3848 struct e1000_mac_info *mac = &adapter->hw.mac;
3849
3850 mac->autoneg = 0;
3851
3852 /* Fiber NICs only allow 1000 gbps Full duplex */
3853 if ((adapter->hw.phy.media_type == e1000_media_type_fiber) &&
3854 spddplx != (SPEED_1000 + DUPLEX_FULL)) {
3855 dev_err(&adapter->pdev->dev,
3856 "Unsupported Speed/Duplex configuration\n");
3857 return -EINVAL;
3858 }
3859
3860 switch (spddplx) {
3861 case SPEED_10 + DUPLEX_HALF:
3862 mac->forced_speed_duplex = ADVERTISE_10_HALF;
3863 break;
3864 case SPEED_10 + DUPLEX_FULL:
3865 mac->forced_speed_duplex = ADVERTISE_10_FULL;
3866 break;
3867 case SPEED_100 + DUPLEX_HALF:
3868 mac->forced_speed_duplex = ADVERTISE_100_HALF;
3869 break;
3870 case SPEED_100 + DUPLEX_FULL:
3871 mac->forced_speed_duplex = ADVERTISE_100_FULL;
3872 break;
3873 case SPEED_1000 + DUPLEX_FULL:
3874 mac->autoneg = 1;
3875 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
3876 break;
3877 case SPEED_1000 + DUPLEX_HALF: /* not supported */
3878 default:
3879 dev_err(&adapter->pdev->dev,
3880 "Unsupported Speed/Duplex configuration\n");
3881 return -EINVAL;
3882 }
3883 return 0;
3884 }
3885
3886
3887 static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
3888 {
3889 struct net_device *netdev = pci_get_drvdata(pdev);
3890 struct igb_adapter *adapter = netdev_priv(netdev);
3891 struct e1000_hw *hw = &adapter->hw;
3892 u32 ctrl, ctrl_ext, rctl, status;
3893 u32 wufc = adapter->wol;
3894 #ifdef CONFIG_PM
3895 int retval = 0;
3896 #endif
3897
3898 netif_device_detach(netdev);
3899
3900 if (netif_running(netdev)) {
3901 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
3902 igb_down(adapter);
3903 igb_free_irq(adapter);
3904 }
3905
3906 #ifdef CONFIG_PM
3907 retval = pci_save_state(pdev);
3908 if (retval)
3909 return retval;
3910 #endif
3911
3912 status = rd32(E1000_STATUS);
3913 if (status & E1000_STATUS_LU)
3914 wufc &= ~E1000_WUFC_LNKC;
3915
3916 if (wufc) {
3917 igb_setup_rctl(adapter);
3918 igb_set_multi(netdev);
3919
3920 /* turn on all-multi mode if wake on multicast is enabled */
3921 if (wufc & E1000_WUFC_MC) {
3922 rctl = rd32(E1000_RCTL);
3923 rctl |= E1000_RCTL_MPE;
3924 wr32(E1000_RCTL, rctl);
3925 }
3926
3927 ctrl = rd32(E1000_CTRL);
3928 /* advertise wake from D3Cold */
3929 #define E1000_CTRL_ADVD3WUC 0x00100000
3930 /* phy power management enable */
3931 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
3932 ctrl |= E1000_CTRL_ADVD3WUC;
3933 wr32(E1000_CTRL, ctrl);
3934
3935 if (adapter->hw.phy.media_type == e1000_media_type_fiber ||
3936 adapter->hw.phy.media_type ==
3937 e1000_media_type_internal_serdes) {
3938 /* keep the laser running in D3 */
3939 ctrl_ext = rd32(E1000_CTRL_EXT);
3940 ctrl_ext |= E1000_CTRL_EXT_SDP7_DATA;
3941 wr32(E1000_CTRL_EXT, ctrl_ext);
3942 }
3943
3944 /* Allow time for pending master requests to run */
3945 igb_disable_pcie_master(&adapter->hw);
3946
3947 wr32(E1000_WUC, E1000_WUC_PME_EN);
3948 wr32(E1000_WUFC, wufc);
3949 pci_enable_wake(pdev, PCI_D3hot, 1);
3950 pci_enable_wake(pdev, PCI_D3cold, 1);
3951 } else {
3952 wr32(E1000_WUC, 0);
3953 wr32(E1000_WUFC, 0);
3954 pci_enable_wake(pdev, PCI_D3hot, 0);
3955 pci_enable_wake(pdev, PCI_D3cold, 0);
3956 }
3957
3958 igb_release_manageability(adapter);
3959
3960 /* make sure adapter isn't asleep if manageability is enabled */
3961 if (adapter->en_mng_pt) {
3962 pci_enable_wake(pdev, PCI_D3hot, 1);
3963 pci_enable_wake(pdev, PCI_D3cold, 1);
3964 }
3965
3966 /* Release control of h/w to f/w. If f/w is AMT enabled, this
3967 * would have already happened in close and is redundant. */
3968 igb_release_hw_control(adapter);
3969
3970 pci_disable_device(pdev);
3971
3972 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3973
3974 return 0;
3975 }
3976
3977 #ifdef CONFIG_PM
3978 static int igb_resume(struct pci_dev *pdev)
3979 {
3980 struct net_device *netdev = pci_get_drvdata(pdev);
3981 struct igb_adapter *adapter = netdev_priv(netdev);
3982 struct e1000_hw *hw = &adapter->hw;
3983 u32 err;
3984
3985 pci_set_power_state(pdev, PCI_D0);
3986 pci_restore_state(pdev);
3987 err = pci_enable_device(pdev);
3988 if (err) {
3989 dev_err(&pdev->dev,
3990 "igb: Cannot enable PCI device from suspend\n");
3991 return err;
3992 }
3993 pci_set_master(pdev);
3994
3995 pci_enable_wake(pdev, PCI_D3hot, 0);
3996 pci_enable_wake(pdev, PCI_D3cold, 0);
3997
3998 if (netif_running(netdev)) {
3999 err = igb_request_irq(adapter);
4000 if (err)
4001 return err;
4002 }
4003
4004 /* e1000_power_up_phy(adapter); */
4005
4006 igb_reset(adapter);
4007 wr32(E1000_WUS, ~0);
4008
4009 igb_init_manageability(adapter);
4010
4011 if (netif_running(netdev))
4012 igb_up(adapter);
4013
4014 netif_device_attach(netdev);
4015
4016 /* let the f/w know that the h/w is now under the control of the
4017 * driver. */
4018 igb_get_hw_control(adapter);
4019
4020 return 0;
4021 }
4022 #endif
4023
4024 static void igb_shutdown(struct pci_dev *pdev)
4025 {
4026 igb_suspend(pdev, PMSG_SUSPEND);
4027 }
4028
4029 #ifdef CONFIG_NET_POLL_CONTROLLER
4030 /*
4031 * Polling 'interrupt' - used by things like netconsole to send skbs
4032 * without having to re-enable interrupts. It's not called while
4033 * the interrupt routine is executing.
4034 */
4035 static void igb_netpoll(struct net_device *netdev)
4036 {
4037 struct igb_adapter *adapter = netdev_priv(netdev);
4038 int i;
4039 int work_done = 0;
4040
4041 igb_irq_disable(adapter);
4042 for (i = 0; i < adapter->num_tx_queues; i++)
4043 igb_clean_tx_irq(adapter, &adapter->tx_ring[i]);
4044
4045 for (i = 0; i < adapter->num_rx_queues; i++)
4046 igb_clean_rx_irq_adv(adapter, &adapter->rx_ring[i],
4047 &work_done,
4048 adapter->rx_ring[i].napi.weight);
4049
4050 igb_irq_enable(adapter);
4051 }
4052 #endif /* CONFIG_NET_POLL_CONTROLLER */
4053
4054 /**
4055 * igb_io_error_detected - called when PCI error is detected
4056 * @pdev: Pointer to PCI device
4057 * @state: The current pci connection state
4058 *
4059 * This function is called after a PCI bus error affecting
4060 * this device has been detected.
4061 */
4062 static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
4063 pci_channel_state_t state)
4064 {
4065 struct net_device *netdev = pci_get_drvdata(pdev);
4066 struct igb_adapter *adapter = netdev_priv(netdev);
4067
4068 netif_device_detach(netdev);
4069
4070 if (netif_running(netdev))
4071 igb_down(adapter);
4072 pci_disable_device(pdev);
4073
4074 /* Request a slot slot reset. */
4075 return PCI_ERS_RESULT_NEED_RESET;
4076 }
4077
4078 /**
4079 * igb_io_slot_reset - called after the pci bus has been reset.
4080 * @pdev: Pointer to PCI device
4081 *
4082 * Restart the card from scratch, as if from a cold-boot. Implementation
4083 * resembles the first-half of the igb_resume routine.
4084 */
4085 static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
4086 {
4087 struct net_device *netdev = pci_get_drvdata(pdev);
4088 struct igb_adapter *adapter = netdev_priv(netdev);
4089 struct e1000_hw *hw = &adapter->hw;
4090
4091 if (pci_enable_device(pdev)) {
4092 dev_err(&pdev->dev,
4093 "Cannot re-enable PCI device after reset.\n");
4094 return PCI_ERS_RESULT_DISCONNECT;
4095 }
4096 pci_set_master(pdev);
4097
4098 pci_enable_wake(pdev, PCI_D3hot, 0);
4099 pci_enable_wake(pdev, PCI_D3cold, 0);
4100
4101 igb_reset(adapter);
4102 wr32(E1000_WUS, ~0);
4103
4104 return PCI_ERS_RESULT_RECOVERED;
4105 }
4106
4107 /**
4108 * igb_io_resume - called when traffic can start flowing again.
4109 * @pdev: Pointer to PCI device
4110 *
4111 * This callback is called when the error recovery driver tells us that
4112 * its OK to resume normal operation. Implementation resembles the
4113 * second-half of the igb_resume routine.
4114 */
4115 static void igb_io_resume(struct pci_dev *pdev)
4116 {
4117 struct net_device *netdev = pci_get_drvdata(pdev);
4118 struct igb_adapter *adapter = netdev_priv(netdev);
4119
4120 igb_init_manageability(adapter);
4121
4122 if (netif_running(netdev)) {
4123 if (igb_up(adapter)) {
4124 dev_err(&pdev->dev, "igb_up failed after reset\n");
4125 return;
4126 }
4127 }
4128
4129 netif_device_attach(netdev);
4130
4131 /* let the f/w know that the h/w is now under the control of the
4132 * driver. */
4133 igb_get_hw_control(adapter);
4134
4135 }
4136
4137 /* igb_main.c */
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