[SCSI] aic94xx: fix section mismatch
[linux-2.6/openmoko-kernel/knife-kernel.git] / arch / x86 / kvm / paging_tmpl.h
blob156fe10288ae330c6d9ac2d3e0b857a9d6c853b5
1 /*
2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * MMU support
9 * Copyright (C) 2006 Qumranet, Inc.
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
21 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
22 * so the code in this file is compiled twice, once per pte size.
25 #if PTTYPE == 64
26 #define pt_element_t u64
27 #define guest_walker guest_walker64
28 #define FNAME(name) paging##64_##name
29 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
30 #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
31 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
32 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
33 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
35 #ifdef CONFIG_X86_64
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
38 #else
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
41 #endif
42 #elif PTTYPE == 32
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
48 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
49 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
50 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
51 #define PT_LEVEL_BITS PT32_LEVEL_BITS
52 #define PT_MAX_FULL_LEVELS 2
53 #define CMPXCHG cmpxchg
54 #else
55 #error Invalid PTTYPE value
56 #endif
58 #define gpte_to_gfn FNAME(gpte_to_gfn)
59 #define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
62 * The guest_walker structure emulates the behavior of the hardware page
63 * table walker.
65 struct guest_walker {
66 int level;
67 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
68 pt_element_t ptes[PT_MAX_FULL_LEVELS];
69 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
70 unsigned pt_access;
71 unsigned pte_access;
72 gfn_t gfn;
73 u32 error_code;
76 static gfn_t gpte_to_gfn(pt_element_t gpte)
78 return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
81 static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
83 return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
86 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
87 gfn_t table_gfn, unsigned index,
88 pt_element_t orig_pte, pt_element_t new_pte)
90 pt_element_t ret;
91 pt_element_t *table;
92 struct page *page;
94 down_read(&current->mm->mmap_sem);
95 page = gfn_to_page(kvm, table_gfn);
96 up_read(&current->mm->mmap_sem);
98 table = kmap_atomic(page, KM_USER0);
100 ret = CMPXCHG(&table[index], orig_pte, new_pte);
102 kunmap_atomic(table, KM_USER0);
104 kvm_release_page_dirty(page);
106 return (ret != orig_pte);
109 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
111 unsigned access;
113 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
114 #if PTTYPE == 64
115 if (is_nx(vcpu))
116 access &= ~(gpte >> PT64_NX_SHIFT);
117 #endif
118 return access;
122 * Fetch a guest pte for a guest virtual address
124 static int FNAME(walk_addr)(struct guest_walker *walker,
125 struct kvm_vcpu *vcpu, gva_t addr,
126 int write_fault, int user_fault, int fetch_fault)
128 pt_element_t pte;
129 gfn_t table_gfn;
130 unsigned index, pt_access, pte_access;
131 gpa_t pte_gpa;
133 pgprintk("%s: addr %lx\n", __func__, addr);
134 walk:
135 walker->level = vcpu->arch.mmu.root_level;
136 pte = vcpu->arch.cr3;
137 #if PTTYPE == 64
138 if (!is_long_mode(vcpu)) {
139 pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
140 if (!is_present_pte(pte))
141 goto not_present;
142 --walker->level;
144 #endif
145 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
146 (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
148 pt_access = ACC_ALL;
150 for (;;) {
151 index = PT_INDEX(addr, walker->level);
153 table_gfn = gpte_to_gfn(pte);
154 pte_gpa = gfn_to_gpa(table_gfn);
155 pte_gpa += index * sizeof(pt_element_t);
156 walker->table_gfn[walker->level - 1] = table_gfn;
157 walker->pte_gpa[walker->level - 1] = pte_gpa;
158 pgprintk("%s: table_gfn[%d] %lx\n", __func__,
159 walker->level - 1, table_gfn);
161 kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
163 if (!is_present_pte(pte))
164 goto not_present;
166 if (write_fault && !is_writeble_pte(pte))
167 if (user_fault || is_write_protection(vcpu))
168 goto access_error;
170 if (user_fault && !(pte & PT_USER_MASK))
171 goto access_error;
173 #if PTTYPE == 64
174 if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
175 goto access_error;
176 #endif
178 if (!(pte & PT_ACCESSED_MASK)) {
179 mark_page_dirty(vcpu->kvm, table_gfn);
180 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
181 index, pte, pte|PT_ACCESSED_MASK))
182 goto walk;
183 pte |= PT_ACCESSED_MASK;
186 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
188 walker->ptes[walker->level - 1] = pte;
190 if (walker->level == PT_PAGE_TABLE_LEVEL) {
191 walker->gfn = gpte_to_gfn(pte);
192 break;
195 if (walker->level == PT_DIRECTORY_LEVEL
196 && (pte & PT_PAGE_SIZE_MASK)
197 && (PTTYPE == 64 || is_pse(vcpu))) {
198 walker->gfn = gpte_to_gfn_pde(pte);
199 walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
200 if (PTTYPE == 32 && is_cpuid_PSE36())
201 walker->gfn += pse36_gfn_delta(pte);
202 break;
205 pt_access = pte_access;
206 --walker->level;
209 if (write_fault && !is_dirty_pte(pte)) {
210 bool ret;
212 mark_page_dirty(vcpu->kvm, table_gfn);
213 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
214 pte|PT_DIRTY_MASK);
215 if (ret)
216 goto walk;
217 pte |= PT_DIRTY_MASK;
218 kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
219 walker->ptes[walker->level - 1] = pte;
222 walker->pt_access = pt_access;
223 walker->pte_access = pte_access;
224 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
225 __func__, (u64)pte, pt_access, pte_access);
226 return 1;
228 not_present:
229 walker->error_code = 0;
230 goto err;
232 access_error:
233 walker->error_code = PFERR_PRESENT_MASK;
235 err:
236 if (write_fault)
237 walker->error_code |= PFERR_WRITE_MASK;
238 if (user_fault)
239 walker->error_code |= PFERR_USER_MASK;
240 if (fetch_fault)
241 walker->error_code |= PFERR_FETCH_MASK;
242 return 0;
245 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
246 u64 *spte, const void *pte)
248 pt_element_t gpte;
249 unsigned pte_access;
250 pfn_t pfn;
251 int largepage = vcpu->arch.update_pte.largepage;
253 gpte = *(const pt_element_t *)pte;
254 if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
255 if (!is_present_pte(gpte))
256 set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
257 return;
259 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
260 pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
261 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
262 return;
263 pfn = vcpu->arch.update_pte.pfn;
264 if (is_error_pfn(pfn))
265 return;
266 kvm_get_pfn(pfn);
267 mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
268 gpte & PT_DIRTY_MASK, NULL, largepage, gpte_to_gfn(gpte),
269 pfn, true);
273 * Fetch a shadow pte for a specific level in the paging hierarchy.
275 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
276 struct guest_walker *walker,
277 int user_fault, int write_fault, int largepage,
278 int *ptwrite, pfn_t pfn)
280 hpa_t shadow_addr;
281 int level;
282 u64 *shadow_ent;
283 unsigned access = walker->pt_access;
285 if (!is_present_pte(walker->ptes[walker->level - 1]))
286 return NULL;
288 shadow_addr = vcpu->arch.mmu.root_hpa;
289 level = vcpu->arch.mmu.shadow_root_level;
290 if (level == PT32E_ROOT_LEVEL) {
291 shadow_addr = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
292 shadow_addr &= PT64_BASE_ADDR_MASK;
293 --level;
296 for (; ; level--) {
297 u32 index = SHADOW_PT_INDEX(addr, level);
298 struct kvm_mmu_page *shadow_page;
299 u64 shadow_pte;
300 int metaphysical;
301 gfn_t table_gfn;
303 shadow_ent = ((u64 *)__va(shadow_addr)) + index;
304 if (level == PT_PAGE_TABLE_LEVEL)
305 break;
307 if (largepage && level == PT_DIRECTORY_LEVEL)
308 break;
310 if (is_shadow_present_pte(*shadow_ent)
311 && !is_large_pte(*shadow_ent)) {
312 shadow_addr = *shadow_ent & PT64_BASE_ADDR_MASK;
313 continue;
316 if (is_large_pte(*shadow_ent))
317 rmap_remove(vcpu->kvm, shadow_ent);
319 if (level - 1 == PT_PAGE_TABLE_LEVEL
320 && walker->level == PT_DIRECTORY_LEVEL) {
321 metaphysical = 1;
322 if (!is_dirty_pte(walker->ptes[level - 1]))
323 access &= ~ACC_WRITE_MASK;
324 table_gfn = gpte_to_gfn(walker->ptes[level - 1]);
325 } else {
326 metaphysical = 0;
327 table_gfn = walker->table_gfn[level - 2];
329 shadow_page = kvm_mmu_get_page(vcpu, table_gfn, addr, level-1,
330 metaphysical, access,
331 shadow_ent);
332 if (!metaphysical) {
333 int r;
334 pt_element_t curr_pte;
335 r = kvm_read_guest_atomic(vcpu->kvm,
336 walker->pte_gpa[level - 2],
337 &curr_pte, sizeof(curr_pte));
338 if (r || curr_pte != walker->ptes[level - 2]) {
339 kvm_release_pfn_clean(pfn);
340 return NULL;
343 shadow_addr = __pa(shadow_page->spt);
344 shadow_pte = shadow_addr | PT_PRESENT_MASK | PT_ACCESSED_MASK
345 | PT_WRITABLE_MASK | PT_USER_MASK;
346 *shadow_ent = shadow_pte;
349 mmu_set_spte(vcpu, shadow_ent, access, walker->pte_access & access,
350 user_fault, write_fault,
351 walker->ptes[walker->level-1] & PT_DIRTY_MASK,
352 ptwrite, largepage, walker->gfn, pfn, false);
354 return shadow_ent;
358 * Page fault handler. There are several causes for a page fault:
359 * - there is no shadow pte for the guest pte
360 * - write access through a shadow pte marked read only so that we can set
361 * the dirty bit
362 * - write access to a shadow pte marked read only so we can update the page
363 * dirty bitmap, when userspace requests it
364 * - mmio access; in this case we will never install a present shadow pte
365 * - normal guest page fault due to the guest pte marked not present, not
366 * writable, or not executable
368 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
369 * a negative value on error.
371 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
372 u32 error_code)
374 int write_fault = error_code & PFERR_WRITE_MASK;
375 int user_fault = error_code & PFERR_USER_MASK;
376 int fetch_fault = error_code & PFERR_FETCH_MASK;
377 struct guest_walker walker;
378 u64 *shadow_pte;
379 int write_pt = 0;
380 int r;
381 pfn_t pfn;
382 int largepage = 0;
384 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
385 kvm_mmu_audit(vcpu, "pre page fault");
387 r = mmu_topup_memory_caches(vcpu);
388 if (r)
389 return r;
392 * Look up the shadow pte for the faulting address.
394 r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
395 fetch_fault);
398 * The page is not mapped by the guest. Let the guest handle it.
400 if (!r) {
401 pgprintk("%s: guest page fault\n", __func__);
402 inject_page_fault(vcpu, addr, walker.error_code);
403 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
404 return 0;
407 down_read(&current->mm->mmap_sem);
408 if (walker.level == PT_DIRECTORY_LEVEL) {
409 gfn_t large_gfn;
410 large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
411 if (is_largepage_backed(vcpu, large_gfn)) {
412 walker.gfn = large_gfn;
413 largepage = 1;
416 pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
417 up_read(&current->mm->mmap_sem);
419 /* mmio */
420 if (is_error_pfn(pfn)) {
421 pgprintk("gfn %x is mmio\n", walker.gfn);
422 kvm_release_pfn_clean(pfn);
423 return 1;
426 spin_lock(&vcpu->kvm->mmu_lock);
427 kvm_mmu_free_some_pages(vcpu);
428 shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
429 largepage, &write_pt, pfn);
431 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
432 shadow_pte, *shadow_pte, write_pt);
434 if (!write_pt)
435 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
437 ++vcpu->stat.pf_fixed;
438 kvm_mmu_audit(vcpu, "post page fault (fixed)");
439 spin_unlock(&vcpu->kvm->mmu_lock);
441 return write_pt;
444 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
446 struct guest_walker walker;
447 gpa_t gpa = UNMAPPED_GVA;
448 int r;
450 r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
452 if (r) {
453 gpa = gfn_to_gpa(walker.gfn);
454 gpa |= vaddr & ~PAGE_MASK;
457 return gpa;
460 static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
461 struct kvm_mmu_page *sp)
463 int i, offset = 0, r = 0;
464 pt_element_t pt;
466 if (sp->role.metaphysical
467 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
468 nonpaging_prefetch_page(vcpu, sp);
469 return;
472 if (PTTYPE == 32)
473 offset = sp->role.quadrant << PT64_LEVEL_BITS;
475 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
476 gpa_t pte_gpa = gfn_to_gpa(sp->gfn);
477 pte_gpa += (i+offset) * sizeof(pt_element_t);
479 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &pt,
480 sizeof(pt_element_t));
481 if (r || is_present_pte(pt))
482 sp->spt[i] = shadow_trap_nonpresent_pte;
483 else
484 sp->spt[i] = shadow_notrap_nonpresent_pte;
488 #undef pt_element_t
489 #undef guest_walker
490 #undef FNAME
491 #undef PT_BASE_ADDR_MASK
492 #undef PT_INDEX
493 #undef SHADOW_PT_INDEX
494 #undef PT_LEVEL_MASK
495 #undef PT_DIR_BASE_ADDR_MASK
496 #undef PT_LEVEL_BITS
497 #undef PT_MAX_FULL_LEVELS
498 #undef gpte_to_gfn
499 #undef gpte_to_gfn_pde
500 #undef CMPXCHG