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[SCSI] aic94xx: fix section mismatch
[linux-2.6/openmoko-kernel/knife-kernel.git] / arch / x86 / kvm / svm.c
blob89e0be2c10d0ee02153fd6f72df1ebd6e31f6e7b
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "kvm_svm.h"
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/vmalloc.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27
28 #include <asm/desc.h>
29
30 MODULE_AUTHOR("Qumranet");
31 MODULE_LICENSE("GPL");
32
33 #define IOPM_ALLOC_ORDER 2
34 #define MSRPM_ALLOC_ORDER 1
35
36 #define DB_VECTOR 1
37 #define UD_VECTOR 6
38 #define GP_VECTOR 13
39
40 #define DR7_GD_MASK (1 << 13)
41 #define DR6_BD_MASK (1 << 13)
42
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
45
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_DEATURE_SVML (1 << 2)
49
50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
51
52 /* enable NPT for AMD64 and X86 with PAE */
53 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
54 static bool npt_enabled = true;
55 #else
56 static bool npt_enabled = false;
57 #endif
58 static int npt = 1;
59
60 module_param(npt, int, S_IRUGO);
61
62 static void kvm_reput_irq(struct vcpu_svm *svm);
63
64 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
65 {
66 return container_of(vcpu, struct vcpu_svm, vcpu);
67 }
68
69 static unsigned long iopm_base;
70
71 struct kvm_ldttss_desc {
72 u16 limit0;
73 u16 base0;
74 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
75 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
76 u32 base3;
77 u32 zero1;
78 } __attribute__((packed));
79
80 struct svm_cpu_data {
81 int cpu;
82
83 u64 asid_generation;
84 u32 max_asid;
85 u32 next_asid;
86 struct kvm_ldttss_desc *tss_desc;
87
88 struct page *save_area;
89 };
90
91 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
92 static uint32_t svm_features;
93
94 struct svm_init_data {
95 int cpu;
96 int r;
97 };
98
99 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
100
101 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
102 #define MSRS_RANGE_SIZE 2048
103 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
104
105 #define MAX_INST_SIZE 15
106
107 static inline u32 svm_has(u32 feat)
108 {
109 return svm_features & feat;
110 }
111
112 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
113 {
114 int word_index = __ffs(vcpu->arch.irq_summary);
115 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
116 int irq = word_index * BITS_PER_LONG + bit_index;
117
118 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
119 if (!vcpu->arch.irq_pending[word_index])
120 clear_bit(word_index, &vcpu->arch.irq_summary);
121 return irq;
122 }
123
124 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
125 {
126 set_bit(irq, vcpu->arch.irq_pending);
127 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
128 }
129
130 static inline void clgi(void)
131 {
132 asm volatile (SVM_CLGI);
133 }
134
135 static inline void stgi(void)
136 {
137 asm volatile (SVM_STGI);
138 }
139
140 static inline void invlpga(unsigned long addr, u32 asid)
141 {
142 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
143 }
144
145 static inline unsigned long kvm_read_cr2(void)
146 {
147 unsigned long cr2;
148
149 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
150 return cr2;
151 }
152
153 static inline void kvm_write_cr2(unsigned long val)
154 {
155 asm volatile ("mov %0, %%cr2" :: "r" (val));
156 }
157
158 static inline unsigned long read_dr6(void)
159 {
160 unsigned long dr6;
161
162 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
163 return dr6;
164 }
165
166 static inline void write_dr6(unsigned long val)
167 {
168 asm volatile ("mov %0, %%dr6" :: "r" (val));
169 }
170
171 static inline unsigned long read_dr7(void)
172 {
173 unsigned long dr7;
174
175 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
176 return dr7;
177 }
178
179 static inline void write_dr7(unsigned long val)
180 {
181 asm volatile ("mov %0, %%dr7" :: "r" (val));
182 }
183
184 static inline void force_new_asid(struct kvm_vcpu *vcpu)
185 {
186 to_svm(vcpu)->asid_generation--;
187 }
188
189 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
190 {
191 force_new_asid(vcpu);
192 }
193
194 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
195 {
196 if (!npt_enabled && !(efer & EFER_LMA))
197 efer &= ~EFER_LME;
198
199 to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
200 vcpu->arch.shadow_efer = efer;
201 }
202
203 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
204 bool has_error_code, u32 error_code)
205 {
206 struct vcpu_svm *svm = to_svm(vcpu);
207
208 svm->vmcb->control.event_inj = nr
209 | SVM_EVTINJ_VALID
210 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
211 | SVM_EVTINJ_TYPE_EXEPT;
212 svm->vmcb->control.event_inj_err = error_code;
213 }
214
215 static bool svm_exception_injected(struct kvm_vcpu *vcpu)
216 {
217 struct vcpu_svm *svm = to_svm(vcpu);
218
219 return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
220 }
221
222 static int is_external_interrupt(u32 info)
223 {
224 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
225 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
226 }
227
228 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
229 {
230 struct vcpu_svm *svm = to_svm(vcpu);
231
232 if (!svm->next_rip) {
233 printk(KERN_DEBUG "%s: NOP\n", __func__);
234 return;
235 }
236 if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
237 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
238 __func__,
239 svm->vmcb->save.rip,
240 svm->next_rip);
241
242 vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
243 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
244
245 vcpu->arch.interrupt_window_open = 1;
246 }
247
248 static int has_svm(void)
249 {
250 uint32_t eax, ebx, ecx, edx;
251
252 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
253 printk(KERN_INFO "has_svm: not amd\n");
254 return 0;
255 }
256
257 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
258 if (eax < SVM_CPUID_FUNC) {
259 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
260 return 0;
261 }
262
263 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
264 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
265 printk(KERN_DEBUG "has_svm: svm not available\n");
266 return 0;
267 }
268 return 1;
269 }
270
271 static void svm_hardware_disable(void *garbage)
272 {
273 struct svm_cpu_data *svm_data
274 = per_cpu(svm_data, raw_smp_processor_id());
275
276 if (svm_data) {
277 uint64_t efer;
278
279 wrmsrl(MSR_VM_HSAVE_PA, 0);
280 rdmsrl(MSR_EFER, efer);
281 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
282 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
283 __free_page(svm_data->save_area);
284 kfree(svm_data);
285 }
286 }
287
288 static void svm_hardware_enable(void *garbage)
289 {
290
291 struct svm_cpu_data *svm_data;
292 uint64_t efer;
293 struct desc_ptr gdt_descr;
294 struct desc_struct *gdt;
295 int me = raw_smp_processor_id();
296
297 if (!has_svm()) {
298 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
299 return;
300 }
301 svm_data = per_cpu(svm_data, me);
302
303 if (!svm_data) {
304 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
305 me);
306 return;
307 }
308
309 svm_data->asid_generation = 1;
310 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
311 svm_data->next_asid = svm_data->max_asid + 1;
312
313 asm volatile ("sgdt %0" : "=m"(gdt_descr));
314 gdt = (struct desc_struct *)gdt_descr.address;
315 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
316
317 rdmsrl(MSR_EFER, efer);
318 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
319
320 wrmsrl(MSR_VM_HSAVE_PA,
321 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
322 }
323
324 static int svm_cpu_init(int cpu)
325 {
326 struct svm_cpu_data *svm_data;
327 int r;
328
329 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
330 if (!svm_data)
331 return -ENOMEM;
332 svm_data->cpu = cpu;
333 svm_data->save_area = alloc_page(GFP_KERNEL);
334 r = -ENOMEM;
335 if (!svm_data->save_area)
336 goto err_1;
337
338 per_cpu(svm_data, cpu) = svm_data;
339
340 return 0;
341
342 err_1:
343 kfree(svm_data);
344 return r;
345
346 }
347
348 static void set_msr_interception(u32 *msrpm, unsigned msr,
349 int read, int write)
350 {
351 int i;
352
353 for (i = 0; i < NUM_MSR_MAPS; i++) {
354 if (msr >= msrpm_ranges[i] &&
355 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
356 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
357 msrpm_ranges[i]) * 2;
358
359 u32 *base = msrpm + (msr_offset / 32);
360 u32 msr_shift = msr_offset % 32;
361 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
362 *base = (*base & ~(0x3 << msr_shift)) |
363 (mask << msr_shift);
364 return;
365 }
366 }
367 BUG();
368 }
369
370 static void svm_vcpu_init_msrpm(u32 *msrpm)
371 {
372 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
373
374 #ifdef CONFIG_X86_64
375 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
376 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
377 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
378 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
379 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
380 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
381 #endif
382 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
383 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
384 set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
385 set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
386 }
387
388 static void svm_enable_lbrv(struct vcpu_svm *svm)
389 {
390 u32 *msrpm = svm->msrpm;
391
392 svm->vmcb->control.lbr_ctl = 1;
393 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
394 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
395 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
396 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
397 }
398
399 static void svm_disable_lbrv(struct vcpu_svm *svm)
400 {
401 u32 *msrpm = svm->msrpm;
402
403 svm->vmcb->control.lbr_ctl = 0;
404 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
405 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
406 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
407 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
408 }
409
410 static __init int svm_hardware_setup(void)
411 {
412 int cpu;
413 struct page *iopm_pages;
414 void *iopm_va;
415 int r;
416
417 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
418
419 if (!iopm_pages)
420 return -ENOMEM;
421
422 iopm_va = page_address(iopm_pages);
423 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
424 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
425 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
426
427 if (boot_cpu_has(X86_FEATURE_NX))
428 kvm_enable_efer_bits(EFER_NX);
429
430 for_each_online_cpu(cpu) {
431 r = svm_cpu_init(cpu);
432 if (r)
433 goto err;
434 }
435
436 svm_features = cpuid_edx(SVM_CPUID_FUNC);
437
438 if (!svm_has(SVM_FEATURE_NPT))
439 npt_enabled = false;
440
441 if (npt_enabled && !npt) {
442 printk(KERN_INFO "kvm: Nested Paging disabled\n");
443 npt_enabled = false;
444 }
445
446 if (npt_enabled) {
447 printk(KERN_INFO "kvm: Nested Paging enabled\n");
448 kvm_enable_tdp();
449 }
450
451 return 0;
452
453 err:
454 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
455 iopm_base = 0;
456 return r;
457 }
458
459 static __exit void svm_hardware_unsetup(void)
460 {
461 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
462 iopm_base = 0;
463 }
464
465 static void init_seg(struct vmcb_seg *seg)
466 {
467 seg->selector = 0;
468 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
469 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
470 seg->limit = 0xffff;
471 seg->base = 0;
472 }
473
474 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
475 {
476 seg->selector = 0;
477 seg->attrib = SVM_SELECTOR_P_MASK | type;
478 seg->limit = 0xffff;
479 seg->base = 0;
480 }
481
482 static void init_vmcb(struct vcpu_svm *svm)
483 {
484 struct vmcb_control_area *control = &svm->vmcb->control;
485 struct vmcb_save_area *save = &svm->vmcb->save;
486
487 control->intercept_cr_read = INTERCEPT_CR0_MASK |
488 INTERCEPT_CR3_MASK |
489 INTERCEPT_CR4_MASK;
490
491 control->intercept_cr_write = INTERCEPT_CR0_MASK |
492 INTERCEPT_CR3_MASK |
493 INTERCEPT_CR4_MASK |
494 INTERCEPT_CR8_MASK;
495
496 control->intercept_dr_read = INTERCEPT_DR0_MASK |
497 INTERCEPT_DR1_MASK |
498 INTERCEPT_DR2_MASK |
499 INTERCEPT_DR3_MASK;
500
501 control->intercept_dr_write = INTERCEPT_DR0_MASK |
502 INTERCEPT_DR1_MASK |
503 INTERCEPT_DR2_MASK |
504 INTERCEPT_DR3_MASK |
505 INTERCEPT_DR5_MASK |
506 INTERCEPT_DR7_MASK;
507
508 control->intercept_exceptions = (1 << PF_VECTOR) |
509 (1 << UD_VECTOR) |
510 (1 << MC_VECTOR);
511
512
513 control->intercept = (1ULL << INTERCEPT_INTR) |
514 (1ULL << INTERCEPT_NMI) |
515 (1ULL << INTERCEPT_SMI) |
516 (1ULL << INTERCEPT_CPUID) |
517 (1ULL << INTERCEPT_INVD) |
518 (1ULL << INTERCEPT_HLT) |
519 (1ULL << INTERCEPT_INVLPGA) |
520 (1ULL << INTERCEPT_IOIO_PROT) |
521 (1ULL << INTERCEPT_MSR_PROT) |
522 (1ULL << INTERCEPT_TASK_SWITCH) |
523 (1ULL << INTERCEPT_SHUTDOWN) |
524 (1ULL << INTERCEPT_VMRUN) |
525 (1ULL << INTERCEPT_VMMCALL) |
526 (1ULL << INTERCEPT_VMLOAD) |
527 (1ULL << INTERCEPT_VMSAVE) |
528 (1ULL << INTERCEPT_STGI) |
529 (1ULL << INTERCEPT_CLGI) |
530 (1ULL << INTERCEPT_SKINIT) |
531 (1ULL << INTERCEPT_WBINVD) |
532 (1ULL << INTERCEPT_MONITOR) |
533 (1ULL << INTERCEPT_MWAIT);
534
535 control->iopm_base_pa = iopm_base;
536 control->msrpm_base_pa = __pa(svm->msrpm);
537 control->tsc_offset = 0;
538 control->int_ctl = V_INTR_MASKING_MASK;
539
540 init_seg(&save->es);
541 init_seg(&save->ss);
542 init_seg(&save->ds);
543 init_seg(&save->fs);
544 init_seg(&save->gs);
545
546 save->cs.selector = 0xf000;
547 /* Executable/Readable Code Segment */
548 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
549 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
550 save->cs.limit = 0xffff;
551 /*
552 * cs.base should really be 0xffff0000, but vmx can't handle that, so
553 * be consistent with it.
554 *
555 * Replace when we have real mode working for vmx.
556 */
557 save->cs.base = 0xf0000;
558
559 save->gdtr.limit = 0xffff;
560 save->idtr.limit = 0xffff;
561
562 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
563 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
564
565 save->efer = MSR_EFER_SVME_MASK;
566 save->dr6 = 0xffff0ff0;
567 save->dr7 = 0x400;
568 save->rflags = 2;
569 save->rip = 0x0000fff0;
570
571 /*
572 * cr0 val on cpu init should be 0x60000010, we enable cpu
573 * cache by default. the orderly way is to enable cache in bios.
574 */
575 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
576 save->cr4 = X86_CR4_PAE;
577 /* rdx = ?? */
578
579 if (npt_enabled) {
580 /* Setup VMCB for Nested Paging */
581 control->nested_ctl = 1;
582 control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH);
583 control->intercept_exceptions &= ~(1 << PF_VECTOR);
584 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
585 INTERCEPT_CR3_MASK);
586 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
587 INTERCEPT_CR3_MASK);
588 save->g_pat = 0x0007040600070406ULL;
589 /* enable caching because the QEMU Bios doesn't enable it */
590 save->cr0 = X86_CR0_ET;
591 save->cr3 = 0;
592 save->cr4 = 0;
593 }
594 force_new_asid(&svm->vcpu);
595 }
596
597 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
598 {
599 struct vcpu_svm *svm = to_svm(vcpu);
600
601 init_vmcb(svm);
602
603 if (vcpu->vcpu_id != 0) {
604 svm->vmcb->save.rip = 0;
605 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
606 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
607 }
608
609 return 0;
610 }
611
612 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
613 {
614 struct vcpu_svm *svm;
615 struct page *page;
616 struct page *msrpm_pages;
617 int err;
618
619 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
620 if (!svm) {
621 err = -ENOMEM;
622 goto out;
623 }
624
625 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
626 if (err)
627 goto free_svm;
628
629 page = alloc_page(GFP_KERNEL);
630 if (!page) {
631 err = -ENOMEM;
632 goto uninit;
633 }
634
635 err = -ENOMEM;
636 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
637 if (!msrpm_pages)
638 goto uninit;
639 svm->msrpm = page_address(msrpm_pages);
640 svm_vcpu_init_msrpm(svm->msrpm);
641
642 svm->vmcb = page_address(page);
643 clear_page(svm->vmcb);
644 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
645 svm->asid_generation = 0;
646 memset(svm->db_regs, 0, sizeof(svm->db_regs));
647 init_vmcb(svm);
648
649 fx_init(&svm->vcpu);
650 svm->vcpu.fpu_active = 1;
651 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
652 if (svm->vcpu.vcpu_id == 0)
653 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
654
655 return &svm->vcpu;
656
657 uninit:
658 kvm_vcpu_uninit(&svm->vcpu);
659 free_svm:
660 kmem_cache_free(kvm_vcpu_cache, svm);
661 out:
662 return ERR_PTR(err);
663 }
664
665 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
666 {
667 struct vcpu_svm *svm = to_svm(vcpu);
668
669 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
670 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
671 kvm_vcpu_uninit(vcpu);
672 kmem_cache_free(kvm_vcpu_cache, svm);
673 }
674
675 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
676 {
677 struct vcpu_svm *svm = to_svm(vcpu);
678 int i;
679
680 if (unlikely(cpu != vcpu->cpu)) {
681 u64 tsc_this, delta;
682
683 /*
684 * Make sure that the guest sees a monotonically
685 * increasing TSC.
686 */
687 rdtscll(tsc_this);
688 delta = vcpu->arch.host_tsc - tsc_this;
689 svm->vmcb->control.tsc_offset += delta;
690 vcpu->cpu = cpu;
691 kvm_migrate_apic_timer(vcpu);
692 }
693
694 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
695 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
696 }
697
698 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
699 {
700 struct vcpu_svm *svm = to_svm(vcpu);
701 int i;
702
703 ++vcpu->stat.host_state_reload;
704 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
705 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
706
707 rdtscll(vcpu->arch.host_tsc);
708 }
709
710 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
711 {
712 }
713
714 static void svm_cache_regs(struct kvm_vcpu *vcpu)
715 {
716 struct vcpu_svm *svm = to_svm(vcpu);
717
718 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
719 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
720 vcpu->arch.rip = svm->vmcb->save.rip;
721 }
722
723 static void svm_decache_regs(struct kvm_vcpu *vcpu)
724 {
725 struct vcpu_svm *svm = to_svm(vcpu);
726 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
727 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
728 svm->vmcb->save.rip = vcpu->arch.rip;
729 }
730
731 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
732 {
733 return to_svm(vcpu)->vmcb->save.rflags;
734 }
735
736 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
737 {
738 to_svm(vcpu)->vmcb->save.rflags = rflags;
739 }
740
741 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
742 {
743 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
744
745 switch (seg) {
746 case VCPU_SREG_CS: return &save->cs;
747 case VCPU_SREG_DS: return &save->ds;
748 case VCPU_SREG_ES: return &save->es;
749 case VCPU_SREG_FS: return &save->fs;
750 case VCPU_SREG_GS: return &save->gs;
751 case VCPU_SREG_SS: return &save->ss;
752 case VCPU_SREG_TR: return &save->tr;
753 case VCPU_SREG_LDTR: return &save->ldtr;
754 }
755 BUG();
756 return NULL;
757 }
758
759 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
760 {
761 struct vmcb_seg *s = svm_seg(vcpu, seg);
762
763 return s->base;
764 }
765
766 static void svm_get_segment(struct kvm_vcpu *vcpu,
767 struct kvm_segment *var, int seg)
768 {
769 struct vmcb_seg *s = svm_seg(vcpu, seg);
770
771 var->base = s->base;
772 var->limit = s->limit;
773 var->selector = s->selector;
774 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
775 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
776 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
777 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
778 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
779 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
780 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
781 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
782 var->unusable = !var->present;
783 }
784
785 static int svm_get_cpl(struct kvm_vcpu *vcpu)
786 {
787 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
788
789 return save->cpl;
790 }
791
792 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
793 {
794 struct vcpu_svm *svm = to_svm(vcpu);
795
796 dt->limit = svm->vmcb->save.idtr.limit;
797 dt->base = svm->vmcb->save.idtr.base;
798 }
799
800 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
801 {
802 struct vcpu_svm *svm = to_svm(vcpu);
803
804 svm->vmcb->save.idtr.limit = dt->limit;
805 svm->vmcb->save.idtr.base = dt->base ;
806 }
807
808 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
809 {
810 struct vcpu_svm *svm = to_svm(vcpu);
811
812 dt->limit = svm->vmcb->save.gdtr.limit;
813 dt->base = svm->vmcb->save.gdtr.base;
814 }
815
816 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
817 {
818 struct vcpu_svm *svm = to_svm(vcpu);
819
820 svm->vmcb->save.gdtr.limit = dt->limit;
821 svm->vmcb->save.gdtr.base = dt->base ;
822 }
823
824 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
825 {
826 }
827
828 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
829 {
830 struct vcpu_svm *svm = to_svm(vcpu);
831
832 #ifdef CONFIG_X86_64
833 if (vcpu->arch.shadow_efer & EFER_LME) {
834 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
835 vcpu->arch.shadow_efer |= EFER_LMA;
836 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
837 }
838
839 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
840 vcpu->arch.shadow_efer &= ~EFER_LMA;
841 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
842 }
843 }
844 #endif
845 if (npt_enabled)
846 goto set;
847
848 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
849 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
850 vcpu->fpu_active = 1;
851 }
852
853 vcpu->arch.cr0 = cr0;
854 cr0 |= X86_CR0_PG | X86_CR0_WP;
855 if (!vcpu->fpu_active) {
856 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
857 cr0 |= X86_CR0_TS;
858 }
859 set:
860 /*
861 * re-enable caching here because the QEMU bios
862 * does not do it - this results in some delay at
863 * reboot
864 */
865 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
866 svm->vmcb->save.cr0 = cr0;
867 }
868
869 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
870 {
871 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
872
873 vcpu->arch.cr4 = cr4;
874 if (!npt_enabled)
875 cr4 |= X86_CR4_PAE;
876 cr4 |= host_cr4_mce;
877 to_svm(vcpu)->vmcb->save.cr4 = cr4;
878 }
879
880 static void svm_set_segment(struct kvm_vcpu *vcpu,
881 struct kvm_segment *var, int seg)
882 {
883 struct vcpu_svm *svm = to_svm(vcpu);
884 struct vmcb_seg *s = svm_seg(vcpu, seg);
885
886 s->base = var->base;
887 s->limit = var->limit;
888 s->selector = var->selector;
889 if (var->unusable)
890 s->attrib = 0;
891 else {
892 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
893 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
894 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
895 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
896 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
897 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
898 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
899 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
900 }
901 if (seg == VCPU_SREG_CS)
902 svm->vmcb->save.cpl
903 = (svm->vmcb->save.cs.attrib
904 >> SVM_SELECTOR_DPL_SHIFT) & 3;
905
906 }
907
908 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
909 {
910 return -EOPNOTSUPP;
911 }
912
913 static int svm_get_irq(struct kvm_vcpu *vcpu)
914 {
915 struct vcpu_svm *svm = to_svm(vcpu);
916 u32 exit_int_info = svm->vmcb->control.exit_int_info;
917
918 if (is_external_interrupt(exit_int_info))
919 return exit_int_info & SVM_EVTINJ_VEC_MASK;
920 return -1;
921 }
922
923 static void load_host_msrs(struct kvm_vcpu *vcpu)
924 {
925 #ifdef CONFIG_X86_64
926 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
927 #endif
928 }
929
930 static void save_host_msrs(struct kvm_vcpu *vcpu)
931 {
932 #ifdef CONFIG_X86_64
933 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
934 #endif
935 }
936
937 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
938 {
939 if (svm_data->next_asid > svm_data->max_asid) {
940 ++svm_data->asid_generation;
941 svm_data->next_asid = 1;
942 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
943 }
944
945 svm->vcpu.cpu = svm_data->cpu;
946 svm->asid_generation = svm_data->asid_generation;
947 svm->vmcb->control.asid = svm_data->next_asid++;
948 }
949
950 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
951 {
952 return to_svm(vcpu)->db_regs[dr];
953 }
954
955 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
956 int *exception)
957 {
958 struct vcpu_svm *svm = to_svm(vcpu);
959
960 *exception = 0;
961
962 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
963 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
964 svm->vmcb->save.dr6 |= DR6_BD_MASK;
965 *exception = DB_VECTOR;
966 return;
967 }
968
969 switch (dr) {
970 case 0 ... 3:
971 svm->db_regs[dr] = value;
972 return;
973 case 4 ... 5:
974 if (vcpu->arch.cr4 & X86_CR4_DE) {
975 *exception = UD_VECTOR;
976 return;
977 }
978 case 7: {
979 if (value & ~((1ULL << 32) - 1)) {
980 *exception = GP_VECTOR;
981 return;
982 }
983 svm->vmcb->save.dr7 = value;
984 return;
985 }
986 default:
987 printk(KERN_DEBUG "%s: unexpected dr %u\n",
988 __func__, dr);
989 *exception = UD_VECTOR;
990 return;
991 }
992 }
993
994 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
995 {
996 u32 exit_int_info = svm->vmcb->control.exit_int_info;
997 struct kvm *kvm = svm->vcpu.kvm;
998 u64 fault_address;
999 u32 error_code;
1000
1001 if (!irqchip_in_kernel(kvm) &&
1002 is_external_interrupt(exit_int_info))
1003 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1004
1005 fault_address = svm->vmcb->control.exit_info_2;
1006 error_code = svm->vmcb->control.exit_info_1;
1007 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1008 }
1009
1010 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1011 {
1012 int er;
1013
1014 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1015 if (er != EMULATE_DONE)
1016 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1017 return 1;
1018 }
1019
1020 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1021 {
1022 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1023 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1024 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1025 svm->vcpu.fpu_active = 1;
1026
1027 return 1;
1028 }
1029
1030 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1031 {
1032 /*
1033 * On an #MC intercept the MCE handler is not called automatically in
1034 * the host. So do it by hand here.
1035 */
1036 asm volatile (
1037 "int $0x12\n");
1038 /* not sure if we ever come back to this point */
1039
1040 return 1;
1041 }
1042
1043 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1044 {
1045 /*
1046 * VMCB is undefined after a SHUTDOWN intercept
1047 * so reinitialize it.
1048 */
1049 clear_page(svm->vmcb);
1050 init_vmcb(svm);
1051
1052 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1053 return 0;
1054 }
1055
1056 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1057 {
1058 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1059 int size, down, in, string, rep;
1060 unsigned port;
1061
1062 ++svm->vcpu.stat.io_exits;
1063
1064 svm->next_rip = svm->vmcb->control.exit_info_2;
1065
1066 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1067
1068 if (string) {
1069 if (emulate_instruction(&svm->vcpu,
1070 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1071 return 0;
1072 return 1;
1073 }
1074
1075 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1076 port = io_info >> 16;
1077 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1078 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1079 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1080
1081 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1082 }
1083
1084 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1085 {
1086 return 1;
1087 }
1088
1089 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1090 {
1091 svm->next_rip = svm->vmcb->save.rip + 1;
1092 skip_emulated_instruction(&svm->vcpu);
1093 return kvm_emulate_halt(&svm->vcpu);
1094 }
1095
1096 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1097 {
1098 svm->next_rip = svm->vmcb->save.rip + 3;
1099 skip_emulated_instruction(&svm->vcpu);
1100 kvm_emulate_hypercall(&svm->vcpu);
1101 return 1;
1102 }
1103
1104 static int invalid_op_interception(struct vcpu_svm *svm,
1105 struct kvm_run *kvm_run)
1106 {
1107 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1108 return 1;
1109 }
1110
1111 static int task_switch_interception(struct vcpu_svm *svm,
1112 struct kvm_run *kvm_run)
1113 {
1114 u16 tss_selector;
1115
1116 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1117 if (svm->vmcb->control.exit_info_2 &
1118 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1119 return kvm_task_switch(&svm->vcpu, tss_selector,
1120 TASK_SWITCH_IRET);
1121 if (svm->vmcb->control.exit_info_2 &
1122 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1123 return kvm_task_switch(&svm->vcpu, tss_selector,
1124 TASK_SWITCH_JMP);
1125 return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1126 }
1127
1128 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1129 {
1130 svm->next_rip = svm->vmcb->save.rip + 2;
1131 kvm_emulate_cpuid(&svm->vcpu);
1132 return 1;
1133 }
1134
1135 static int emulate_on_interception(struct vcpu_svm *svm,
1136 struct kvm_run *kvm_run)
1137 {
1138 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1139 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1140 return 1;
1141 }
1142
1143 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1144 {
1145 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1146 if (irqchip_in_kernel(svm->vcpu.kvm))
1147 return 1;
1148 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1149 return 0;
1150 }
1151
1152 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1153 {
1154 struct vcpu_svm *svm = to_svm(vcpu);
1155
1156 switch (ecx) {
1157 case MSR_IA32_TIME_STAMP_COUNTER: {
1158 u64 tsc;
1159
1160 rdtscll(tsc);
1161 *data = svm->vmcb->control.tsc_offset + tsc;
1162 break;
1163 }
1164 case MSR_K6_STAR:
1165 *data = svm->vmcb->save.star;
1166 break;
1167 #ifdef CONFIG_X86_64
1168 case MSR_LSTAR:
1169 *data = svm->vmcb->save.lstar;
1170 break;
1171 case MSR_CSTAR:
1172 *data = svm->vmcb->save.cstar;
1173 break;
1174 case MSR_KERNEL_GS_BASE:
1175 *data = svm->vmcb->save.kernel_gs_base;
1176 break;
1177 case MSR_SYSCALL_MASK:
1178 *data = svm->vmcb->save.sfmask;
1179 break;
1180 #endif
1181 case MSR_IA32_SYSENTER_CS:
1182 *data = svm->vmcb->save.sysenter_cs;
1183 break;
1184 case MSR_IA32_SYSENTER_EIP:
1185 *data = svm->vmcb->save.sysenter_eip;
1186 break;
1187 case MSR_IA32_SYSENTER_ESP:
1188 *data = svm->vmcb->save.sysenter_esp;
1189 break;
1190 /* Nobody will change the following 5 values in the VMCB so
1191 we can safely return them on rdmsr. They will always be 0
1192 until LBRV is implemented. */
1193 case MSR_IA32_DEBUGCTLMSR:
1194 *data = svm->vmcb->save.dbgctl;
1195 break;
1196 case MSR_IA32_LASTBRANCHFROMIP:
1197 *data = svm->vmcb->save.br_from;
1198 break;
1199 case MSR_IA32_LASTBRANCHTOIP:
1200 *data = svm->vmcb->save.br_to;
1201 break;
1202 case MSR_IA32_LASTINTFROMIP:
1203 *data = svm->vmcb->save.last_excp_from;
1204 break;
1205 case MSR_IA32_LASTINTTOIP:
1206 *data = svm->vmcb->save.last_excp_to;
1207 break;
1208 default:
1209 return kvm_get_msr_common(vcpu, ecx, data);
1210 }
1211 return 0;
1212 }
1213
1214 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1215 {
1216 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1217 u64 data;
1218
1219 if (svm_get_msr(&svm->vcpu, ecx, &data))
1220 kvm_inject_gp(&svm->vcpu, 0);
1221 else {
1222 svm->vmcb->save.rax = data & 0xffffffff;
1223 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1224 svm->next_rip = svm->vmcb->save.rip + 2;
1225 skip_emulated_instruction(&svm->vcpu);
1226 }
1227 return 1;
1228 }
1229
1230 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1231 {
1232 struct vcpu_svm *svm = to_svm(vcpu);
1233
1234 switch (ecx) {
1235 case MSR_IA32_TIME_STAMP_COUNTER: {
1236 u64 tsc;
1237
1238 rdtscll(tsc);
1239 svm->vmcb->control.tsc_offset = data - tsc;
1240 break;
1241 }
1242 case MSR_K6_STAR:
1243 svm->vmcb->save.star = data;
1244 break;
1245 #ifdef CONFIG_X86_64
1246 case MSR_LSTAR:
1247 svm->vmcb->save.lstar = data;
1248 break;
1249 case MSR_CSTAR:
1250 svm->vmcb->save.cstar = data;
1251 break;
1252 case MSR_KERNEL_GS_BASE:
1253 svm->vmcb->save.kernel_gs_base = data;
1254 break;
1255 case MSR_SYSCALL_MASK:
1256 svm->vmcb->save.sfmask = data;
1257 break;
1258 #endif
1259 case MSR_IA32_SYSENTER_CS:
1260 svm->vmcb->save.sysenter_cs = data;
1261 break;
1262 case MSR_IA32_SYSENTER_EIP:
1263 svm->vmcb->save.sysenter_eip = data;
1264 break;
1265 case MSR_IA32_SYSENTER_ESP:
1266 svm->vmcb->save.sysenter_esp = data;
1267 break;
1268 case MSR_IA32_DEBUGCTLMSR:
1269 if (!svm_has(SVM_FEATURE_LBRV)) {
1270 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1271 __func__, data);
1272 break;
1273 }
1274 if (data & DEBUGCTL_RESERVED_BITS)
1275 return 1;
1276
1277 svm->vmcb->save.dbgctl = data;
1278 if (data & (1ULL<<0))
1279 svm_enable_lbrv(svm);
1280 else
1281 svm_disable_lbrv(svm);
1282 break;
1283 case MSR_K7_EVNTSEL0:
1284 case MSR_K7_EVNTSEL1:
1285 case MSR_K7_EVNTSEL2:
1286 case MSR_K7_EVNTSEL3:
1287 /*
1288 * only support writing 0 to the performance counters for now
1289 * to make Windows happy. Should be replaced by a real
1290 * performance counter emulation later.
1291 */
1292 if (data != 0)
1293 goto unhandled;
1294 break;
1295 default:
1296 unhandled:
1297 return kvm_set_msr_common(vcpu, ecx, data);
1298 }
1299 return 0;
1300 }
1301
1302 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1303 {
1304 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1305 u64 data = (svm->vmcb->save.rax & -1u)
1306 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1307 svm->next_rip = svm->vmcb->save.rip + 2;
1308 if (svm_set_msr(&svm->vcpu, ecx, data))
1309 kvm_inject_gp(&svm->vcpu, 0);
1310 else
1311 skip_emulated_instruction(&svm->vcpu);
1312 return 1;
1313 }
1314
1315 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1316 {
1317 if (svm->vmcb->control.exit_info_1)
1318 return wrmsr_interception(svm, kvm_run);
1319 else
1320 return rdmsr_interception(svm, kvm_run);
1321 }
1322
1323 static int interrupt_window_interception(struct vcpu_svm *svm,
1324 struct kvm_run *kvm_run)
1325 {
1326 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1327 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1328 /*
1329 * If the user space waits to inject interrupts, exit as soon as
1330 * possible
1331 */
1332 if (kvm_run->request_interrupt_window &&
1333 !svm->vcpu.arch.irq_summary) {
1334 ++svm->vcpu.stat.irq_window_exits;
1335 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1336 return 0;
1337 }
1338
1339 return 1;
1340 }
1341
1342 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1343 struct kvm_run *kvm_run) = {
1344 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1345 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1346 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1347 [SVM_EXIT_READ_CR8] = emulate_on_interception,
1348 /* for now: */
1349 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1350 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1351 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1352 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
1353 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1354 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1355 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1356 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1357 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1358 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1359 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1360 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1361 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1362 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1363 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
1364 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1365 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1366 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
1367 [SVM_EXIT_INTR] = nop_on_interception,
1368 [SVM_EXIT_NMI] = nop_on_interception,
1369 [SVM_EXIT_SMI] = nop_on_interception,
1370 [SVM_EXIT_INIT] = nop_on_interception,
1371 [SVM_EXIT_VINTR] = interrupt_window_interception,
1372 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1373 [SVM_EXIT_CPUID] = cpuid_interception,
1374 [SVM_EXIT_INVD] = emulate_on_interception,
1375 [SVM_EXIT_HLT] = halt_interception,
1376 [SVM_EXIT_INVLPG] = emulate_on_interception,
1377 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1378 [SVM_EXIT_IOIO] = io_interception,
1379 [SVM_EXIT_MSR] = msr_interception,
1380 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1381 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1382 [SVM_EXIT_VMRUN] = invalid_op_interception,
1383 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1384 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1385 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1386 [SVM_EXIT_STGI] = invalid_op_interception,
1387 [SVM_EXIT_CLGI] = invalid_op_interception,
1388 [SVM_EXIT_SKINIT] = invalid_op_interception,
1389 [SVM_EXIT_WBINVD] = emulate_on_interception,
1390 [SVM_EXIT_MONITOR] = invalid_op_interception,
1391 [SVM_EXIT_MWAIT] = invalid_op_interception,
1392 [SVM_EXIT_NPF] = pf_interception,
1393 };
1394
1395 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1396 {
1397 struct vcpu_svm *svm = to_svm(vcpu);
1398 u32 exit_code = svm->vmcb->control.exit_code;
1399
1400 if (npt_enabled) {
1401 int mmu_reload = 0;
1402 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1403 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1404 mmu_reload = 1;
1405 }
1406 vcpu->arch.cr0 = svm->vmcb->save.cr0;
1407 vcpu->arch.cr3 = svm->vmcb->save.cr3;
1408 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1409 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1410 kvm_inject_gp(vcpu, 0);
1411 return 1;
1412 }
1413 }
1414 if (mmu_reload) {
1415 kvm_mmu_reset_context(vcpu);
1416 kvm_mmu_load(vcpu);
1417 }
1418 }
1419
1420 kvm_reput_irq(svm);
1421
1422 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1423 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1424 kvm_run->fail_entry.hardware_entry_failure_reason
1425 = svm->vmcb->control.exit_code;
1426 return 0;
1427 }
1428
1429 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1430 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1431 exit_code != SVM_EXIT_NPF)
1432 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1433 "exit_code 0x%x\n",
1434 __func__, svm->vmcb->control.exit_int_info,
1435 exit_code);
1436
1437 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1438 || !svm_exit_handlers[exit_code]) {
1439 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1440 kvm_run->hw.hardware_exit_reason = exit_code;
1441 return 0;
1442 }
1443
1444 return svm_exit_handlers[exit_code](svm, kvm_run);
1445 }
1446
1447 static void reload_tss(struct kvm_vcpu *vcpu)
1448 {
1449 int cpu = raw_smp_processor_id();
1450
1451 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1452 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1453 load_TR_desc();
1454 }
1455
1456 static void pre_svm_run(struct vcpu_svm *svm)
1457 {
1458 int cpu = raw_smp_processor_id();
1459
1460 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1461
1462 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1463 if (svm->vcpu.cpu != cpu ||
1464 svm->asid_generation != svm_data->asid_generation)
1465 new_asid(svm, svm_data);
1466 }
1467
1468
1469 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1470 {
1471 struct vmcb_control_area *control;
1472
1473 control = &svm->vmcb->control;
1474 control->int_vector = irq;
1475 control->int_ctl &= ~V_INTR_PRIO_MASK;
1476 control->int_ctl |= V_IRQ_MASK |
1477 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1478 }
1479
1480 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1481 {
1482 struct vcpu_svm *svm = to_svm(vcpu);
1483
1484 svm_inject_irq(svm, irq);
1485 }
1486
1487 static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1488 {
1489 struct vcpu_svm *svm = to_svm(vcpu);
1490 struct vmcb *vmcb = svm->vmcb;
1491 int max_irr, tpr;
1492
1493 if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1494 return;
1495
1496 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1497
1498 max_irr = kvm_lapic_find_highest_irr(vcpu);
1499 if (max_irr == -1)
1500 return;
1501
1502 tpr = kvm_lapic_get_cr8(vcpu) << 4;
1503
1504 if (tpr >= (max_irr & 0xf0))
1505 vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1506 }
1507
1508 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1509 {
1510 struct vcpu_svm *svm = to_svm(vcpu);
1511 struct vmcb *vmcb = svm->vmcb;
1512 int intr_vector = -1;
1513
1514 if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1515 ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1516 intr_vector = vmcb->control.exit_int_info &
1517 SVM_EVTINJ_VEC_MASK;
1518 vmcb->control.exit_int_info = 0;
1519 svm_inject_irq(svm, intr_vector);
1520 goto out;
1521 }
1522
1523 if (vmcb->control.int_ctl & V_IRQ_MASK)
1524 goto out;
1525
1526 if (!kvm_cpu_has_interrupt(vcpu))
1527 goto out;
1528
1529 if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1530 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1531 (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1532 /* unable to deliver irq, set pending irq */
1533 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1534 svm_inject_irq(svm, 0x0);
1535 goto out;
1536 }
1537 /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1538 intr_vector = kvm_cpu_get_interrupt(vcpu);
1539 svm_inject_irq(svm, intr_vector);
1540 kvm_timer_intr_post(vcpu, intr_vector);
1541 out:
1542 update_cr8_intercept(vcpu);
1543 }
1544
1545 static void kvm_reput_irq(struct vcpu_svm *svm)
1546 {
1547 struct vmcb_control_area *control = &svm->vmcb->control;
1548
1549 if ((control->int_ctl & V_IRQ_MASK)
1550 && !irqchip_in_kernel(svm->vcpu.kvm)) {
1551 control->int_ctl &= ~V_IRQ_MASK;
1552 push_irq(&svm->vcpu, control->int_vector);
1553 }
1554
1555 svm->vcpu.arch.interrupt_window_open =
1556 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1557 }
1558
1559 static void svm_do_inject_vector(struct vcpu_svm *svm)
1560 {
1561 struct kvm_vcpu *vcpu = &svm->vcpu;
1562 int word_index = __ffs(vcpu->arch.irq_summary);
1563 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1564 int irq = word_index * BITS_PER_LONG + bit_index;
1565
1566 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1567 if (!vcpu->arch.irq_pending[word_index])
1568 clear_bit(word_index, &vcpu->arch.irq_summary);
1569 svm_inject_irq(svm, irq);
1570 }
1571
1572 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1573 struct kvm_run *kvm_run)
1574 {
1575 struct vcpu_svm *svm = to_svm(vcpu);
1576 struct vmcb_control_area *control = &svm->vmcb->control;
1577
1578 svm->vcpu.arch.interrupt_window_open =
1579 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1580 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1581
1582 if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1583 /*
1584 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1585 */
1586 svm_do_inject_vector(svm);
1587
1588 /*
1589 * Interrupts blocked. Wait for unblock.
1590 */
1591 if (!svm->vcpu.arch.interrupt_window_open &&
1592 (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1593 control->intercept |= 1ULL << INTERCEPT_VINTR;
1594 else
1595 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1596 }
1597
1598 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1599 {
1600 return 0;
1601 }
1602
1603 static void save_db_regs(unsigned long *db_regs)
1604 {
1605 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1606 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1607 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1608 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1609 }
1610
1611 static void load_db_regs(unsigned long *db_regs)
1612 {
1613 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1614 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1615 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1616 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1617 }
1618
1619 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1620 {
1621 force_new_asid(vcpu);
1622 }
1623
1624 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1625 {
1626 }
1627
1628 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1629 {
1630 struct vcpu_svm *svm = to_svm(vcpu);
1631
1632 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1633 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1634 kvm_lapic_set_tpr(vcpu, cr8);
1635 }
1636 }
1637
1638 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1639 {
1640 struct vcpu_svm *svm = to_svm(vcpu);
1641 u64 cr8;
1642
1643 if (!irqchip_in_kernel(vcpu->kvm))
1644 return;
1645
1646 cr8 = kvm_get_cr8(vcpu);
1647 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1648 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1649 }
1650
1651 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1652 {
1653 struct vcpu_svm *svm = to_svm(vcpu);
1654 u16 fs_selector;
1655 u16 gs_selector;
1656 u16 ldt_selector;
1657
1658 pre_svm_run(svm);
1659
1660 sync_lapic_to_cr8(vcpu);
1661
1662 save_host_msrs(vcpu);
1663 fs_selector = read_fs();
1664 gs_selector = read_gs();
1665 ldt_selector = read_ldt();
1666 svm->host_cr2 = kvm_read_cr2();
1667 svm->host_dr6 = read_dr6();
1668 svm->host_dr7 = read_dr7();
1669 svm->vmcb->save.cr2 = vcpu->arch.cr2;
1670 /* required for live migration with NPT */
1671 if (npt_enabled)
1672 svm->vmcb->save.cr3 = vcpu->arch.cr3;
1673
1674 if (svm->vmcb->save.dr7 & 0xff) {
1675 write_dr7(0);
1676 save_db_regs(svm->host_db_regs);
1677 load_db_regs(svm->db_regs);
1678 }
1679
1680 clgi();
1681
1682 local_irq_enable();
1683
1684 asm volatile (
1685 #ifdef CONFIG_X86_64
1686 "push %%rbp; \n\t"
1687 #else
1688 "push %%ebp; \n\t"
1689 #endif
1690
1691 #ifdef CONFIG_X86_64
1692 "mov %c[rbx](%[svm]), %%rbx \n\t"
1693 "mov %c[rcx](%[svm]), %%rcx \n\t"
1694 "mov %c[rdx](%[svm]), %%rdx \n\t"
1695 "mov %c[rsi](%[svm]), %%rsi \n\t"
1696 "mov %c[rdi](%[svm]), %%rdi \n\t"
1697 "mov %c[rbp](%[svm]), %%rbp \n\t"
1698 "mov %c[r8](%[svm]), %%r8 \n\t"
1699 "mov %c[r9](%[svm]), %%r9 \n\t"
1700 "mov %c[r10](%[svm]), %%r10 \n\t"
1701 "mov %c[r11](%[svm]), %%r11 \n\t"
1702 "mov %c[r12](%[svm]), %%r12 \n\t"
1703 "mov %c[r13](%[svm]), %%r13 \n\t"
1704 "mov %c[r14](%[svm]), %%r14 \n\t"
1705 "mov %c[r15](%[svm]), %%r15 \n\t"
1706 #else
1707 "mov %c[rbx](%[svm]), %%ebx \n\t"
1708 "mov %c[rcx](%[svm]), %%ecx \n\t"
1709 "mov %c[rdx](%[svm]), %%edx \n\t"
1710 "mov %c[rsi](%[svm]), %%esi \n\t"
1711 "mov %c[rdi](%[svm]), %%edi \n\t"
1712 "mov %c[rbp](%[svm]), %%ebp \n\t"
1713 #endif
1714
1715 #ifdef CONFIG_X86_64
1716 /* Enter guest mode */
1717 "push %%rax \n\t"
1718 "mov %c[vmcb](%[svm]), %%rax \n\t"
1719 SVM_VMLOAD "\n\t"
1720 SVM_VMRUN "\n\t"
1721 SVM_VMSAVE "\n\t"
1722 "pop %%rax \n\t"
1723 #else
1724 /* Enter guest mode */
1725 "push %%eax \n\t"
1726 "mov %c[vmcb](%[svm]), %%eax \n\t"
1727 SVM_VMLOAD "\n\t"
1728 SVM_VMRUN "\n\t"
1729 SVM_VMSAVE "\n\t"
1730 "pop %%eax \n\t"
1731 #endif
1732
1733 /* Save guest registers, load host registers */
1734 #ifdef CONFIG_X86_64
1735 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1736 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1737 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1738 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1739 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1740 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1741 "mov %%r8, %c[r8](%[svm]) \n\t"
1742 "mov %%r9, %c[r9](%[svm]) \n\t"
1743 "mov %%r10, %c[r10](%[svm]) \n\t"
1744 "mov %%r11, %c[r11](%[svm]) \n\t"
1745 "mov %%r12, %c[r12](%[svm]) \n\t"
1746 "mov %%r13, %c[r13](%[svm]) \n\t"
1747 "mov %%r14, %c[r14](%[svm]) \n\t"
1748 "mov %%r15, %c[r15](%[svm]) \n\t"
1749
1750 "pop %%rbp; \n\t"
1751 #else
1752 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1753 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1754 "mov %%edx, %c[rdx](%[svm]) \n\t"
1755 "mov %%esi, %c[rsi](%[svm]) \n\t"
1756 "mov %%edi, %c[rdi](%[svm]) \n\t"
1757 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1758
1759 "pop %%ebp; \n\t"
1760 #endif
1761 :
1762 : [svm]"a"(svm),
1763 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1764 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1765 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1766 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1767 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1768 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1769 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1770 #ifdef CONFIG_X86_64
1771 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1772 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1773 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1774 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1775 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1776 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1777 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1778 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1779 #endif
1780 : "cc", "memory"
1781 #ifdef CONFIG_X86_64
1782 , "rbx", "rcx", "rdx", "rsi", "rdi"
1783 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1784 #else
1785 , "ebx", "ecx", "edx" , "esi", "edi"
1786 #endif
1787 );
1788
1789 if ((svm->vmcb->save.dr7 & 0xff))
1790 load_db_regs(svm->host_db_regs);
1791
1792 vcpu->arch.cr2 = svm->vmcb->save.cr2;
1793
1794 write_dr6(svm->host_dr6);
1795 write_dr7(svm->host_dr7);
1796 kvm_write_cr2(svm->host_cr2);
1797
1798 load_fs(fs_selector);
1799 load_gs(gs_selector);
1800 load_ldt(ldt_selector);
1801 load_host_msrs(vcpu);
1802
1803 reload_tss(vcpu);
1804
1805 local_irq_disable();
1806
1807 stgi();
1808
1809 sync_cr8_to_lapic(vcpu);
1810
1811 svm->next_rip = 0;
1812 }
1813
1814 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1815 {
1816 struct vcpu_svm *svm = to_svm(vcpu);
1817
1818 if (npt_enabled) {
1819 svm->vmcb->control.nested_cr3 = root;
1820 force_new_asid(vcpu);
1821 return;
1822 }
1823
1824 svm->vmcb->save.cr3 = root;
1825 force_new_asid(vcpu);
1826
1827 if (vcpu->fpu_active) {
1828 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1829 svm->vmcb->save.cr0 |= X86_CR0_TS;
1830 vcpu->fpu_active = 0;
1831 }
1832 }
1833
1834 static int is_disabled(void)
1835 {
1836 u64 vm_cr;
1837
1838 rdmsrl(MSR_VM_CR, vm_cr);
1839 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1840 return 1;
1841
1842 return 0;
1843 }
1844
1845 static void
1846 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1847 {
1848 /*
1849 * Patch in the VMMCALL instruction:
1850 */
1851 hypercall[0] = 0x0f;
1852 hypercall[1] = 0x01;
1853 hypercall[2] = 0xd9;
1854 }
1855
1856 static void svm_check_processor_compat(void *rtn)
1857 {
1858 *(int *)rtn = 0;
1859 }
1860
1861 static bool svm_cpu_has_accelerated_tpr(void)
1862 {
1863 return false;
1864 }
1865
1866 static struct kvm_x86_ops svm_x86_ops = {
1867 .cpu_has_kvm_support = has_svm,
1868 .disabled_by_bios = is_disabled,
1869 .hardware_setup = svm_hardware_setup,
1870 .hardware_unsetup = svm_hardware_unsetup,
1871 .check_processor_compatibility = svm_check_processor_compat,
1872 .hardware_enable = svm_hardware_enable,
1873 .hardware_disable = svm_hardware_disable,
1874 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1875
1876 .vcpu_create = svm_create_vcpu,
1877 .vcpu_free = svm_free_vcpu,
1878 .vcpu_reset = svm_vcpu_reset,
1879
1880 .prepare_guest_switch = svm_prepare_guest_switch,
1881 .vcpu_load = svm_vcpu_load,
1882 .vcpu_put = svm_vcpu_put,
1883 .vcpu_decache = svm_vcpu_decache,
1884
1885 .set_guest_debug = svm_guest_debug,
1886 .get_msr = svm_get_msr,
1887 .set_msr = svm_set_msr,
1888 .get_segment_base = svm_get_segment_base,
1889 .get_segment = svm_get_segment,
1890 .set_segment = svm_set_segment,
1891 .get_cpl = svm_get_cpl,
1892 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1893 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1894 .set_cr0 = svm_set_cr0,
1895 .set_cr3 = svm_set_cr3,
1896 .set_cr4 = svm_set_cr4,
1897 .set_efer = svm_set_efer,
1898 .get_idt = svm_get_idt,
1899 .set_idt = svm_set_idt,
1900 .get_gdt = svm_get_gdt,
1901 .set_gdt = svm_set_gdt,
1902 .get_dr = svm_get_dr,
1903 .set_dr = svm_set_dr,
1904 .cache_regs = svm_cache_regs,
1905 .decache_regs = svm_decache_regs,
1906 .get_rflags = svm_get_rflags,
1907 .set_rflags = svm_set_rflags,
1908
1909 .tlb_flush = svm_flush_tlb,
1910
1911 .run = svm_vcpu_run,
1912 .handle_exit = handle_exit,
1913 .skip_emulated_instruction = skip_emulated_instruction,
1914 .patch_hypercall = svm_patch_hypercall,
1915 .get_irq = svm_get_irq,
1916 .set_irq = svm_set_irq,
1917 .queue_exception = svm_queue_exception,
1918 .exception_injected = svm_exception_injected,
1919 .inject_pending_irq = svm_intr_assist,
1920 .inject_pending_vectors = do_interrupt_requests,
1921
1922 .set_tss_addr = svm_set_tss_addr,
1923 };
1924
1925 static int __init svm_init(void)
1926 {
1927 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
1928 THIS_MODULE);
1929 }
1930
1931 static void __exit svm_exit(void)
1932 {
1933 kvm_exit();
1934 }
1935
1936 module_init(svm_init)
1937 module_exit(svm_exit)
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