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[SCSI] aic94xx: fix section mismatch
[linux-2.6/openmoko-kernel/knife-kernel.git] / arch / x86 / kvm / vmx.c
blob8e5d6645b90d11e08c6f71153e722a004c570457
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "vmx.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29
30 #include <asm/io.h>
31 #include <asm/desc.h>
32
33 MODULE_AUTHOR("Qumranet");
34 MODULE_LICENSE("GPL");
35
36 static int bypass_guest_pf = 1;
37 module_param(bypass_guest_pf, bool, 0);
38
39 static int enable_vpid = 1;
40 module_param(enable_vpid, bool, 0);
41
42 static int flexpriority_enabled = 1;
43 module_param(flexpriority_enabled, bool, 0);
44
45 struct vmcs {
46 u32 revision_id;
47 u32 abort;
48 char data[0];
49 };
50
51 struct vcpu_vmx {
52 struct kvm_vcpu vcpu;
53 int launched;
54 u8 fail;
55 u32 idt_vectoring_info;
56 struct kvm_msr_entry *guest_msrs;
57 struct kvm_msr_entry *host_msrs;
58 int nmsrs;
59 int save_nmsrs;
60 int msr_offset_efer;
61 #ifdef CONFIG_X86_64
62 int msr_offset_kernel_gs_base;
63 #endif
64 struct vmcs *vmcs;
65 struct {
66 int loaded;
67 u16 fs_sel, gs_sel, ldt_sel;
68 int gs_ldt_reload_needed;
69 int fs_reload_needed;
70 int guest_efer_loaded;
71 } host_state;
72 struct {
73 struct {
74 bool pending;
75 u8 vector;
76 unsigned rip;
77 } irq;
78 } rmode;
79 int vpid;
80 };
81
82 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
83 {
84 return container_of(vcpu, struct vcpu_vmx, vcpu);
85 }
86
87 static int init_rmode_tss(struct kvm *kvm);
88
89 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
90 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
91
92 static struct page *vmx_io_bitmap_a;
93 static struct page *vmx_io_bitmap_b;
94 static struct page *vmx_msr_bitmap;
95
96 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
97 static DEFINE_SPINLOCK(vmx_vpid_lock);
98
99 static struct vmcs_config {
100 int size;
101 int order;
102 u32 revision_id;
103 u32 pin_based_exec_ctrl;
104 u32 cpu_based_exec_ctrl;
105 u32 cpu_based_2nd_exec_ctrl;
106 u32 vmexit_ctrl;
107 u32 vmentry_ctrl;
108 } vmcs_config;
109
110 #define VMX_SEGMENT_FIELD(seg) \
111 [VCPU_SREG_##seg] = { \
112 .selector = GUEST_##seg##_SELECTOR, \
113 .base = GUEST_##seg##_BASE, \
114 .limit = GUEST_##seg##_LIMIT, \
115 .ar_bytes = GUEST_##seg##_AR_BYTES, \
116 }
117
118 static struct kvm_vmx_segment_field {
119 unsigned selector;
120 unsigned base;
121 unsigned limit;
122 unsigned ar_bytes;
123 } kvm_vmx_segment_fields[] = {
124 VMX_SEGMENT_FIELD(CS),
125 VMX_SEGMENT_FIELD(DS),
126 VMX_SEGMENT_FIELD(ES),
127 VMX_SEGMENT_FIELD(FS),
128 VMX_SEGMENT_FIELD(GS),
129 VMX_SEGMENT_FIELD(SS),
130 VMX_SEGMENT_FIELD(TR),
131 VMX_SEGMENT_FIELD(LDTR),
132 };
133
134 /*
135 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
136 * away by decrementing the array size.
137 */
138 static const u32 vmx_msr_index[] = {
139 #ifdef CONFIG_X86_64
140 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
141 #endif
142 MSR_EFER, MSR_K6_STAR,
143 };
144 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
145
146 static void load_msrs(struct kvm_msr_entry *e, int n)
147 {
148 int i;
149
150 for (i = 0; i < n; ++i)
151 wrmsrl(e[i].index, e[i].data);
152 }
153
154 static void save_msrs(struct kvm_msr_entry *e, int n)
155 {
156 int i;
157
158 for (i = 0; i < n; ++i)
159 rdmsrl(e[i].index, e[i].data);
160 }
161
162 static inline int is_page_fault(u32 intr_info)
163 {
164 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
165 INTR_INFO_VALID_MASK)) ==
166 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
167 }
168
169 static inline int is_no_device(u32 intr_info)
170 {
171 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
172 INTR_INFO_VALID_MASK)) ==
173 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
174 }
175
176 static inline int is_invalid_opcode(u32 intr_info)
177 {
178 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
179 INTR_INFO_VALID_MASK)) ==
180 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
181 }
182
183 static inline int is_external_interrupt(u32 intr_info)
184 {
185 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
186 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
187 }
188
189 static inline int cpu_has_vmx_msr_bitmap(void)
190 {
191 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
192 }
193
194 static inline int cpu_has_vmx_tpr_shadow(void)
195 {
196 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
197 }
198
199 static inline int vm_need_tpr_shadow(struct kvm *kvm)
200 {
201 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
202 }
203
204 static inline int cpu_has_secondary_exec_ctrls(void)
205 {
206 return (vmcs_config.cpu_based_exec_ctrl &
207 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
208 }
209
210 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
211 {
212 return flexpriority_enabled
213 && (vmcs_config.cpu_based_2nd_exec_ctrl &
214 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
215 }
216
217 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
218 {
219 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
220 (irqchip_in_kernel(kvm)));
221 }
222
223 static inline int cpu_has_vmx_vpid(void)
224 {
225 return (vmcs_config.cpu_based_2nd_exec_ctrl &
226 SECONDARY_EXEC_ENABLE_VPID);
227 }
228
229 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
230 {
231 int i;
232
233 for (i = 0; i < vmx->nmsrs; ++i)
234 if (vmx->guest_msrs[i].index == msr)
235 return i;
236 return -1;
237 }
238
239 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
240 {
241 struct {
242 u64 vpid : 16;
243 u64 rsvd : 48;
244 u64 gva;
245 } operand = { vpid, 0, gva };
246
247 asm volatile (ASM_VMX_INVVPID
248 /* CF==1 or ZF==1 --> rc = -1 */
249 "; ja 1f ; ud2 ; 1:"
250 : : "a"(&operand), "c"(ext) : "cc", "memory");
251 }
252
253 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
254 {
255 int i;
256
257 i = __find_msr_index(vmx, msr);
258 if (i >= 0)
259 return &vmx->guest_msrs[i];
260 return NULL;
261 }
262
263 static void vmcs_clear(struct vmcs *vmcs)
264 {
265 u64 phys_addr = __pa(vmcs);
266 u8 error;
267
268 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
269 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
270 : "cc", "memory");
271 if (error)
272 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
273 vmcs, phys_addr);
274 }
275
276 static void __vcpu_clear(void *arg)
277 {
278 struct vcpu_vmx *vmx = arg;
279 int cpu = raw_smp_processor_id();
280
281 if (vmx->vcpu.cpu == cpu)
282 vmcs_clear(vmx->vmcs);
283 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
284 per_cpu(current_vmcs, cpu) = NULL;
285 rdtscll(vmx->vcpu.arch.host_tsc);
286 }
287
288 static void vcpu_clear(struct vcpu_vmx *vmx)
289 {
290 if (vmx->vcpu.cpu == -1)
291 return;
292 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
293 vmx->launched = 0;
294 }
295
296 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
297 {
298 if (vmx->vpid == 0)
299 return;
300
301 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
302 }
303
304 static unsigned long vmcs_readl(unsigned long field)
305 {
306 unsigned long value;
307
308 asm volatile (ASM_VMX_VMREAD_RDX_RAX
309 : "=a"(value) : "d"(field) : "cc");
310 return value;
311 }
312
313 static u16 vmcs_read16(unsigned long field)
314 {
315 return vmcs_readl(field);
316 }
317
318 static u32 vmcs_read32(unsigned long field)
319 {
320 return vmcs_readl(field);
321 }
322
323 static u64 vmcs_read64(unsigned long field)
324 {
325 #ifdef CONFIG_X86_64
326 return vmcs_readl(field);
327 #else
328 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
329 #endif
330 }
331
332 static noinline void vmwrite_error(unsigned long field, unsigned long value)
333 {
334 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
335 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
336 dump_stack();
337 }
338
339 static void vmcs_writel(unsigned long field, unsigned long value)
340 {
341 u8 error;
342
343 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
344 : "=q"(error) : "a"(value), "d"(field) : "cc");
345 if (unlikely(error))
346 vmwrite_error(field, value);
347 }
348
349 static void vmcs_write16(unsigned long field, u16 value)
350 {
351 vmcs_writel(field, value);
352 }
353
354 static void vmcs_write32(unsigned long field, u32 value)
355 {
356 vmcs_writel(field, value);
357 }
358
359 static void vmcs_write64(unsigned long field, u64 value)
360 {
361 #ifdef CONFIG_X86_64
362 vmcs_writel(field, value);
363 #else
364 vmcs_writel(field, value);
365 asm volatile ("");
366 vmcs_writel(field+1, value >> 32);
367 #endif
368 }
369
370 static void vmcs_clear_bits(unsigned long field, u32 mask)
371 {
372 vmcs_writel(field, vmcs_readl(field) & ~mask);
373 }
374
375 static void vmcs_set_bits(unsigned long field, u32 mask)
376 {
377 vmcs_writel(field, vmcs_readl(field) | mask);
378 }
379
380 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
381 {
382 u32 eb;
383
384 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
385 if (!vcpu->fpu_active)
386 eb |= 1u << NM_VECTOR;
387 if (vcpu->guest_debug.enabled)
388 eb |= 1u << 1;
389 if (vcpu->arch.rmode.active)
390 eb = ~0;
391 vmcs_write32(EXCEPTION_BITMAP, eb);
392 }
393
394 static void reload_tss(void)
395 {
396 /*
397 * VT restores TR but not its size. Useless.
398 */
399 struct descriptor_table gdt;
400 struct desc_struct *descs;
401
402 get_gdt(&gdt);
403 descs = (void *)gdt.base;
404 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
405 load_TR_desc();
406 }
407
408 static void load_transition_efer(struct vcpu_vmx *vmx)
409 {
410 int efer_offset = vmx->msr_offset_efer;
411 u64 host_efer = vmx->host_msrs[efer_offset].data;
412 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
413 u64 ignore_bits;
414
415 if (efer_offset < 0)
416 return;
417 /*
418 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
419 * outside long mode
420 */
421 ignore_bits = EFER_NX | EFER_SCE;
422 #ifdef CONFIG_X86_64
423 ignore_bits |= EFER_LMA | EFER_LME;
424 /* SCE is meaningful only in long mode on Intel */
425 if (guest_efer & EFER_LMA)
426 ignore_bits &= ~(u64)EFER_SCE;
427 #endif
428 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
429 return;
430
431 vmx->host_state.guest_efer_loaded = 1;
432 guest_efer &= ~ignore_bits;
433 guest_efer |= host_efer & ignore_bits;
434 wrmsrl(MSR_EFER, guest_efer);
435 vmx->vcpu.stat.efer_reload++;
436 }
437
438 static void reload_host_efer(struct vcpu_vmx *vmx)
439 {
440 if (vmx->host_state.guest_efer_loaded) {
441 vmx->host_state.guest_efer_loaded = 0;
442 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
443 }
444 }
445
446 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
447 {
448 struct vcpu_vmx *vmx = to_vmx(vcpu);
449
450 if (vmx->host_state.loaded)
451 return;
452
453 vmx->host_state.loaded = 1;
454 /*
455 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
456 * allow segment selectors with cpl > 0 or ti == 1.
457 */
458 vmx->host_state.ldt_sel = read_ldt();
459 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
460 vmx->host_state.fs_sel = read_fs();
461 if (!(vmx->host_state.fs_sel & 7)) {
462 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
463 vmx->host_state.fs_reload_needed = 0;
464 } else {
465 vmcs_write16(HOST_FS_SELECTOR, 0);
466 vmx->host_state.fs_reload_needed = 1;
467 }
468 vmx->host_state.gs_sel = read_gs();
469 if (!(vmx->host_state.gs_sel & 7))
470 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
471 else {
472 vmcs_write16(HOST_GS_SELECTOR, 0);
473 vmx->host_state.gs_ldt_reload_needed = 1;
474 }
475
476 #ifdef CONFIG_X86_64
477 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
478 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
479 #else
480 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
481 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
482 #endif
483
484 #ifdef CONFIG_X86_64
485 if (is_long_mode(&vmx->vcpu))
486 save_msrs(vmx->host_msrs +
487 vmx->msr_offset_kernel_gs_base, 1);
488
489 #endif
490 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
491 load_transition_efer(vmx);
492 }
493
494 static void vmx_load_host_state(struct vcpu_vmx *vmx)
495 {
496 unsigned long flags;
497
498 if (!vmx->host_state.loaded)
499 return;
500
501 ++vmx->vcpu.stat.host_state_reload;
502 vmx->host_state.loaded = 0;
503 if (vmx->host_state.fs_reload_needed)
504 load_fs(vmx->host_state.fs_sel);
505 if (vmx->host_state.gs_ldt_reload_needed) {
506 load_ldt(vmx->host_state.ldt_sel);
507 /*
508 * If we have to reload gs, we must take care to
509 * preserve our gs base.
510 */
511 local_irq_save(flags);
512 load_gs(vmx->host_state.gs_sel);
513 #ifdef CONFIG_X86_64
514 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
515 #endif
516 local_irq_restore(flags);
517 }
518 reload_tss();
519 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
520 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
521 reload_host_efer(vmx);
522 }
523
524 /*
525 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
526 * vcpu mutex is already taken.
527 */
528 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
529 {
530 struct vcpu_vmx *vmx = to_vmx(vcpu);
531 u64 phys_addr = __pa(vmx->vmcs);
532 u64 tsc_this, delta, new_offset;
533
534 if (vcpu->cpu != cpu) {
535 vcpu_clear(vmx);
536 kvm_migrate_apic_timer(vcpu);
537 vpid_sync_vcpu_all(vmx);
538 }
539
540 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
541 u8 error;
542
543 per_cpu(current_vmcs, cpu) = vmx->vmcs;
544 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
545 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
546 : "cc");
547 if (error)
548 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
549 vmx->vmcs, phys_addr);
550 }
551
552 if (vcpu->cpu != cpu) {
553 struct descriptor_table dt;
554 unsigned long sysenter_esp;
555
556 vcpu->cpu = cpu;
557 /*
558 * Linux uses per-cpu TSS and GDT, so set these when switching
559 * processors.
560 */
561 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
562 get_gdt(&dt);
563 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
564
565 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
566 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
567
568 /*
569 * Make sure the time stamp counter is monotonous.
570 */
571 rdtscll(tsc_this);
572 if (tsc_this < vcpu->arch.host_tsc) {
573 delta = vcpu->arch.host_tsc - tsc_this;
574 new_offset = vmcs_read64(TSC_OFFSET) + delta;
575 vmcs_write64(TSC_OFFSET, new_offset);
576 }
577 }
578 }
579
580 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
581 {
582 vmx_load_host_state(to_vmx(vcpu));
583 }
584
585 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
586 {
587 if (vcpu->fpu_active)
588 return;
589 vcpu->fpu_active = 1;
590 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
591 if (vcpu->arch.cr0 & X86_CR0_TS)
592 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
593 update_exception_bitmap(vcpu);
594 }
595
596 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
597 {
598 if (!vcpu->fpu_active)
599 return;
600 vcpu->fpu_active = 0;
601 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
602 update_exception_bitmap(vcpu);
603 }
604
605 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
606 {
607 vcpu_clear(to_vmx(vcpu));
608 }
609
610 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
611 {
612 return vmcs_readl(GUEST_RFLAGS);
613 }
614
615 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
616 {
617 if (vcpu->arch.rmode.active)
618 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
619 vmcs_writel(GUEST_RFLAGS, rflags);
620 }
621
622 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
623 {
624 unsigned long rip;
625 u32 interruptibility;
626
627 rip = vmcs_readl(GUEST_RIP);
628 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
629 vmcs_writel(GUEST_RIP, rip);
630
631 /*
632 * We emulated an instruction, so temporary interrupt blocking
633 * should be removed, if set.
634 */
635 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
636 if (interruptibility & 3)
637 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
638 interruptibility & ~3);
639 vcpu->arch.interrupt_window_open = 1;
640 }
641
642 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
643 bool has_error_code, u32 error_code)
644 {
645 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
646 nr | INTR_TYPE_EXCEPTION
647 | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0)
648 | INTR_INFO_VALID_MASK);
649 if (has_error_code)
650 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
651 }
652
653 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
654 {
655 struct vcpu_vmx *vmx = to_vmx(vcpu);
656
657 return !(vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
658 }
659
660 /*
661 * Swap MSR entry in host/guest MSR entry array.
662 */
663 #ifdef CONFIG_X86_64
664 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
665 {
666 struct kvm_msr_entry tmp;
667
668 tmp = vmx->guest_msrs[to];
669 vmx->guest_msrs[to] = vmx->guest_msrs[from];
670 vmx->guest_msrs[from] = tmp;
671 tmp = vmx->host_msrs[to];
672 vmx->host_msrs[to] = vmx->host_msrs[from];
673 vmx->host_msrs[from] = tmp;
674 }
675 #endif
676
677 /*
678 * Set up the vmcs to automatically save and restore system
679 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
680 * mode, as fiddling with msrs is very expensive.
681 */
682 static void setup_msrs(struct vcpu_vmx *vmx)
683 {
684 int save_nmsrs;
685
686 vmx_load_host_state(vmx);
687 save_nmsrs = 0;
688 #ifdef CONFIG_X86_64
689 if (is_long_mode(&vmx->vcpu)) {
690 int index;
691
692 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
693 if (index >= 0)
694 move_msr_up(vmx, index, save_nmsrs++);
695 index = __find_msr_index(vmx, MSR_LSTAR);
696 if (index >= 0)
697 move_msr_up(vmx, index, save_nmsrs++);
698 index = __find_msr_index(vmx, MSR_CSTAR);
699 if (index >= 0)
700 move_msr_up(vmx, index, save_nmsrs++);
701 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
702 if (index >= 0)
703 move_msr_up(vmx, index, save_nmsrs++);
704 /*
705 * MSR_K6_STAR is only needed on long mode guests, and only
706 * if efer.sce is enabled.
707 */
708 index = __find_msr_index(vmx, MSR_K6_STAR);
709 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
710 move_msr_up(vmx, index, save_nmsrs++);
711 }
712 #endif
713 vmx->save_nmsrs = save_nmsrs;
714
715 #ifdef CONFIG_X86_64
716 vmx->msr_offset_kernel_gs_base =
717 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
718 #endif
719 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
720 }
721
722 /*
723 * reads and returns guest's timestamp counter "register"
724 * guest_tsc = host_tsc + tsc_offset -- 21.3
725 */
726 static u64 guest_read_tsc(void)
727 {
728 u64 host_tsc, tsc_offset;
729
730 rdtscll(host_tsc);
731 tsc_offset = vmcs_read64(TSC_OFFSET);
732 return host_tsc + tsc_offset;
733 }
734
735 /*
736 * writes 'guest_tsc' into guest's timestamp counter "register"
737 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
738 */
739 static void guest_write_tsc(u64 guest_tsc)
740 {
741 u64 host_tsc;
742
743 rdtscll(host_tsc);
744 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
745 }
746
747 /*
748 * Reads an msr value (of 'msr_index') into 'pdata'.
749 * Returns 0 on success, non-0 otherwise.
750 * Assumes vcpu_load() was already called.
751 */
752 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
753 {
754 u64 data;
755 struct kvm_msr_entry *msr;
756
757 if (!pdata) {
758 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
759 return -EINVAL;
760 }
761
762 switch (msr_index) {
763 #ifdef CONFIG_X86_64
764 case MSR_FS_BASE:
765 data = vmcs_readl(GUEST_FS_BASE);
766 break;
767 case MSR_GS_BASE:
768 data = vmcs_readl(GUEST_GS_BASE);
769 break;
770 case MSR_EFER:
771 return kvm_get_msr_common(vcpu, msr_index, pdata);
772 #endif
773 case MSR_IA32_TIME_STAMP_COUNTER:
774 data = guest_read_tsc();
775 break;
776 case MSR_IA32_SYSENTER_CS:
777 data = vmcs_read32(GUEST_SYSENTER_CS);
778 break;
779 case MSR_IA32_SYSENTER_EIP:
780 data = vmcs_readl(GUEST_SYSENTER_EIP);
781 break;
782 case MSR_IA32_SYSENTER_ESP:
783 data = vmcs_readl(GUEST_SYSENTER_ESP);
784 break;
785 default:
786 msr = find_msr_entry(to_vmx(vcpu), msr_index);
787 if (msr) {
788 data = msr->data;
789 break;
790 }
791 return kvm_get_msr_common(vcpu, msr_index, pdata);
792 }
793
794 *pdata = data;
795 return 0;
796 }
797
798 /*
799 * Writes msr value into into the appropriate "register".
800 * Returns 0 on success, non-0 otherwise.
801 * Assumes vcpu_load() was already called.
802 */
803 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
804 {
805 struct vcpu_vmx *vmx = to_vmx(vcpu);
806 struct kvm_msr_entry *msr;
807 int ret = 0;
808
809 switch (msr_index) {
810 #ifdef CONFIG_X86_64
811 case MSR_EFER:
812 ret = kvm_set_msr_common(vcpu, msr_index, data);
813 if (vmx->host_state.loaded) {
814 reload_host_efer(vmx);
815 load_transition_efer(vmx);
816 }
817 break;
818 case MSR_FS_BASE:
819 vmcs_writel(GUEST_FS_BASE, data);
820 break;
821 case MSR_GS_BASE:
822 vmcs_writel(GUEST_GS_BASE, data);
823 break;
824 #endif
825 case MSR_IA32_SYSENTER_CS:
826 vmcs_write32(GUEST_SYSENTER_CS, data);
827 break;
828 case MSR_IA32_SYSENTER_EIP:
829 vmcs_writel(GUEST_SYSENTER_EIP, data);
830 break;
831 case MSR_IA32_SYSENTER_ESP:
832 vmcs_writel(GUEST_SYSENTER_ESP, data);
833 break;
834 case MSR_IA32_TIME_STAMP_COUNTER:
835 guest_write_tsc(data);
836 break;
837 default:
838 msr = find_msr_entry(vmx, msr_index);
839 if (msr) {
840 msr->data = data;
841 if (vmx->host_state.loaded)
842 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
843 break;
844 }
845 ret = kvm_set_msr_common(vcpu, msr_index, data);
846 }
847
848 return ret;
849 }
850
851 /*
852 * Sync the rsp and rip registers into the vcpu structure. This allows
853 * registers to be accessed by indexing vcpu->arch.regs.
854 */
855 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
856 {
857 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
858 vcpu->arch.rip = vmcs_readl(GUEST_RIP);
859 }
860
861 /*
862 * Syncs rsp and rip back into the vmcs. Should be called after possible
863 * modification.
864 */
865 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
866 {
867 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
868 vmcs_writel(GUEST_RIP, vcpu->arch.rip);
869 }
870
871 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
872 {
873 unsigned long dr7 = 0x400;
874 int old_singlestep;
875
876 old_singlestep = vcpu->guest_debug.singlestep;
877
878 vcpu->guest_debug.enabled = dbg->enabled;
879 if (vcpu->guest_debug.enabled) {
880 int i;
881
882 dr7 |= 0x200; /* exact */
883 for (i = 0; i < 4; ++i) {
884 if (!dbg->breakpoints[i].enabled)
885 continue;
886 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
887 dr7 |= 2 << (i*2); /* global enable */
888 dr7 |= 0 << (i*4+16); /* execution breakpoint */
889 }
890
891 vcpu->guest_debug.singlestep = dbg->singlestep;
892 } else
893 vcpu->guest_debug.singlestep = 0;
894
895 if (old_singlestep && !vcpu->guest_debug.singlestep) {
896 unsigned long flags;
897
898 flags = vmcs_readl(GUEST_RFLAGS);
899 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
900 vmcs_writel(GUEST_RFLAGS, flags);
901 }
902
903 update_exception_bitmap(vcpu);
904 vmcs_writel(GUEST_DR7, dr7);
905
906 return 0;
907 }
908
909 static int vmx_get_irq(struct kvm_vcpu *vcpu)
910 {
911 struct vcpu_vmx *vmx = to_vmx(vcpu);
912 u32 idtv_info_field;
913
914 idtv_info_field = vmx->idt_vectoring_info;
915 if (idtv_info_field & INTR_INFO_VALID_MASK) {
916 if (is_external_interrupt(idtv_info_field))
917 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
918 else
919 printk(KERN_DEBUG "pending exception: not handled yet\n");
920 }
921 return -1;
922 }
923
924 static __init int cpu_has_kvm_support(void)
925 {
926 unsigned long ecx = cpuid_ecx(1);
927 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
928 }
929
930 static __init int vmx_disabled_by_bios(void)
931 {
932 u64 msr;
933
934 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
935 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
936 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
937 == MSR_IA32_FEATURE_CONTROL_LOCKED;
938 /* locked but not enabled */
939 }
940
941 static void hardware_enable(void *garbage)
942 {
943 int cpu = raw_smp_processor_id();
944 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
945 u64 old;
946
947 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
948 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
949 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
950 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
951 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
952 /* enable and lock */
953 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
954 MSR_IA32_FEATURE_CONTROL_LOCKED |
955 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
956 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
957 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
958 : "memory", "cc");
959 }
960
961 static void hardware_disable(void *garbage)
962 {
963 asm volatile (ASM_VMX_VMXOFF : : : "cc");
964 }
965
966 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
967 u32 msr, u32 *result)
968 {
969 u32 vmx_msr_low, vmx_msr_high;
970 u32 ctl = ctl_min | ctl_opt;
971
972 rdmsr(msr, vmx_msr_low, vmx_msr_high);
973
974 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
975 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
976
977 /* Ensure minimum (required) set of control bits are supported. */
978 if (ctl_min & ~ctl)
979 return -EIO;
980
981 *result = ctl;
982 return 0;
983 }
984
985 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
986 {
987 u32 vmx_msr_low, vmx_msr_high;
988 u32 min, opt;
989 u32 _pin_based_exec_control = 0;
990 u32 _cpu_based_exec_control = 0;
991 u32 _cpu_based_2nd_exec_control = 0;
992 u32 _vmexit_control = 0;
993 u32 _vmentry_control = 0;
994
995 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
996 opt = 0;
997 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
998 &_pin_based_exec_control) < 0)
999 return -EIO;
1000
1001 min = CPU_BASED_HLT_EXITING |
1002 #ifdef CONFIG_X86_64
1003 CPU_BASED_CR8_LOAD_EXITING |
1004 CPU_BASED_CR8_STORE_EXITING |
1005 #endif
1006 CPU_BASED_USE_IO_BITMAPS |
1007 CPU_BASED_MOV_DR_EXITING |
1008 CPU_BASED_USE_TSC_OFFSETING;
1009 opt = CPU_BASED_TPR_SHADOW |
1010 CPU_BASED_USE_MSR_BITMAPS |
1011 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1012 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1013 &_cpu_based_exec_control) < 0)
1014 return -EIO;
1015 #ifdef CONFIG_X86_64
1016 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1017 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1018 ~CPU_BASED_CR8_STORE_EXITING;
1019 #endif
1020 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1021 min = 0;
1022 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1023 SECONDARY_EXEC_WBINVD_EXITING |
1024 SECONDARY_EXEC_ENABLE_VPID;
1025 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
1026 &_cpu_based_2nd_exec_control) < 0)
1027 return -EIO;
1028 }
1029 #ifndef CONFIG_X86_64
1030 if (!(_cpu_based_2nd_exec_control &
1031 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1032 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1033 #endif
1034
1035 min = 0;
1036 #ifdef CONFIG_X86_64
1037 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1038 #endif
1039 opt = 0;
1040 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1041 &_vmexit_control) < 0)
1042 return -EIO;
1043
1044 min = opt = 0;
1045 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1046 &_vmentry_control) < 0)
1047 return -EIO;
1048
1049 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1050
1051 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1052 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1053 return -EIO;
1054
1055 #ifdef CONFIG_X86_64
1056 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1057 if (vmx_msr_high & (1u<<16))
1058 return -EIO;
1059 #endif
1060
1061 /* Require Write-Back (WB) memory type for VMCS accesses. */
1062 if (((vmx_msr_high >> 18) & 15) != 6)
1063 return -EIO;
1064
1065 vmcs_conf->size = vmx_msr_high & 0x1fff;
1066 vmcs_conf->order = get_order(vmcs_config.size);
1067 vmcs_conf->revision_id = vmx_msr_low;
1068
1069 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1070 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1071 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1072 vmcs_conf->vmexit_ctrl = _vmexit_control;
1073 vmcs_conf->vmentry_ctrl = _vmentry_control;
1074
1075 return 0;
1076 }
1077
1078 static struct vmcs *alloc_vmcs_cpu(int cpu)
1079 {
1080 int node = cpu_to_node(cpu);
1081 struct page *pages;
1082 struct vmcs *vmcs;
1083
1084 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1085 if (!pages)
1086 return NULL;
1087 vmcs = page_address(pages);
1088 memset(vmcs, 0, vmcs_config.size);
1089 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1090 return vmcs;
1091 }
1092
1093 static struct vmcs *alloc_vmcs(void)
1094 {
1095 return alloc_vmcs_cpu(raw_smp_processor_id());
1096 }
1097
1098 static void free_vmcs(struct vmcs *vmcs)
1099 {
1100 free_pages((unsigned long)vmcs, vmcs_config.order);
1101 }
1102
1103 static void free_kvm_area(void)
1104 {
1105 int cpu;
1106
1107 for_each_online_cpu(cpu)
1108 free_vmcs(per_cpu(vmxarea, cpu));
1109 }
1110
1111 static __init int alloc_kvm_area(void)
1112 {
1113 int cpu;
1114
1115 for_each_online_cpu(cpu) {
1116 struct vmcs *vmcs;
1117
1118 vmcs = alloc_vmcs_cpu(cpu);
1119 if (!vmcs) {
1120 free_kvm_area();
1121 return -ENOMEM;
1122 }
1123
1124 per_cpu(vmxarea, cpu) = vmcs;
1125 }
1126 return 0;
1127 }
1128
1129 static __init int hardware_setup(void)
1130 {
1131 if (setup_vmcs_config(&vmcs_config) < 0)
1132 return -EIO;
1133
1134 if (boot_cpu_has(X86_FEATURE_NX))
1135 kvm_enable_efer_bits(EFER_NX);
1136
1137 return alloc_kvm_area();
1138 }
1139
1140 static __exit void hardware_unsetup(void)
1141 {
1142 free_kvm_area();
1143 }
1144
1145 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1146 {
1147 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1148
1149 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1150 vmcs_write16(sf->selector, save->selector);
1151 vmcs_writel(sf->base, save->base);
1152 vmcs_write32(sf->limit, save->limit);
1153 vmcs_write32(sf->ar_bytes, save->ar);
1154 } else {
1155 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1156 << AR_DPL_SHIFT;
1157 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1158 }
1159 }
1160
1161 static void enter_pmode(struct kvm_vcpu *vcpu)
1162 {
1163 unsigned long flags;
1164
1165 vcpu->arch.rmode.active = 0;
1166
1167 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1168 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1169 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1170
1171 flags = vmcs_readl(GUEST_RFLAGS);
1172 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1173 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1174 vmcs_writel(GUEST_RFLAGS, flags);
1175
1176 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1177 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1178
1179 update_exception_bitmap(vcpu);
1180
1181 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1182 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1183 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1184 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1185
1186 vmcs_write16(GUEST_SS_SELECTOR, 0);
1187 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1188
1189 vmcs_write16(GUEST_CS_SELECTOR,
1190 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1191 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1192 }
1193
1194 static gva_t rmode_tss_base(struct kvm *kvm)
1195 {
1196 if (!kvm->arch.tss_addr) {
1197 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1198 kvm->memslots[0].npages - 3;
1199 return base_gfn << PAGE_SHIFT;
1200 }
1201 return kvm->arch.tss_addr;
1202 }
1203
1204 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1205 {
1206 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1207
1208 save->selector = vmcs_read16(sf->selector);
1209 save->base = vmcs_readl(sf->base);
1210 save->limit = vmcs_read32(sf->limit);
1211 save->ar = vmcs_read32(sf->ar_bytes);
1212 vmcs_write16(sf->selector, save->base >> 4);
1213 vmcs_write32(sf->base, save->base & 0xfffff);
1214 vmcs_write32(sf->limit, 0xffff);
1215 vmcs_write32(sf->ar_bytes, 0xf3);
1216 }
1217
1218 static void enter_rmode(struct kvm_vcpu *vcpu)
1219 {
1220 unsigned long flags;
1221
1222 vcpu->arch.rmode.active = 1;
1223
1224 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1225 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1226
1227 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1228 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1229
1230 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1231 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1232
1233 flags = vmcs_readl(GUEST_RFLAGS);
1234 vcpu->arch.rmode.save_iopl
1235 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1236
1237 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1238
1239 vmcs_writel(GUEST_RFLAGS, flags);
1240 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1241 update_exception_bitmap(vcpu);
1242
1243 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1244 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1245 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1246
1247 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1248 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1249 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1250 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1251 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1252
1253 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1254 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1255 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1256 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1257
1258 kvm_mmu_reset_context(vcpu);
1259 init_rmode_tss(vcpu->kvm);
1260 }
1261
1262 #ifdef CONFIG_X86_64
1263
1264 static void enter_lmode(struct kvm_vcpu *vcpu)
1265 {
1266 u32 guest_tr_ar;
1267
1268 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1269 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1270 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1271 __func__);
1272 vmcs_write32(GUEST_TR_AR_BYTES,
1273 (guest_tr_ar & ~AR_TYPE_MASK)
1274 | AR_TYPE_BUSY_64_TSS);
1275 }
1276
1277 vcpu->arch.shadow_efer |= EFER_LMA;
1278
1279 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1280 vmcs_write32(VM_ENTRY_CONTROLS,
1281 vmcs_read32(VM_ENTRY_CONTROLS)
1282 | VM_ENTRY_IA32E_MODE);
1283 }
1284
1285 static void exit_lmode(struct kvm_vcpu *vcpu)
1286 {
1287 vcpu->arch.shadow_efer &= ~EFER_LMA;
1288
1289 vmcs_write32(VM_ENTRY_CONTROLS,
1290 vmcs_read32(VM_ENTRY_CONTROLS)
1291 & ~VM_ENTRY_IA32E_MODE);
1292 }
1293
1294 #endif
1295
1296 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1297 {
1298 vpid_sync_vcpu_all(to_vmx(vcpu));
1299 }
1300
1301 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1302 {
1303 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1304 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1305 }
1306
1307 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1308 {
1309 vmx_fpu_deactivate(vcpu);
1310
1311 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1312 enter_pmode(vcpu);
1313
1314 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1315 enter_rmode(vcpu);
1316
1317 #ifdef CONFIG_X86_64
1318 if (vcpu->arch.shadow_efer & EFER_LME) {
1319 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1320 enter_lmode(vcpu);
1321 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1322 exit_lmode(vcpu);
1323 }
1324 #endif
1325
1326 vmcs_writel(CR0_READ_SHADOW, cr0);
1327 vmcs_writel(GUEST_CR0,
1328 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1329 vcpu->arch.cr0 = cr0;
1330
1331 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1332 vmx_fpu_activate(vcpu);
1333 }
1334
1335 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1336 {
1337 vmx_flush_tlb(vcpu);
1338 vmcs_writel(GUEST_CR3, cr3);
1339 if (vcpu->arch.cr0 & X86_CR0_PE)
1340 vmx_fpu_deactivate(vcpu);
1341 }
1342
1343 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1344 {
1345 vmcs_writel(CR4_READ_SHADOW, cr4);
1346 vmcs_writel(GUEST_CR4, cr4 | (vcpu->arch.rmode.active ?
1347 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1348 vcpu->arch.cr4 = cr4;
1349 }
1350
1351 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1352 {
1353 struct vcpu_vmx *vmx = to_vmx(vcpu);
1354 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1355
1356 vcpu->arch.shadow_efer = efer;
1357 if (!msr)
1358 return;
1359 if (efer & EFER_LMA) {
1360 vmcs_write32(VM_ENTRY_CONTROLS,
1361 vmcs_read32(VM_ENTRY_CONTROLS) |
1362 VM_ENTRY_IA32E_MODE);
1363 msr->data = efer;
1364
1365 } else {
1366 vmcs_write32(VM_ENTRY_CONTROLS,
1367 vmcs_read32(VM_ENTRY_CONTROLS) &
1368 ~VM_ENTRY_IA32E_MODE);
1369
1370 msr->data = efer & ~EFER_LME;
1371 }
1372 setup_msrs(vmx);
1373 }
1374
1375 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1376 {
1377 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1378
1379 return vmcs_readl(sf->base);
1380 }
1381
1382 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1383 struct kvm_segment *var, int seg)
1384 {
1385 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1386 u32 ar;
1387
1388 var->base = vmcs_readl(sf->base);
1389 var->limit = vmcs_read32(sf->limit);
1390 var->selector = vmcs_read16(sf->selector);
1391 ar = vmcs_read32(sf->ar_bytes);
1392 if (ar & AR_UNUSABLE_MASK)
1393 ar = 0;
1394 var->type = ar & 15;
1395 var->s = (ar >> 4) & 1;
1396 var->dpl = (ar >> 5) & 3;
1397 var->present = (ar >> 7) & 1;
1398 var->avl = (ar >> 12) & 1;
1399 var->l = (ar >> 13) & 1;
1400 var->db = (ar >> 14) & 1;
1401 var->g = (ar >> 15) & 1;
1402 var->unusable = (ar >> 16) & 1;
1403 }
1404
1405 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1406 {
1407 struct kvm_segment kvm_seg;
1408
1409 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1410 return 0;
1411
1412 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1413 return 3;
1414
1415 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1416 return kvm_seg.selector & 3;
1417 }
1418
1419 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1420 {
1421 u32 ar;
1422
1423 if (var->unusable)
1424 ar = 1 << 16;
1425 else {
1426 ar = var->type & 15;
1427 ar |= (var->s & 1) << 4;
1428 ar |= (var->dpl & 3) << 5;
1429 ar |= (var->present & 1) << 7;
1430 ar |= (var->avl & 1) << 12;
1431 ar |= (var->l & 1) << 13;
1432 ar |= (var->db & 1) << 14;
1433 ar |= (var->g & 1) << 15;
1434 }
1435 if (ar == 0) /* a 0 value means unusable */
1436 ar = AR_UNUSABLE_MASK;
1437
1438 return ar;
1439 }
1440
1441 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1442 struct kvm_segment *var, int seg)
1443 {
1444 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1445 u32 ar;
1446
1447 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1448 vcpu->arch.rmode.tr.selector = var->selector;
1449 vcpu->arch.rmode.tr.base = var->base;
1450 vcpu->arch.rmode.tr.limit = var->limit;
1451 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1452 return;
1453 }
1454 vmcs_writel(sf->base, var->base);
1455 vmcs_write32(sf->limit, var->limit);
1456 vmcs_write16(sf->selector, var->selector);
1457 if (vcpu->arch.rmode.active && var->s) {
1458 /*
1459 * Hack real-mode segments into vm86 compatibility.
1460 */
1461 if (var->base == 0xffff0000 && var->selector == 0xf000)
1462 vmcs_writel(sf->base, 0xf0000);
1463 ar = 0xf3;
1464 } else
1465 ar = vmx_segment_access_rights(var);
1466 vmcs_write32(sf->ar_bytes, ar);
1467 }
1468
1469 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1470 {
1471 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1472
1473 *db = (ar >> 14) & 1;
1474 *l = (ar >> 13) & 1;
1475 }
1476
1477 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1478 {
1479 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1480 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1481 }
1482
1483 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1484 {
1485 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1486 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1487 }
1488
1489 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1490 {
1491 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1492 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1493 }
1494
1495 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1496 {
1497 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1498 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1499 }
1500
1501 static int init_rmode_tss(struct kvm *kvm)
1502 {
1503 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1504 u16 data = 0;
1505 int ret = 0;
1506 int r;
1507
1508 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1509 if (r < 0)
1510 goto out;
1511 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1512 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1513 if (r < 0)
1514 goto out;
1515 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1516 if (r < 0)
1517 goto out;
1518 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1519 if (r < 0)
1520 goto out;
1521 data = ~0;
1522 r = kvm_write_guest_page(kvm, fn, &data,
1523 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1524 sizeof(u8));
1525 if (r < 0)
1526 goto out;
1527
1528 ret = 1;
1529 out:
1530 return ret;
1531 }
1532
1533 static void seg_setup(int seg)
1534 {
1535 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1536
1537 vmcs_write16(sf->selector, 0);
1538 vmcs_writel(sf->base, 0);
1539 vmcs_write32(sf->limit, 0xffff);
1540 vmcs_write32(sf->ar_bytes, 0x93);
1541 }
1542
1543 static int alloc_apic_access_page(struct kvm *kvm)
1544 {
1545 struct kvm_userspace_memory_region kvm_userspace_mem;
1546 int r = 0;
1547
1548 down_write(&kvm->slots_lock);
1549 if (kvm->arch.apic_access_page)
1550 goto out;
1551 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1552 kvm_userspace_mem.flags = 0;
1553 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1554 kvm_userspace_mem.memory_size = PAGE_SIZE;
1555 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1556 if (r)
1557 goto out;
1558
1559 down_read(&current->mm->mmap_sem);
1560 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
1561 up_read(&current->mm->mmap_sem);
1562 out:
1563 up_write(&kvm->slots_lock);
1564 return r;
1565 }
1566
1567 static void allocate_vpid(struct vcpu_vmx *vmx)
1568 {
1569 int vpid;
1570
1571 vmx->vpid = 0;
1572 if (!enable_vpid || !cpu_has_vmx_vpid())
1573 return;
1574 spin_lock(&vmx_vpid_lock);
1575 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
1576 if (vpid < VMX_NR_VPIDS) {
1577 vmx->vpid = vpid;
1578 __set_bit(vpid, vmx_vpid_bitmap);
1579 }
1580 spin_unlock(&vmx_vpid_lock);
1581 }
1582
1583 void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr)
1584 {
1585 void *va;
1586
1587 if (!cpu_has_vmx_msr_bitmap())
1588 return;
1589
1590 /*
1591 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
1592 * have the write-low and read-high bitmap offsets the wrong way round.
1593 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
1594 */
1595 va = kmap(msr_bitmap);
1596 if (msr <= 0x1fff) {
1597 __clear_bit(msr, va + 0x000); /* read-low */
1598 __clear_bit(msr, va + 0x800); /* write-low */
1599 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
1600 msr &= 0x1fff;
1601 __clear_bit(msr, va + 0x400); /* read-high */
1602 __clear_bit(msr, va + 0xc00); /* write-high */
1603 }
1604 kunmap(msr_bitmap);
1605 }
1606
1607 /*
1608 * Sets up the vmcs for emulated real mode.
1609 */
1610 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1611 {
1612 u32 host_sysenter_cs;
1613 u32 junk;
1614 unsigned long a;
1615 struct descriptor_table dt;
1616 int i;
1617 unsigned long kvm_vmx_return;
1618 u32 exec_control;
1619
1620 /* I/O */
1621 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1622 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1623
1624 if (cpu_has_vmx_msr_bitmap())
1625 vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap));
1626
1627 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1628
1629 /* Control */
1630 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1631 vmcs_config.pin_based_exec_ctrl);
1632
1633 exec_control = vmcs_config.cpu_based_exec_ctrl;
1634 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1635 exec_control &= ~CPU_BASED_TPR_SHADOW;
1636 #ifdef CONFIG_X86_64
1637 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1638 CPU_BASED_CR8_LOAD_EXITING;
1639 #endif
1640 }
1641 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1642
1643 if (cpu_has_secondary_exec_ctrls()) {
1644 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1645 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1646 exec_control &=
1647 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1648 if (vmx->vpid == 0)
1649 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
1650 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1651 }
1652
1653 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1654 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1655 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1656
1657 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1658 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1659 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1660
1661 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1662 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1663 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1664 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1665 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1666 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1667 #ifdef CONFIG_X86_64
1668 rdmsrl(MSR_FS_BASE, a);
1669 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1670 rdmsrl(MSR_GS_BASE, a);
1671 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1672 #else
1673 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1674 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1675 #endif
1676
1677 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1678
1679 get_idt(&dt);
1680 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1681
1682 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1683 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1684 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1685 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1686 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1687
1688 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1689 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1690 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1691 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1692 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1693 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1694
1695 for (i = 0; i < NR_VMX_MSR; ++i) {
1696 u32 index = vmx_msr_index[i];
1697 u32 data_low, data_high;
1698 u64 data;
1699 int j = vmx->nmsrs;
1700
1701 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1702 continue;
1703 if (wrmsr_safe(index, data_low, data_high) < 0)
1704 continue;
1705 data = data_low | ((u64)data_high << 32);
1706 vmx->host_msrs[j].index = index;
1707 vmx->host_msrs[j].reserved = 0;
1708 vmx->host_msrs[j].data = data;
1709 vmx->guest_msrs[j] = vmx->host_msrs[j];
1710 ++vmx->nmsrs;
1711 }
1712
1713 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1714
1715 /* 22.2.1, 20.8.1 */
1716 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1717
1718 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1719 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1720
1721
1722 return 0;
1723 }
1724
1725 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1726 {
1727 struct vcpu_vmx *vmx = to_vmx(vcpu);
1728 u64 msr;
1729 int ret;
1730
1731 down_read(&vcpu->kvm->slots_lock);
1732 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1733 ret = -ENOMEM;
1734 goto out;
1735 }
1736
1737 vmx->vcpu.arch.rmode.active = 0;
1738
1739 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1740 kvm_set_cr8(&vmx->vcpu, 0);
1741 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1742 if (vmx->vcpu.vcpu_id == 0)
1743 msr |= MSR_IA32_APICBASE_BSP;
1744 kvm_set_apic_base(&vmx->vcpu, msr);
1745
1746 fx_init(&vmx->vcpu);
1747
1748 /*
1749 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1750 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1751 */
1752 if (vmx->vcpu.vcpu_id == 0) {
1753 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1754 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1755 } else {
1756 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
1757 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
1758 }
1759 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1760 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1761
1762 seg_setup(VCPU_SREG_DS);
1763 seg_setup(VCPU_SREG_ES);
1764 seg_setup(VCPU_SREG_FS);
1765 seg_setup(VCPU_SREG_GS);
1766 seg_setup(VCPU_SREG_SS);
1767
1768 vmcs_write16(GUEST_TR_SELECTOR, 0);
1769 vmcs_writel(GUEST_TR_BASE, 0);
1770 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1771 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1772
1773 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1774 vmcs_writel(GUEST_LDTR_BASE, 0);
1775 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1776 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1777
1778 vmcs_write32(GUEST_SYSENTER_CS, 0);
1779 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1780 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1781
1782 vmcs_writel(GUEST_RFLAGS, 0x02);
1783 if (vmx->vcpu.vcpu_id == 0)
1784 vmcs_writel(GUEST_RIP, 0xfff0);
1785 else
1786 vmcs_writel(GUEST_RIP, 0);
1787 vmcs_writel(GUEST_RSP, 0);
1788
1789 /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1790 vmcs_writel(GUEST_DR7, 0x400);
1791
1792 vmcs_writel(GUEST_GDTR_BASE, 0);
1793 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1794
1795 vmcs_writel(GUEST_IDTR_BASE, 0);
1796 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1797
1798 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1799 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1800 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1801
1802 guest_write_tsc(0);
1803
1804 /* Special registers */
1805 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1806
1807 setup_msrs(vmx);
1808
1809 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1810
1811 if (cpu_has_vmx_tpr_shadow()) {
1812 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1813 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1814 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1815 page_to_phys(vmx->vcpu.arch.apic->regs_page));
1816 vmcs_write32(TPR_THRESHOLD, 0);
1817 }
1818
1819 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1820 vmcs_write64(APIC_ACCESS_ADDR,
1821 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
1822
1823 if (vmx->vpid != 0)
1824 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
1825
1826 vmx->vcpu.arch.cr0 = 0x60000010;
1827 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
1828 vmx_set_cr4(&vmx->vcpu, 0);
1829 vmx_set_efer(&vmx->vcpu, 0);
1830 vmx_fpu_activate(&vmx->vcpu);
1831 update_exception_bitmap(&vmx->vcpu);
1832
1833 vpid_sync_vcpu_all(vmx);
1834
1835 ret = 0;
1836
1837 out:
1838 up_read(&vcpu->kvm->slots_lock);
1839 return ret;
1840 }
1841
1842 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1843 {
1844 struct vcpu_vmx *vmx = to_vmx(vcpu);
1845
1846 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
1847
1848 if (vcpu->arch.rmode.active) {
1849 vmx->rmode.irq.pending = true;
1850 vmx->rmode.irq.vector = irq;
1851 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1852 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1853 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1854 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1855 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1856 return;
1857 }
1858 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1859 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1860 }
1861
1862 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1863 {
1864 int word_index = __ffs(vcpu->arch.irq_summary);
1865 int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1866 int irq = word_index * BITS_PER_LONG + bit_index;
1867
1868 clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1869 if (!vcpu->arch.irq_pending[word_index])
1870 clear_bit(word_index, &vcpu->arch.irq_summary);
1871 vmx_inject_irq(vcpu, irq);
1872 }
1873
1874
1875 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1876 struct kvm_run *kvm_run)
1877 {
1878 u32 cpu_based_vm_exec_control;
1879
1880 vcpu->arch.interrupt_window_open =
1881 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1882 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1883
1884 if (vcpu->arch.interrupt_window_open &&
1885 vcpu->arch.irq_summary &&
1886 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1887 /*
1888 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1889 */
1890 kvm_do_inject_irq(vcpu);
1891
1892 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1893 if (!vcpu->arch.interrupt_window_open &&
1894 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
1895 /*
1896 * Interrupts blocked. Wait for unblock.
1897 */
1898 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1899 else
1900 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1901 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1902 }
1903
1904 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1905 {
1906 int ret;
1907 struct kvm_userspace_memory_region tss_mem = {
1908 .slot = 8,
1909 .guest_phys_addr = addr,
1910 .memory_size = PAGE_SIZE * 3,
1911 .flags = 0,
1912 };
1913
1914 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1915 if (ret)
1916 return ret;
1917 kvm->arch.tss_addr = addr;
1918 return 0;
1919 }
1920
1921 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1922 {
1923 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1924
1925 set_debugreg(dbg->bp[0], 0);
1926 set_debugreg(dbg->bp[1], 1);
1927 set_debugreg(dbg->bp[2], 2);
1928 set_debugreg(dbg->bp[3], 3);
1929
1930 if (dbg->singlestep) {
1931 unsigned long flags;
1932
1933 flags = vmcs_readl(GUEST_RFLAGS);
1934 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1935 vmcs_writel(GUEST_RFLAGS, flags);
1936 }
1937 }
1938
1939 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1940 int vec, u32 err_code)
1941 {
1942 if (!vcpu->arch.rmode.active)
1943 return 0;
1944
1945 /*
1946 * Instruction with address size override prefix opcode 0x67
1947 * Cause the #SS fault with 0 error code in VM86 mode.
1948 */
1949 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1950 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1951 return 1;
1952 return 0;
1953 }
1954
1955 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1956 {
1957 struct vcpu_vmx *vmx = to_vmx(vcpu);
1958 u32 intr_info, error_code;
1959 unsigned long cr2, rip;
1960 u32 vect_info;
1961 enum emulation_result er;
1962
1963 vect_info = vmx->idt_vectoring_info;
1964 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1965
1966 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1967 !is_page_fault(intr_info))
1968 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1969 "intr info 0x%x\n", __func__, vect_info, intr_info);
1970
1971 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1972 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1973 set_bit(irq, vcpu->arch.irq_pending);
1974 set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
1975 }
1976
1977 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1978 return 1; /* already handled by vmx_vcpu_run() */
1979
1980 if (is_no_device(intr_info)) {
1981 vmx_fpu_activate(vcpu);
1982 return 1;
1983 }
1984
1985 if (is_invalid_opcode(intr_info)) {
1986 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1987 if (er != EMULATE_DONE)
1988 kvm_queue_exception(vcpu, UD_VECTOR);
1989 return 1;
1990 }
1991
1992 error_code = 0;
1993 rip = vmcs_readl(GUEST_RIP);
1994 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
1995 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1996 if (is_page_fault(intr_info)) {
1997 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1998 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
1999 (u32)((u64)cr2 >> 32), handler);
2000 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2001 }
2002
2003 if (vcpu->arch.rmode.active &&
2004 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2005 error_code)) {
2006 if (vcpu->arch.halt_request) {
2007 vcpu->arch.halt_request = 0;
2008 return kvm_emulate_halt(vcpu);
2009 }
2010 return 1;
2011 }
2012
2013 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
2014 (INTR_TYPE_EXCEPTION | 1)) {
2015 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2016 return 0;
2017 }
2018 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2019 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
2020 kvm_run->ex.error_code = error_code;
2021 return 0;
2022 }
2023
2024 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2025 struct kvm_run *kvm_run)
2026 {
2027 ++vcpu->stat.irq_exits;
2028 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2029 return 1;
2030 }
2031
2032 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2033 {
2034 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2035 return 0;
2036 }
2037
2038 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2039 {
2040 unsigned long exit_qualification;
2041 int size, down, in, string, rep;
2042 unsigned port;
2043
2044 ++vcpu->stat.io_exits;
2045 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2046 string = (exit_qualification & 16) != 0;
2047
2048 if (string) {
2049 if (emulate_instruction(vcpu,
2050 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2051 return 0;
2052 return 1;
2053 }
2054
2055 size = (exit_qualification & 7) + 1;
2056 in = (exit_qualification & 8) != 0;
2057 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
2058 rep = (exit_qualification & 32) != 0;
2059 port = exit_qualification >> 16;
2060
2061 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2062 }
2063
2064 static void
2065 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2066 {
2067 /*
2068 * Patch in the VMCALL instruction:
2069 */
2070 hypercall[0] = 0x0f;
2071 hypercall[1] = 0x01;
2072 hypercall[2] = 0xc1;
2073 }
2074
2075 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2076 {
2077 unsigned long exit_qualification;
2078 int cr;
2079 int reg;
2080
2081 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2082 cr = exit_qualification & 15;
2083 reg = (exit_qualification >> 8) & 15;
2084 switch ((exit_qualification >> 4) & 3) {
2085 case 0: /* mov to cr */
2086 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)vcpu->arch.regs[reg],
2087 (u32)((u64)vcpu->arch.regs[reg] >> 32), handler);
2088 switch (cr) {
2089 case 0:
2090 vcpu_load_rsp_rip(vcpu);
2091 kvm_set_cr0(vcpu, vcpu->arch.regs[reg]);
2092 skip_emulated_instruction(vcpu);
2093 return 1;
2094 case 3:
2095 vcpu_load_rsp_rip(vcpu);
2096 kvm_set_cr3(vcpu, vcpu->arch.regs[reg]);
2097 skip_emulated_instruction(vcpu);
2098 return 1;
2099 case 4:
2100 vcpu_load_rsp_rip(vcpu);
2101 kvm_set_cr4(vcpu, vcpu->arch.regs[reg]);
2102 skip_emulated_instruction(vcpu);
2103 return 1;
2104 case 8:
2105 vcpu_load_rsp_rip(vcpu);
2106 kvm_set_cr8(vcpu, vcpu->arch.regs[reg]);
2107 skip_emulated_instruction(vcpu);
2108 if (irqchip_in_kernel(vcpu->kvm))
2109 return 1;
2110 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2111 return 0;
2112 };
2113 break;
2114 case 2: /* clts */
2115 vcpu_load_rsp_rip(vcpu);
2116 vmx_fpu_deactivate(vcpu);
2117 vcpu->arch.cr0 &= ~X86_CR0_TS;
2118 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2119 vmx_fpu_activate(vcpu);
2120 KVMTRACE_0D(CLTS, vcpu, handler);
2121 skip_emulated_instruction(vcpu);
2122 return 1;
2123 case 1: /*mov from cr*/
2124 switch (cr) {
2125 case 3:
2126 vcpu_load_rsp_rip(vcpu);
2127 vcpu->arch.regs[reg] = vcpu->arch.cr3;
2128 vcpu_put_rsp_rip(vcpu);
2129 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2130 (u32)vcpu->arch.regs[reg],
2131 (u32)((u64)vcpu->arch.regs[reg] >> 32),
2132 handler);
2133 skip_emulated_instruction(vcpu);
2134 return 1;
2135 case 8:
2136 vcpu_load_rsp_rip(vcpu);
2137 vcpu->arch.regs[reg] = kvm_get_cr8(vcpu);
2138 vcpu_put_rsp_rip(vcpu);
2139 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2140 (u32)vcpu->arch.regs[reg], handler);
2141 skip_emulated_instruction(vcpu);
2142 return 1;
2143 }
2144 break;
2145 case 3: /* lmsw */
2146 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2147
2148 skip_emulated_instruction(vcpu);
2149 return 1;
2150 default:
2151 break;
2152 }
2153 kvm_run->exit_reason = 0;
2154 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2155 (int)(exit_qualification >> 4) & 3, cr);
2156 return 0;
2157 }
2158
2159 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2160 {
2161 unsigned long exit_qualification;
2162 unsigned long val;
2163 int dr, reg;
2164
2165 /*
2166 * FIXME: this code assumes the host is debugging the guest.
2167 * need to deal with guest debugging itself too.
2168 */
2169 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2170 dr = exit_qualification & 7;
2171 reg = (exit_qualification >> 8) & 15;
2172 vcpu_load_rsp_rip(vcpu);
2173 if (exit_qualification & 16) {
2174 /* mov from dr */
2175 switch (dr) {
2176 case 6:
2177 val = 0xffff0ff0;
2178 break;
2179 case 7:
2180 val = 0x400;
2181 break;
2182 default:
2183 val = 0;
2184 }
2185 vcpu->arch.regs[reg] = val;
2186 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2187 } else {
2188 /* mov to dr */
2189 }
2190 vcpu_put_rsp_rip(vcpu);
2191 skip_emulated_instruction(vcpu);
2192 return 1;
2193 }
2194
2195 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2196 {
2197 kvm_emulate_cpuid(vcpu);
2198 return 1;
2199 }
2200
2201 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2202 {
2203 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2204 u64 data;
2205
2206 if (vmx_get_msr(vcpu, ecx, &data)) {
2207 kvm_inject_gp(vcpu, 0);
2208 return 1;
2209 }
2210
2211 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2212 handler);
2213
2214 /* FIXME: handling of bits 32:63 of rax, rdx */
2215 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2216 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2217 skip_emulated_instruction(vcpu);
2218 return 1;
2219 }
2220
2221 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2222 {
2223 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2224 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2225 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2226
2227 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2228 handler);
2229
2230 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2231 kvm_inject_gp(vcpu, 0);
2232 return 1;
2233 }
2234
2235 skip_emulated_instruction(vcpu);
2236 return 1;
2237 }
2238
2239 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2240 struct kvm_run *kvm_run)
2241 {
2242 return 1;
2243 }
2244
2245 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2246 struct kvm_run *kvm_run)
2247 {
2248 u32 cpu_based_vm_exec_control;
2249
2250 /* clear pending irq */
2251 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2252 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2253 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2254
2255 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2256
2257 /*
2258 * If the user space waits to inject interrupts, exit as soon as
2259 * possible
2260 */
2261 if (kvm_run->request_interrupt_window &&
2262 !vcpu->arch.irq_summary) {
2263 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2264 ++vcpu->stat.irq_window_exits;
2265 return 0;
2266 }
2267 return 1;
2268 }
2269
2270 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2271 {
2272 skip_emulated_instruction(vcpu);
2273 return kvm_emulate_halt(vcpu);
2274 }
2275
2276 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2277 {
2278 skip_emulated_instruction(vcpu);
2279 kvm_emulate_hypercall(vcpu);
2280 return 1;
2281 }
2282
2283 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2284 {
2285 skip_emulated_instruction(vcpu);
2286 /* TODO: Add support for VT-d/pass-through device */
2287 return 1;
2288 }
2289
2290 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2291 {
2292 u64 exit_qualification;
2293 enum emulation_result er;
2294 unsigned long offset;
2295
2296 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2297 offset = exit_qualification & 0xffful;
2298
2299 KVMTRACE_1D(APIC_ACCESS, vcpu, (u32)offset, handler);
2300
2301 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2302
2303 if (er != EMULATE_DONE) {
2304 printk(KERN_ERR
2305 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2306 offset);
2307 return -ENOTSUPP;
2308 }
2309 return 1;
2310 }
2311
2312 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2313 {
2314 unsigned long exit_qualification;
2315 u16 tss_selector;
2316 int reason;
2317
2318 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2319
2320 reason = (u32)exit_qualification >> 30;
2321 tss_selector = exit_qualification;
2322
2323 return kvm_task_switch(vcpu, tss_selector, reason);
2324 }
2325
2326 /*
2327 * The exit handlers return 1 if the exit was handled fully and guest execution
2328 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2329 * to be done to userspace and return 0.
2330 */
2331 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2332 struct kvm_run *kvm_run) = {
2333 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2334 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2335 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2336 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2337 [EXIT_REASON_CR_ACCESS] = handle_cr,
2338 [EXIT_REASON_DR_ACCESS] = handle_dr,
2339 [EXIT_REASON_CPUID] = handle_cpuid,
2340 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2341 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2342 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2343 [EXIT_REASON_HLT] = handle_halt,
2344 [EXIT_REASON_VMCALL] = handle_vmcall,
2345 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
2346 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
2347 [EXIT_REASON_WBINVD] = handle_wbinvd,
2348 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
2349 };
2350
2351 static const int kvm_vmx_max_exit_handlers =
2352 ARRAY_SIZE(kvm_vmx_exit_handlers);
2353
2354 /*
2355 * The guest has exited. See if we can fix it or if we need userspace
2356 * assistance.
2357 */
2358 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2359 {
2360 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2361 struct vcpu_vmx *vmx = to_vmx(vcpu);
2362 u32 vectoring_info = vmx->idt_vectoring_info;
2363
2364 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)vmcs_readl(GUEST_RIP),
2365 (u32)((u64)vmcs_readl(GUEST_RIP) >> 32), entryexit);
2366
2367 if (unlikely(vmx->fail)) {
2368 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2369 kvm_run->fail_entry.hardware_entry_failure_reason
2370 = vmcs_read32(VM_INSTRUCTION_ERROR);
2371 return 0;
2372 }
2373
2374 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2375 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2376 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2377 "exit reason is 0x%x\n", __func__, exit_reason);
2378 if (exit_reason < kvm_vmx_max_exit_handlers
2379 && kvm_vmx_exit_handlers[exit_reason])
2380 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2381 else {
2382 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2383 kvm_run->hw.hardware_exit_reason = exit_reason;
2384 }
2385 return 0;
2386 }
2387
2388 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2389 {
2390 int max_irr, tpr;
2391
2392 if (!vm_need_tpr_shadow(vcpu->kvm))
2393 return;
2394
2395 if (!kvm_lapic_enabled(vcpu) ||
2396 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2397 vmcs_write32(TPR_THRESHOLD, 0);
2398 return;
2399 }
2400
2401 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2402 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2403 }
2404
2405 static void enable_irq_window(struct kvm_vcpu *vcpu)
2406 {
2407 u32 cpu_based_vm_exec_control;
2408
2409 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2410 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2411 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2412 }
2413
2414 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2415 {
2416 struct vcpu_vmx *vmx = to_vmx(vcpu);
2417 u32 idtv_info_field, intr_info_field;
2418 int has_ext_irq, interrupt_window_open;
2419 int vector;
2420
2421 update_tpr_threshold(vcpu);
2422
2423 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2424 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2425 idtv_info_field = vmx->idt_vectoring_info;
2426 if (intr_info_field & INTR_INFO_VALID_MASK) {
2427 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2428 /* TODO: fault when IDT_Vectoring */
2429 if (printk_ratelimit())
2430 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2431 }
2432 if (has_ext_irq)
2433 enable_irq_window(vcpu);
2434 return;
2435 }
2436 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2437 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2438 == INTR_TYPE_EXT_INTR
2439 && vcpu->arch.rmode.active) {
2440 u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2441
2442 vmx_inject_irq(vcpu, vect);
2443 if (unlikely(has_ext_irq))
2444 enable_irq_window(vcpu);
2445 return;
2446 }
2447
2448 KVMTRACE_1D(REDELIVER_EVT, vcpu, idtv_info_field, handler);
2449
2450 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2451 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2452 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2453
2454 if (unlikely(idtv_info_field & INTR_INFO_DELIVER_CODE_MASK))
2455 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2456 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2457 if (unlikely(has_ext_irq))
2458 enable_irq_window(vcpu);
2459 return;
2460 }
2461 if (!has_ext_irq)
2462 return;
2463 interrupt_window_open =
2464 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2465 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2466 if (interrupt_window_open) {
2467 vector = kvm_cpu_get_interrupt(vcpu);
2468 vmx_inject_irq(vcpu, vector);
2469 kvm_timer_intr_post(vcpu, vector);
2470 } else
2471 enable_irq_window(vcpu);
2472 }
2473
2474 /*
2475 * Failure to inject an interrupt should give us the information
2476 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
2477 * when fetching the interrupt redirection bitmap in the real-mode
2478 * tss, this doesn't happen. So we do it ourselves.
2479 */
2480 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2481 {
2482 vmx->rmode.irq.pending = 0;
2483 if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2484 return;
2485 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2486 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2487 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2488 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2489 return;
2490 }
2491 vmx->idt_vectoring_info =
2492 VECTORING_INFO_VALID_MASK
2493 | INTR_TYPE_EXT_INTR
2494 | vmx->rmode.irq.vector;
2495 }
2496
2497 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2498 {
2499 struct vcpu_vmx *vmx = to_vmx(vcpu);
2500 u32 intr_info;
2501
2502 /*
2503 * Loading guest fpu may have cleared host cr0.ts
2504 */
2505 vmcs_writel(HOST_CR0, read_cr0());
2506
2507 asm(
2508 /* Store host registers */
2509 #ifdef CONFIG_X86_64
2510 "push %%rdx; push %%rbp;"
2511 "push %%rcx \n\t"
2512 #else
2513 "push %%edx; push %%ebp;"
2514 "push %%ecx \n\t"
2515 #endif
2516 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2517 /* Check if vmlaunch of vmresume is needed */
2518 "cmpl $0, %c[launched](%0) \n\t"
2519 /* Load guest registers. Don't clobber flags. */
2520 #ifdef CONFIG_X86_64
2521 "mov %c[cr2](%0), %%rax \n\t"
2522 "mov %%rax, %%cr2 \n\t"
2523 "mov %c[rax](%0), %%rax \n\t"
2524 "mov %c[rbx](%0), %%rbx \n\t"
2525 "mov %c[rdx](%0), %%rdx \n\t"
2526 "mov %c[rsi](%0), %%rsi \n\t"
2527 "mov %c[rdi](%0), %%rdi \n\t"
2528 "mov %c[rbp](%0), %%rbp \n\t"
2529 "mov %c[r8](%0), %%r8 \n\t"
2530 "mov %c[r9](%0), %%r9 \n\t"
2531 "mov %c[r10](%0), %%r10 \n\t"
2532 "mov %c[r11](%0), %%r11 \n\t"
2533 "mov %c[r12](%0), %%r12 \n\t"
2534 "mov %c[r13](%0), %%r13 \n\t"
2535 "mov %c[r14](%0), %%r14 \n\t"
2536 "mov %c[r15](%0), %%r15 \n\t"
2537 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2538 #else
2539 "mov %c[cr2](%0), %%eax \n\t"
2540 "mov %%eax, %%cr2 \n\t"
2541 "mov %c[rax](%0), %%eax \n\t"
2542 "mov %c[rbx](%0), %%ebx \n\t"
2543 "mov %c[rdx](%0), %%edx \n\t"
2544 "mov %c[rsi](%0), %%esi \n\t"
2545 "mov %c[rdi](%0), %%edi \n\t"
2546 "mov %c[rbp](%0), %%ebp \n\t"
2547 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2548 #endif
2549 /* Enter guest mode */
2550 "jne .Llaunched \n\t"
2551 ASM_VMX_VMLAUNCH "\n\t"
2552 "jmp .Lkvm_vmx_return \n\t"
2553 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2554 ".Lkvm_vmx_return: "
2555 /* Save guest registers, load host registers, keep flags */
2556 #ifdef CONFIG_X86_64
2557 "xchg %0, (%%rsp) \n\t"
2558 "mov %%rax, %c[rax](%0) \n\t"
2559 "mov %%rbx, %c[rbx](%0) \n\t"
2560 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2561 "mov %%rdx, %c[rdx](%0) \n\t"
2562 "mov %%rsi, %c[rsi](%0) \n\t"
2563 "mov %%rdi, %c[rdi](%0) \n\t"
2564 "mov %%rbp, %c[rbp](%0) \n\t"
2565 "mov %%r8, %c[r8](%0) \n\t"
2566 "mov %%r9, %c[r9](%0) \n\t"
2567 "mov %%r10, %c[r10](%0) \n\t"
2568 "mov %%r11, %c[r11](%0) \n\t"
2569 "mov %%r12, %c[r12](%0) \n\t"
2570 "mov %%r13, %c[r13](%0) \n\t"
2571 "mov %%r14, %c[r14](%0) \n\t"
2572 "mov %%r15, %c[r15](%0) \n\t"
2573 "mov %%cr2, %%rax \n\t"
2574 "mov %%rax, %c[cr2](%0) \n\t"
2575
2576 "pop %%rbp; pop %%rbp; pop %%rdx \n\t"
2577 #else
2578 "xchg %0, (%%esp) \n\t"
2579 "mov %%eax, %c[rax](%0) \n\t"
2580 "mov %%ebx, %c[rbx](%0) \n\t"
2581 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2582 "mov %%edx, %c[rdx](%0) \n\t"
2583 "mov %%esi, %c[rsi](%0) \n\t"
2584 "mov %%edi, %c[rdi](%0) \n\t"
2585 "mov %%ebp, %c[rbp](%0) \n\t"
2586 "mov %%cr2, %%eax \n\t"
2587 "mov %%eax, %c[cr2](%0) \n\t"
2588
2589 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2590 #endif
2591 "setbe %c[fail](%0) \n\t"
2592 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2593 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2594 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2595 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
2596 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
2597 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
2598 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
2599 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
2600 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
2601 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
2602 #ifdef CONFIG_X86_64
2603 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
2604 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
2605 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
2606 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
2607 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
2608 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
2609 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
2610 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
2611 #endif
2612 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
2613 : "cc", "memory"
2614 #ifdef CONFIG_X86_64
2615 , "rbx", "rdi", "rsi"
2616 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2617 #else
2618 , "ebx", "edi", "rsi"
2619 #endif
2620 );
2621
2622 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2623 if (vmx->rmode.irq.pending)
2624 fixup_rmode_irq(vmx);
2625
2626 vcpu->arch.interrupt_window_open =
2627 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2628
2629 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2630 vmx->launched = 1;
2631
2632 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2633
2634 /* We need to handle NMIs before interrupts are enabled */
2635 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
2636 KVMTRACE_0D(NMI, vcpu, handler);
2637 asm("int $2");
2638 }
2639 }
2640
2641 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2642 {
2643 struct vcpu_vmx *vmx = to_vmx(vcpu);
2644
2645 if (vmx->vmcs) {
2646 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2647 free_vmcs(vmx->vmcs);
2648 vmx->vmcs = NULL;
2649 }
2650 }
2651
2652 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2653 {
2654 struct vcpu_vmx *vmx = to_vmx(vcpu);
2655
2656 spin_lock(&vmx_vpid_lock);
2657 if (vmx->vpid != 0)
2658 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2659 spin_unlock(&vmx_vpid_lock);
2660 vmx_free_vmcs(vcpu);
2661 kfree(vmx->host_msrs);
2662 kfree(vmx->guest_msrs);
2663 kvm_vcpu_uninit(vcpu);
2664 kmem_cache_free(kvm_vcpu_cache, vmx);
2665 }
2666
2667 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2668 {
2669 int err;
2670 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2671 int cpu;
2672
2673 if (!vmx)
2674 return ERR_PTR(-ENOMEM);
2675
2676 allocate_vpid(vmx);
2677
2678 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2679 if (err)
2680 goto free_vcpu;
2681
2682 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2683 if (!vmx->guest_msrs) {
2684 err = -ENOMEM;
2685 goto uninit_vcpu;
2686 }
2687
2688 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2689 if (!vmx->host_msrs)
2690 goto free_guest_msrs;
2691
2692 vmx->vmcs = alloc_vmcs();
2693 if (!vmx->vmcs)
2694 goto free_msrs;
2695
2696 vmcs_clear(vmx->vmcs);
2697
2698 cpu = get_cpu();
2699 vmx_vcpu_load(&vmx->vcpu, cpu);
2700 err = vmx_vcpu_setup(vmx);
2701 vmx_vcpu_put(&vmx->vcpu);
2702 put_cpu();
2703 if (err)
2704 goto free_vmcs;
2705 if (vm_need_virtualize_apic_accesses(kvm))
2706 if (alloc_apic_access_page(kvm) != 0)
2707 goto free_vmcs;
2708
2709 return &vmx->vcpu;
2710
2711 free_vmcs:
2712 free_vmcs(vmx->vmcs);
2713 free_msrs:
2714 kfree(vmx->host_msrs);
2715 free_guest_msrs:
2716 kfree(vmx->guest_msrs);
2717 uninit_vcpu:
2718 kvm_vcpu_uninit(&vmx->vcpu);
2719 free_vcpu:
2720 kmem_cache_free(kvm_vcpu_cache, vmx);
2721 return ERR_PTR(err);
2722 }
2723
2724 static void __init vmx_check_processor_compat(void *rtn)
2725 {
2726 struct vmcs_config vmcs_conf;
2727
2728 *(int *)rtn = 0;
2729 if (setup_vmcs_config(&vmcs_conf) < 0)
2730 *(int *)rtn = -EIO;
2731 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2732 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2733 smp_processor_id());
2734 *(int *)rtn = -EIO;
2735 }
2736 }
2737
2738 static struct kvm_x86_ops vmx_x86_ops = {
2739 .cpu_has_kvm_support = cpu_has_kvm_support,
2740 .disabled_by_bios = vmx_disabled_by_bios,
2741 .hardware_setup = hardware_setup,
2742 .hardware_unsetup = hardware_unsetup,
2743 .check_processor_compatibility = vmx_check_processor_compat,
2744 .hardware_enable = hardware_enable,
2745 .hardware_disable = hardware_disable,
2746 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
2747
2748 .vcpu_create = vmx_create_vcpu,
2749 .vcpu_free = vmx_free_vcpu,
2750 .vcpu_reset = vmx_vcpu_reset,
2751
2752 .prepare_guest_switch = vmx_save_host_state,
2753 .vcpu_load = vmx_vcpu_load,
2754 .vcpu_put = vmx_vcpu_put,
2755 .vcpu_decache = vmx_vcpu_decache,
2756
2757 .set_guest_debug = set_guest_debug,
2758 .guest_debug_pre = kvm_guest_debug_pre,
2759 .get_msr = vmx_get_msr,
2760 .set_msr = vmx_set_msr,
2761 .get_segment_base = vmx_get_segment_base,
2762 .get_segment = vmx_get_segment,
2763 .set_segment = vmx_set_segment,
2764 .get_cpl = vmx_get_cpl,
2765 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2766 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2767 .set_cr0 = vmx_set_cr0,
2768 .set_cr3 = vmx_set_cr3,
2769 .set_cr4 = vmx_set_cr4,
2770 .set_efer = vmx_set_efer,
2771 .get_idt = vmx_get_idt,
2772 .set_idt = vmx_set_idt,
2773 .get_gdt = vmx_get_gdt,
2774 .set_gdt = vmx_set_gdt,
2775 .cache_regs = vcpu_load_rsp_rip,
2776 .decache_regs = vcpu_put_rsp_rip,
2777 .get_rflags = vmx_get_rflags,
2778 .set_rflags = vmx_set_rflags,
2779
2780 .tlb_flush = vmx_flush_tlb,
2781
2782 .run = vmx_vcpu_run,
2783 .handle_exit = kvm_handle_exit,
2784 .skip_emulated_instruction = skip_emulated_instruction,
2785 .patch_hypercall = vmx_patch_hypercall,
2786 .get_irq = vmx_get_irq,
2787 .set_irq = vmx_inject_irq,
2788 .queue_exception = vmx_queue_exception,
2789 .exception_injected = vmx_exception_injected,
2790 .inject_pending_irq = vmx_intr_assist,
2791 .inject_pending_vectors = do_interrupt_requests,
2792
2793 .set_tss_addr = vmx_set_tss_addr,
2794 };
2795
2796 static int __init vmx_init(void)
2797 {
2798 void *va;
2799 int r;
2800
2801 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2802 if (!vmx_io_bitmap_a)
2803 return -ENOMEM;
2804
2805 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2806 if (!vmx_io_bitmap_b) {
2807 r = -ENOMEM;
2808 goto out;
2809 }
2810
2811 vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2812 if (!vmx_msr_bitmap) {
2813 r = -ENOMEM;
2814 goto out1;
2815 }
2816
2817 /*
2818 * Allow direct access to the PC debug port (it is often used for I/O
2819 * delays, but the vmexits simply slow things down).
2820 */
2821 va = kmap(vmx_io_bitmap_a);
2822 memset(va, 0xff, PAGE_SIZE);
2823 clear_bit(0x80, va);
2824 kunmap(vmx_io_bitmap_a);
2825
2826 va = kmap(vmx_io_bitmap_b);
2827 memset(va, 0xff, PAGE_SIZE);
2828 kunmap(vmx_io_bitmap_b);
2829
2830 va = kmap(vmx_msr_bitmap);
2831 memset(va, 0xff, PAGE_SIZE);
2832 kunmap(vmx_msr_bitmap);
2833
2834 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
2835
2836 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2837 if (r)
2838 goto out2;
2839
2840 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE);
2841 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE);
2842 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS);
2843 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP);
2844 vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP);
2845
2846 if (bypass_guest_pf)
2847 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2848
2849 return 0;
2850
2851 out2:
2852 __free_page(vmx_msr_bitmap);
2853 out1:
2854 __free_page(vmx_io_bitmap_b);
2855 out:
2856 __free_page(vmx_io_bitmap_a);
2857 return r;
2858 }
2859
2860 static void __exit vmx_exit(void)
2861 {
2862 __free_page(vmx_msr_bitmap);
2863 __free_page(vmx_io_bitmap_b);
2864 __free_page(vmx_io_bitmap_a);
2865
2866 kvm_exit();
2867 }
2868
2869 module_init(vmx_init)
2870 module_exit(vmx_exit)
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