[SCSI] aic94xx: fix section mismatch
[linux-2.6/openmoko-kernel/knife-kernel.git] / arch / x86 / kvm / vmx.h
blob5dff4606b988591d4e0e82f6247945a829f7f977
1 #ifndef VMX_H
2 #define VMX_H
4 /*
5 * vmx.h: VMX Architecture related definitions
6 * Copyright (c) 2004, Intel Corporation.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19 * Place - Suite 330, Boston, MA 02111-1307 USA.
21 * A few random additions are:
22 * Copyright (C) 2006 Qumranet
23 * Avi Kivity <avi@qumranet.com>
24 * Yaniv Kamay <yaniv@qumranet.com>
29 * Definitions of Primary Processor-Based VM-Execution Controls.
31 #define CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
32 #define CPU_BASED_USE_TSC_OFFSETING 0x00000008
33 #define CPU_BASED_HLT_EXITING 0x00000080
34 #define CPU_BASED_INVLPG_EXITING 0x00000200
35 #define CPU_BASED_MWAIT_EXITING 0x00000400
36 #define CPU_BASED_RDPMC_EXITING 0x00000800
37 #define CPU_BASED_RDTSC_EXITING 0x00001000
38 #define CPU_BASED_CR8_LOAD_EXITING 0x00080000
39 #define CPU_BASED_CR8_STORE_EXITING 0x00100000
40 #define CPU_BASED_TPR_SHADOW 0x00200000
41 #define CPU_BASED_MOV_DR_EXITING 0x00800000
42 #define CPU_BASED_UNCOND_IO_EXITING 0x01000000
43 #define CPU_BASED_USE_IO_BITMAPS 0x02000000
44 #define CPU_BASED_USE_MSR_BITMAPS 0x10000000
45 #define CPU_BASED_MONITOR_EXITING 0x20000000
46 #define CPU_BASED_PAUSE_EXITING 0x40000000
47 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
49 * Definitions of Secondary Processor-Based VM-Execution Controls.
51 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
52 #define SECONDARY_EXEC_ENABLE_VPID 0x00000020
53 #define SECONDARY_EXEC_WBINVD_EXITING 0x00000040
56 #define PIN_BASED_EXT_INTR_MASK 0x00000001
57 #define PIN_BASED_NMI_EXITING 0x00000008
58 #define PIN_BASED_VIRTUAL_NMIS 0x00000020
60 #define VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
61 #define VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
63 #define VM_ENTRY_IA32E_MODE 0x00000200
64 #define VM_ENTRY_SMM 0x00000400
65 #define VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
67 /* VMCS Encodings */
68 enum vmcs_field {
69 VIRTUAL_PROCESSOR_ID = 0x00000000,
70 GUEST_ES_SELECTOR = 0x00000800,
71 GUEST_CS_SELECTOR = 0x00000802,
72 GUEST_SS_SELECTOR = 0x00000804,
73 GUEST_DS_SELECTOR = 0x00000806,
74 GUEST_FS_SELECTOR = 0x00000808,
75 GUEST_GS_SELECTOR = 0x0000080a,
76 GUEST_LDTR_SELECTOR = 0x0000080c,
77 GUEST_TR_SELECTOR = 0x0000080e,
78 HOST_ES_SELECTOR = 0x00000c00,
79 HOST_CS_SELECTOR = 0x00000c02,
80 HOST_SS_SELECTOR = 0x00000c04,
81 HOST_DS_SELECTOR = 0x00000c06,
82 HOST_FS_SELECTOR = 0x00000c08,
83 HOST_GS_SELECTOR = 0x00000c0a,
84 HOST_TR_SELECTOR = 0x00000c0c,
85 IO_BITMAP_A = 0x00002000,
86 IO_BITMAP_A_HIGH = 0x00002001,
87 IO_BITMAP_B = 0x00002002,
88 IO_BITMAP_B_HIGH = 0x00002003,
89 MSR_BITMAP = 0x00002004,
90 MSR_BITMAP_HIGH = 0x00002005,
91 VM_EXIT_MSR_STORE_ADDR = 0x00002006,
92 VM_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
93 VM_EXIT_MSR_LOAD_ADDR = 0x00002008,
94 VM_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
95 VM_ENTRY_MSR_LOAD_ADDR = 0x0000200a,
96 VM_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200b,
97 TSC_OFFSET = 0x00002010,
98 TSC_OFFSET_HIGH = 0x00002011,
99 VIRTUAL_APIC_PAGE_ADDR = 0x00002012,
100 VIRTUAL_APIC_PAGE_ADDR_HIGH = 0x00002013,
101 APIC_ACCESS_ADDR = 0x00002014,
102 APIC_ACCESS_ADDR_HIGH = 0x00002015,
103 VMCS_LINK_POINTER = 0x00002800,
104 VMCS_LINK_POINTER_HIGH = 0x00002801,
105 GUEST_IA32_DEBUGCTL = 0x00002802,
106 GUEST_IA32_DEBUGCTL_HIGH = 0x00002803,
107 PIN_BASED_VM_EXEC_CONTROL = 0x00004000,
108 CPU_BASED_VM_EXEC_CONTROL = 0x00004002,
109 EXCEPTION_BITMAP = 0x00004004,
110 PAGE_FAULT_ERROR_CODE_MASK = 0x00004006,
111 PAGE_FAULT_ERROR_CODE_MATCH = 0x00004008,
112 CR3_TARGET_COUNT = 0x0000400a,
113 VM_EXIT_CONTROLS = 0x0000400c,
114 VM_EXIT_MSR_STORE_COUNT = 0x0000400e,
115 VM_EXIT_MSR_LOAD_COUNT = 0x00004010,
116 VM_ENTRY_CONTROLS = 0x00004012,
117 VM_ENTRY_MSR_LOAD_COUNT = 0x00004014,
118 VM_ENTRY_INTR_INFO_FIELD = 0x00004016,
119 VM_ENTRY_EXCEPTION_ERROR_CODE = 0x00004018,
120 VM_ENTRY_INSTRUCTION_LEN = 0x0000401a,
121 TPR_THRESHOLD = 0x0000401c,
122 SECONDARY_VM_EXEC_CONTROL = 0x0000401e,
123 VM_INSTRUCTION_ERROR = 0x00004400,
124 VM_EXIT_REASON = 0x00004402,
125 VM_EXIT_INTR_INFO = 0x00004404,
126 VM_EXIT_INTR_ERROR_CODE = 0x00004406,
127 IDT_VECTORING_INFO_FIELD = 0x00004408,
128 IDT_VECTORING_ERROR_CODE = 0x0000440a,
129 VM_EXIT_INSTRUCTION_LEN = 0x0000440c,
130 VMX_INSTRUCTION_INFO = 0x0000440e,
131 GUEST_ES_LIMIT = 0x00004800,
132 GUEST_CS_LIMIT = 0x00004802,
133 GUEST_SS_LIMIT = 0x00004804,
134 GUEST_DS_LIMIT = 0x00004806,
135 GUEST_FS_LIMIT = 0x00004808,
136 GUEST_GS_LIMIT = 0x0000480a,
137 GUEST_LDTR_LIMIT = 0x0000480c,
138 GUEST_TR_LIMIT = 0x0000480e,
139 GUEST_GDTR_LIMIT = 0x00004810,
140 GUEST_IDTR_LIMIT = 0x00004812,
141 GUEST_ES_AR_BYTES = 0x00004814,
142 GUEST_CS_AR_BYTES = 0x00004816,
143 GUEST_SS_AR_BYTES = 0x00004818,
144 GUEST_DS_AR_BYTES = 0x0000481a,
145 GUEST_FS_AR_BYTES = 0x0000481c,
146 GUEST_GS_AR_BYTES = 0x0000481e,
147 GUEST_LDTR_AR_BYTES = 0x00004820,
148 GUEST_TR_AR_BYTES = 0x00004822,
149 GUEST_INTERRUPTIBILITY_INFO = 0x00004824,
150 GUEST_ACTIVITY_STATE = 0X00004826,
151 GUEST_SYSENTER_CS = 0x0000482A,
152 HOST_IA32_SYSENTER_CS = 0x00004c00,
153 CR0_GUEST_HOST_MASK = 0x00006000,
154 CR4_GUEST_HOST_MASK = 0x00006002,
155 CR0_READ_SHADOW = 0x00006004,
156 CR4_READ_SHADOW = 0x00006006,
157 CR3_TARGET_VALUE0 = 0x00006008,
158 CR3_TARGET_VALUE1 = 0x0000600a,
159 CR3_TARGET_VALUE2 = 0x0000600c,
160 CR3_TARGET_VALUE3 = 0x0000600e,
161 EXIT_QUALIFICATION = 0x00006400,
162 GUEST_LINEAR_ADDRESS = 0x0000640a,
163 GUEST_CR0 = 0x00006800,
164 GUEST_CR3 = 0x00006802,
165 GUEST_CR4 = 0x00006804,
166 GUEST_ES_BASE = 0x00006806,
167 GUEST_CS_BASE = 0x00006808,
168 GUEST_SS_BASE = 0x0000680a,
169 GUEST_DS_BASE = 0x0000680c,
170 GUEST_FS_BASE = 0x0000680e,
171 GUEST_GS_BASE = 0x00006810,
172 GUEST_LDTR_BASE = 0x00006812,
173 GUEST_TR_BASE = 0x00006814,
174 GUEST_GDTR_BASE = 0x00006816,
175 GUEST_IDTR_BASE = 0x00006818,
176 GUEST_DR7 = 0x0000681a,
177 GUEST_RSP = 0x0000681c,
178 GUEST_RIP = 0x0000681e,
179 GUEST_RFLAGS = 0x00006820,
180 GUEST_PENDING_DBG_EXCEPTIONS = 0x00006822,
181 GUEST_SYSENTER_ESP = 0x00006824,
182 GUEST_SYSENTER_EIP = 0x00006826,
183 HOST_CR0 = 0x00006c00,
184 HOST_CR3 = 0x00006c02,
185 HOST_CR4 = 0x00006c04,
186 HOST_FS_BASE = 0x00006c06,
187 HOST_GS_BASE = 0x00006c08,
188 HOST_TR_BASE = 0x00006c0a,
189 HOST_GDTR_BASE = 0x00006c0c,
190 HOST_IDTR_BASE = 0x00006c0e,
191 HOST_IA32_SYSENTER_ESP = 0x00006c10,
192 HOST_IA32_SYSENTER_EIP = 0x00006c12,
193 HOST_RSP = 0x00006c14,
194 HOST_RIP = 0x00006c16,
197 #define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
199 #define EXIT_REASON_EXCEPTION_NMI 0
200 #define EXIT_REASON_EXTERNAL_INTERRUPT 1
201 #define EXIT_REASON_TRIPLE_FAULT 2
203 #define EXIT_REASON_PENDING_INTERRUPT 7
205 #define EXIT_REASON_TASK_SWITCH 9
206 #define EXIT_REASON_CPUID 10
207 #define EXIT_REASON_HLT 12
208 #define EXIT_REASON_INVLPG 14
209 #define EXIT_REASON_RDPMC 15
210 #define EXIT_REASON_RDTSC 16
211 #define EXIT_REASON_VMCALL 18
212 #define EXIT_REASON_VMCLEAR 19
213 #define EXIT_REASON_VMLAUNCH 20
214 #define EXIT_REASON_VMPTRLD 21
215 #define EXIT_REASON_VMPTRST 22
216 #define EXIT_REASON_VMREAD 23
217 #define EXIT_REASON_VMRESUME 24
218 #define EXIT_REASON_VMWRITE 25
219 #define EXIT_REASON_VMOFF 26
220 #define EXIT_REASON_VMON 27
221 #define EXIT_REASON_CR_ACCESS 28
222 #define EXIT_REASON_DR_ACCESS 29
223 #define EXIT_REASON_IO_INSTRUCTION 30
224 #define EXIT_REASON_MSR_READ 31
225 #define EXIT_REASON_MSR_WRITE 32
226 #define EXIT_REASON_MWAIT_INSTRUCTION 36
227 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
228 #define EXIT_REASON_APIC_ACCESS 44
229 #define EXIT_REASON_WBINVD 54
232 * Interruption-information format
234 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
235 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
236 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
237 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
239 #define VECTORING_INFO_VECTOR_MASK INTR_INFO_VECTOR_MASK
240 #define VECTORING_INFO_TYPE_MASK INTR_INFO_INTR_TYPE_MASK
241 #define VECTORING_INFO_DELIVER_CODE_MASK INTR_INFO_DELIVER_CODE_MASK
242 #define VECTORING_INFO_VALID_MASK INTR_INFO_VALID_MASK
244 #define INTR_TYPE_EXT_INTR (0 << 8) /* external interrupt */
245 #define INTR_TYPE_EXCEPTION (3 << 8) /* processor exception */
246 #define INTR_TYPE_SOFT_INTR (4 << 8) /* software interrupt */
249 * Exit Qualifications for MOV for Control Register Access
251 #define CONTROL_REG_ACCESS_NUM 0x7 /* 2:0, number of control reg.*/
252 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
253 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose reg. */
254 #define LMSW_SOURCE_DATA_SHIFT 16
255 #define LMSW_SOURCE_DATA (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
256 #define REG_EAX (0 << 8)
257 #define REG_ECX (1 << 8)
258 #define REG_EDX (2 << 8)
259 #define REG_EBX (3 << 8)
260 #define REG_ESP (4 << 8)
261 #define REG_EBP (5 << 8)
262 #define REG_ESI (6 << 8)
263 #define REG_EDI (7 << 8)
264 #define REG_R8 (8 << 8)
265 #define REG_R9 (9 << 8)
266 #define REG_R10 (10 << 8)
267 #define REG_R11 (11 << 8)
268 #define REG_R12 (12 << 8)
269 #define REG_R13 (13 << 8)
270 #define REG_R14 (14 << 8)
271 #define REG_R15 (15 << 8)
274 * Exit Qualifications for MOV for Debug Register Access
276 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug reg. */
277 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
278 #define TYPE_MOV_TO_DR (0 << 4)
279 #define TYPE_MOV_FROM_DR (1 << 4)
280 #define DEBUG_REG_ACCESS_REG 0xf00 /* 11:8, general purpose reg. */
283 /* segment AR */
284 #define SEGMENT_AR_L_MASK (1 << 13)
286 #define AR_TYPE_ACCESSES_MASK 1
287 #define AR_TYPE_READABLE_MASK (1 << 1)
288 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
289 #define AR_TYPE_CODE_MASK (1 << 3)
290 #define AR_TYPE_MASK 0x0f
291 #define AR_TYPE_BUSY_64_TSS 11
292 #define AR_TYPE_BUSY_32_TSS 11
293 #define AR_TYPE_BUSY_16_TSS 3
294 #define AR_TYPE_LDT 2
296 #define AR_UNUSABLE_MASK (1 << 16)
297 #define AR_S_MASK (1 << 4)
298 #define AR_P_MASK (1 << 7)
299 #define AR_L_MASK (1 << 13)
300 #define AR_DB_MASK (1 << 14)
301 #define AR_G_MASK (1 << 15)
302 #define AR_DPL_SHIFT 5
303 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
305 #define AR_RESERVD_MASK 0xfffe0f00
307 #define MSR_IA32_VMX_BASIC 0x480
308 #define MSR_IA32_VMX_PINBASED_CTLS 0x481
309 #define MSR_IA32_VMX_PROCBASED_CTLS 0x482
310 #define MSR_IA32_VMX_EXIT_CTLS 0x483
311 #define MSR_IA32_VMX_ENTRY_CTLS 0x484
312 #define MSR_IA32_VMX_MISC 0x485
313 #define MSR_IA32_VMX_CR0_FIXED0 0x486
314 #define MSR_IA32_VMX_CR0_FIXED1 0x487
315 #define MSR_IA32_VMX_CR4_FIXED0 0x488
316 #define MSR_IA32_VMX_CR4_FIXED1 0x489
317 #define MSR_IA32_VMX_VMCS_ENUM 0x48a
318 #define MSR_IA32_VMX_PROCBASED_CTLS2 0x48b
320 #define MSR_IA32_FEATURE_CONTROL 0x3a
321 #define MSR_IA32_FEATURE_CONTROL_LOCKED 0x1
322 #define MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED 0x4
324 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT 9
326 #define VMX_NR_VPIDS (1 << 16)
327 #define VMX_VPID_EXTENT_SINGLE_CONTEXT 1
328 #define VMX_VPID_EXTENT_ALL_CONTEXT 2
330 #endif