drivers/i2c/busses/i2c-piix4.c

   1 /*
   2     piix4.c - Part of lm_sensors, Linux kernel modules for hardware
   3               monitoring
   4     Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
   5     Philip Edelbrock <phil@netroedge.com>
   6
   7     This program is free software; you can redistribute it and/or modify
   8     it under the terms of the GNU General Public License as published by
   9     the Free Software Foundation; either version 2 of the License, or
  10     (at your option) any later version.
  11
  12     This program is distributed in the hope that it will be useful,
  13     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20 */
  21
  22 /*
  23    Supports:
  24         Intel PIIX4, 440MX
  25         Serverworks OSB4, CSB5, CSB6, HT-1000
  26         ATI IXP200, IXP300, IXP400, SB600, SB700, SB800
  27         SMSC Victory66
  28
  29    Note: we assume there can only be one device, with one SMBus interface.
  30 */
  31
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/pci.h>
  35 #include <linux/kernel.h>
  36 #include <linux/delay.h>
  37 #include <linux/stddef.h>
  38 #include <linux/ioport.h>
  39 #include <linux/i2c.h>
  40 #include <linux/init.h>
  41 #include <linux/dmi.h>
  42 #include <asm/io.h>
  43
  44
  45 struct sd {
  46         const unsigned short mfr;
  47         const unsigned short dev;
  48         const unsigned char fn;
  49         const char *name;
  50 };
  51
  52 /* PIIX4 SMBus address offsets */
  53 #define SMBHSTSTS       (0 + piix4_smba)
  54 #define SMBHSLVSTS      (1 + piix4_smba)
  55 #define SMBHSTCNT       (2 + piix4_smba)
  56 #define SMBHSTCMD       (3 + piix4_smba)
  57 #define SMBHSTADD       (4 + piix4_smba)
  58 #define SMBHSTDAT0      (5 + piix4_smba)
  59 #define SMBHSTDAT1      (6 + piix4_smba)
  60 #define SMBBLKDAT       (7 + piix4_smba)
  61 #define SMBSLVCNT       (8 + piix4_smba)
  62 #define SMBSHDWCMD      (9 + piix4_smba)
  63 #define SMBSLVEVT       (0xA + piix4_smba)
  64 #define SMBSLVDAT       (0xC + piix4_smba)
  65
  66 /* count for request_region */
  67 #define SMBIOSIZE       8
  68
  69 /* PCI Address Constants */
  70 #define SMBBA           0x090
  71 #define SMBHSTCFG       0x0D2
  72 #define SMBSLVC         0x0D3
  73 #define SMBSHDW1        0x0D4
  74 #define SMBSHDW2        0x0D5
  75 #define SMBREV          0x0D6
  76
  77 /* Other settings */
  78 #define MAX_TIMEOUT     500
  79 #define  ENABLE_INT9    0
  80
  81 /* PIIX4 constants */
  82 #define PIIX4_QUICK             0x00
  83 #define PIIX4_BYTE              0x04
  84 #define PIIX4_BYTE_DATA         0x08
  85 #define PIIX4_WORD_DATA         0x0C
  86 #define PIIX4_BLOCK_DATA        0x14
  87
  88 /* insmod parameters */
  89
  90 /* If force is set to anything different from 0, we forcibly enable the
  91    PIIX4. DANGEROUS! */
  92 static int force;
  93 module_param (force, int, 0);
  94 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
  95
  96 /* If force_addr is set to anything different from 0, we forcibly enable
  97    the PIIX4 at the given address. VERY DANGEROUS! */
  98 static int force_addr;
  99 module_param (force_addr, int, 0);
 100 MODULE_PARM_DESC(force_addr,
 101                  "Forcibly enable the PIIX4 at the given address. "
 102                  "EXTREMELY DANGEROUS!");
 103
 104 static int piix4_transaction(void);
 105
 106 static unsigned short piix4_smba;
 107 static int srvrworks_csb5_delay;
 108 static struct pci_driver piix4_driver;
 109 static struct i2c_adapter piix4_adapter;
 110
 111 static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
 112         {
 113                 .ident = "Sapphire AM2RD790",
 114                 .matches = {
 115                         DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
 116                         DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
 117                 },
 118         },
 119         {
 120                 .ident = "DFI Lanparty UT 790FX",
 121                 .matches = {
 122                         DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
 123                         DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
 124                 },
 125         },
 126         { }
 127 };
 128
 129 /* The IBM entry is in a separate table because we only check it
 130    on Intel-based systems */
 131 static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
 132         {
 133                 .ident = "IBM",
 134                 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
 135         },
 136         { },
 137 };
 138
 139 static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
 140                                 const struct pci_device_id *id)
 141 {
 142         unsigned char temp;
 143
 144         dev_info(&PIIX4_dev->dev, "Found %s device\n", pci_name(PIIX4_dev));
 145
 146         if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
 147             (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
 148                 srvrworks_csb5_delay = 1;
 149
 150         /* On some motherboards, it was reported that accessing the SMBus
 151            caused severe hardware problems */
 152         if (dmi_check_system(piix4_dmi_blacklist)) {
 153                 dev_err(&PIIX4_dev->dev,
 154                         "Accessing the SMBus on this system is unsafe!\n");
 155                 return -EPERM;
 156         }
 157
 158         /* Don't access SMBus on IBM systems which get corrupted eeproms */
 159         if (dmi_check_system(piix4_dmi_ibm) &&
 160                         PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
 161                 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
 162                         "may corrupt your serial eeprom! Refusing to load "
 163                         "module!\n");
 164                 return -EPERM;
 165         }
 166
 167         /* Determine the address of the SMBus areas */
 168         if (force_addr) {
 169                 piix4_smba = force_addr & 0xfff0;
 170                 force = 0;
 171         } else {
 172                 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
 173                 piix4_smba &= 0xfff0;
 174                 if(piix4_smba == 0) {
 175                         dev_err(&PIIX4_dev->dev, "SMB base address "
 176                                 "uninitialized - upgrade BIOS or use "
 177                                 "force_addr=0xaddr\n");
 178                         return -ENODEV;
 179                 }
 180         }
 181
 182         if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
 183                 dev_err(&PIIX4_dev->dev, "SMB region 0x%x already in use!\n",
 184                         piix4_smba);
 185                 return -ENODEV;
 186         }
 187
 188         pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
 189
 190         /* If force_addr is set, we program the new address here. Just to make
 191            sure, we disable the PIIX4 first. */
 192         if (force_addr) {
 193                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
 194                 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
 195                 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
 196                 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
 197                         "new address %04x!\n", piix4_smba);
 198         } else if ((temp & 1) == 0) {
 199                 if (force) {
 200                         /* This should never need to be done, but has been
 201                          * noted that many Dell machines have the SMBus
 202                          * interface on the PIIX4 disabled!? NOTE: This assumes
 203                          * I/O space and other allocations WERE done by the
 204                          * Bios!  Don't complain if your hardware does weird
 205                          * things after enabling this. :') Check for Bios
 206                          * updates before resorting to this.
 207                          */
 208                         pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
 209                                               temp | 1);
 210                         dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
 211                                 "WARNING: SMBus interface has been "
 212                                 "FORCEFULLY ENABLED!\n");
 213                 } else {
 214                         dev_err(&PIIX4_dev->dev,
 215                                 "Host SMBus controller not enabled!\n");
 216                         release_region(piix4_smba, SMBIOSIZE);
 217                         piix4_smba = 0;
 218                         return -ENODEV;
 219                 }
 220         }
 221
 222         if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
 223                 dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
 224         else if ((temp & 0x0E) == 0)
 225                 dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
 226         else
 227                 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
 228                         "(or code out of date)!\n");
 229
 230         pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
 231         dev_dbg(&PIIX4_dev->dev, "SMBREV = 0x%X\n", temp);
 232         dev_dbg(&PIIX4_dev->dev, "SMBA = 0x%X\n", piix4_smba);
 233
 234         return 0;
 235 }
 236
 237 /* Another internally used function */
 238 static int piix4_transaction(void)
 239 {
 240         int temp;
 241         int result = 0;
 242         int timeout = 0;
 243
 244         dev_dbg(&piix4_adapter.dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
 245                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 246                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 247                 inb_p(SMBHSTDAT1));
 248
 249         /* Make sure the SMBus host is ready to start transmitting */
 250         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 251                 dev_dbg(&piix4_adapter.dev, "SMBus busy (%02x). "
 252                         "Resetting...\n", temp);
 253                 outb_p(temp, SMBHSTSTS);
 254                 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 255                         dev_err(&piix4_adapter.dev, "Failed! (%02x)\n", temp);
 256                         return -1;
 257                 } else {
 258                         dev_dbg(&piix4_adapter.dev, "Successful!\n");
 259                 }
 260         }
 261
 262         /* start the transaction by setting bit 6 */
 263         outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
 264
 265         /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
 266         if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
 267                 msleep(2);
 268         else
 269                 msleep(1);
 270
 271         while ((timeout++ < MAX_TIMEOUT) &&
 272                ((temp = inb_p(SMBHSTSTS)) & 0x01))
 273                 msleep(1);
 274
 275         /* If the SMBus is still busy, we give up */
 276         if (timeout >= MAX_TIMEOUT) {
 277                 dev_err(&piix4_adapter.dev, "SMBus Timeout!\n");
 278                 result = -1;
 279         }
 280
 281         if (temp & 0x10) {
 282                 result = -1;
 283                 dev_err(&piix4_adapter.dev, "Error: Failed bus transaction\n");
 284         }
 285
 286         if (temp & 0x08) {
 287                 result = -1;
 288                 dev_dbg(&piix4_adapter.dev, "Bus collision! SMBus may be "
 289                         "locked until next hard reset. (sorry!)\n");
 290                 /* Clock stops and slave is stuck in mid-transmission */
 291         }
 292
 293         if (temp & 0x04) {
 294                 result = -1;
 295                 dev_dbg(&piix4_adapter.dev, "Error: no response!\n");
 296         }
 297
 298         if (inb_p(SMBHSTSTS) != 0x00)
 299                 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
 300
 301         if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
 302                 dev_err(&piix4_adapter.dev, "Failed reset at end of "
 303                         "transaction (%02x)\n", temp);
 304         }
 305         dev_dbg(&piix4_adapter.dev, "Transaction (post): CNT=%02x, CMD=%02x, "
 306                 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
 307                 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
 308                 inb_p(SMBHSTDAT1));
 309         return result;
 310 }
 311
 312 /* Return -1 on error. */
 313 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
 314                  unsigned short flags, char read_write,
 315                  u8 command, int size, union i2c_smbus_data * data)
 316 {
 317         int i, len;
 318
 319         switch (size) {
 320         case I2C_SMBUS_PROC_CALL:
 321                 dev_err(&adap->dev, "I2C_SMBUS_PROC_CALL not supported!\n");
 322                 return -1;
 323         case I2C_SMBUS_QUICK:
 324                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 325                        SMBHSTADD);
 326                 size = PIIX4_QUICK;
 327                 break;
 328         case I2C_SMBUS_BYTE:
 329                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 330                        SMBHSTADD);
 331                 if (read_write == I2C_SMBUS_WRITE)
 332                         outb_p(command, SMBHSTCMD);
 333                 size = PIIX4_BYTE;
 334                 break;
 335         case I2C_SMBUS_BYTE_DATA:
 336                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 337                        SMBHSTADD);
 338                 outb_p(command, SMBHSTCMD);
 339                 if (read_write == I2C_SMBUS_WRITE)
 340                         outb_p(data->byte, SMBHSTDAT0);
 341                 size = PIIX4_BYTE_DATA;
 342                 break;
 343         case I2C_SMBUS_WORD_DATA:
 344                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 345                        SMBHSTADD);
 346                 outb_p(command, SMBHSTCMD);
 347                 if (read_write == I2C_SMBUS_WRITE) {
 348                         outb_p(data->word & 0xff, SMBHSTDAT0);
 349                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
 350                 }
 351                 size = PIIX4_WORD_DATA;
 352                 break;
 353         case I2C_SMBUS_BLOCK_DATA:
 354                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 355                        SMBHSTADD);
 356                 outb_p(command, SMBHSTCMD);
 357                 if (read_write == I2C_SMBUS_WRITE) {
 358                         len = data->block[0];
 359                         if (len < 0)
 360                                 len = 0;
 361                         if (len > 32)
 362                                 len = 32;
 363                         outb_p(len, SMBHSTDAT0);
 364                         i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
 365                         for (i = 1; i <= len; i++)
 366                                 outb_p(data->block[i], SMBBLKDAT);
 367                 }
 368                 size = PIIX4_BLOCK_DATA;
 369                 break;
 370         }
 371
 372         outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
 373
 374         if (piix4_transaction())        /* Error in transaction */
 375                 return -1;
 376
 377         if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
 378                 return 0;
 379
 380
 381         switch (size) {
 382         case PIIX4_BYTE:
 383         case PIIX4_BYTE_DATA:
 384                 data->byte = inb_p(SMBHSTDAT0);
 385                 break;
 386         case PIIX4_WORD_DATA:
 387                 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
 388                 break;
 389         case PIIX4_BLOCK_DATA:
 390                 data->block[0] = inb_p(SMBHSTDAT0);
 391                 i = inb_p(SMBHSTCNT);   /* Reset SMBBLKDAT */
 392                 for (i = 1; i <= data->block[0]; i++)
 393                         data->block[i] = inb_p(SMBBLKDAT);
 394                 break;
 395         }
 396         return 0;
 397 }
 398
 399 static u32 piix4_func(struct i2c_adapter *adapter)
 400 {
 401         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 402             I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 403             I2C_FUNC_SMBUS_BLOCK_DATA;
 404 }
 405
 406 static const struct i2c_algorithm smbus_algorithm = {
 407         .smbus_xfer     = piix4_access,
 408         .functionality  = piix4_func,
 409 };
 410
 411 static struct i2c_adapter piix4_adapter = {
 412         .owner          = THIS_MODULE,
 413         .id             = I2C_HW_SMBUS_PIIX4,
 414         .class          = I2C_CLASS_HWMON,
 415         .algo           = &smbus_algorithm,
 416 };
 417
 418 static struct pci_device_id piix4_ids[] = {
 419         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
 420         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
 421         { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
 422         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
 423         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
 424         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
 425         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
 426         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 427                      PCI_DEVICE_ID_SERVERWORKS_OSB4) },
 428         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 429                      PCI_DEVICE_ID_SERVERWORKS_CSB5) },
 430         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 431                      PCI_DEVICE_ID_SERVERWORKS_CSB6) },
 432         { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
 433                      PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
 434         { 0, }
 435 };
 436
 437 MODULE_DEVICE_TABLE (pci, piix4_ids);
 438
 439 static int __devinit piix4_probe(struct pci_dev *dev,
 440                                 const struct pci_device_id *id)
 441 {
 442         int retval;
 443
 444         retval = piix4_setup(dev, id);
 445         if (retval)
 446                 return retval;
 447
 448         /* set up the sysfs linkage to our parent device */
 449         piix4_adapter.dev.parent = &dev->dev;
 450
 451         snprintf(piix4_adapter.name, sizeof(piix4_adapter.name),
 452                 "SMBus PIIX4 adapter at %04x", piix4_smba);
 453
 454         if ((retval = i2c_add_adapter(&piix4_adapter))) {
 455                 dev_err(&dev->dev, "Couldn't register adapter!\n");
 456                 release_region(piix4_smba, SMBIOSIZE);
 457                 piix4_smba = 0;
 458         }
 459
 460         return retval;
 461 }
 462
 463 static void __devexit piix4_remove(struct pci_dev *dev)
 464 {
 465         if (piix4_smba) {
 466                 i2c_del_adapter(&piix4_adapter);
 467                 release_region(piix4_smba, SMBIOSIZE);
 468                 piix4_smba = 0;
 469         }
 470 }
 471
 472 static struct pci_driver piix4_driver = {
 473         .name           = "piix4_smbus",
 474         .id_table       = piix4_ids,
 475         .probe          = piix4_probe,
 476         .remove         = __devexit_p(piix4_remove),
 477 };
 478
 479 static int __init i2c_piix4_init(void)
 480 {
 481         return pci_register_driver(&piix4_driver);
 482 }
 483
 484 static void __exit i2c_piix4_exit(void)
 485 {
 486         pci_unregister_driver(&piix4_driver);
 487 }
 488
 489 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
 490                 "Philip Edelbrock <phil@netroedge.com>");
 491 MODULE_DESCRIPTION("PIIX4 SMBus driver");
 492 MODULE_LICENSE("GPL");
 493
 494 module_init(i2c_piix4_init);
 495 module_exit(i2c_piix4_exit);