sound/pci/ca0106/ca0106.h

   1 /*
   2  *  Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
   3  *  Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit
   4  *  Version: 0.0.22
   5  *
   6  *  FEATURES currently supported:
   7  *    See ca0106_main.c for features.
   8  *
   9  *  Changelog:
  10  *    Support interrupts per period.
  11  *    Removed noise from Center/LFE channel when in Analog mode.
  12  *    Rename and remove mixer controls.
  13  *  0.0.6
  14  *    Use separate card based DMA buffer for periods table list.
  15  *  0.0.7
  16  *    Change remove and rename ctrls into lists.
  17  *  0.0.8
  18  *    Try to fix capture sources.
  19  *  0.0.9
  20  *    Fix AC3 output.
  21  *    Enable S32_LE format support.
  22  *  0.0.10
  23  *    Enable playback 48000 and 96000 rates. (Rates other that these do not work, even with "plug:front".)
  24  *  0.0.11
  25  *    Add Model name recognition.
  26  *  0.0.12
  27  *    Correct interrupt timing. interrupt at end of period, instead of in the middle of a playback period.
  28  *    Remove redundent "voice" handling.
  29  *  0.0.13
  30  *    Single trigger call for multi channels.
  31  *  0.0.14
  32  *    Set limits based on what the sound card hardware can do.
  33  *    playback periods_min=2, periods_max=8
  34  *    capture hw constraints require period_size = n * 64 bytes.
  35  *    playback hw constraints require period_size = n * 64 bytes.
  36  *  0.0.15
  37  *    Separated ca0106.c into separate functional .c files.
  38  *  0.0.16
  39  *    Implement 192000 sample rate.
  40  *  0.0.17
  41  *    Add support for SB0410 and SB0413.
  42  *  0.0.18
  43  *    Modified Copyright message.
  44  *  0.0.19
  45  *    Added I2C and SPI registers. Filled in interrupt enable.
  46  *  0.0.20
  47  *    Added GPIO info for SB Live 24bit.
  48  *  0.0.21
  49  *   Implement support for Line-in capture on SB Live 24bit.
  50  *  0.0.22
  51  *    Add support for mute control on SB Live 24bit (cards w/ SPI DAC)
  52  *
  53  *
  54  *  This code was initally based on code from ALSA's emu10k1x.c which is:
  55  *  Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
  56  *
  57  *   This program is free software; you can redistribute it and/or modify
  58  *   it under the terms of the GNU General Public License as published by
  59  *   the Free Software Foundation; either version 2 of the License, or
  60  *   (at your option) any later version.
  61  *
  62  *   This program is distributed in the hope that it will be useful,
  63  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  64  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  65  *   GNU General Public License for more details.
  66  *
  67  *   You should have received a copy of the GNU General Public License
  68  *   along with this program; if not, write to the Free Software
  69  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  70  *
  71  */
  72
  73 /************************************************************************************************/
  74 /* PCI function 0 registers, address = <val> + PCIBASE0                                         */
  75 /************************************************************************************************/
  76
  77 #define PTR                     0x00            /* Indexed register set pointer register        */
  78                                                 /* NOTE: The CHANNELNUM and ADDRESS words can   */
  79                                                 /* be modified independently of each other.     */
  80                                                 /* CNL[1:0], ADDR[27:16]                        */
  81
  82 #define DATA                    0x04            /* Indexed register set data register           */
  83                                                 /* DATA[31:0]                                   */
  84
  85 #define IPR                     0x08            /* Global interrupt pending register            */
  86                                                 /* Clear pending interrupts by writing a 1 to   */
  87                                                 /* the relevant bits and zero to the other bits */
  88 #define IPR_MIDI_RX_B           0x00020000      /* MIDI UART-B Receive buffer non-empty         */
  89 #define IPR_MIDI_TX_B           0x00010000      /* MIDI UART-B Transmit buffer empty            */
  90 #define IPR_SPDIF_IN_USER       0x00004000      /* SPDIF input user data has 16 more bits       */
  91 #define IPR_SPDIF_OUT_USER      0x00002000      /* SPDIF output user data needs 16 more bits    */
  92 #define IPR_SPDIF_OUT_FRAME     0x00001000      /* SPDIF frame about to start                   */
  93 #define IPR_SPI                 0x00000800      /* SPI transaction completed                    */
  94 #define IPR_I2C_EEPROM          0x00000400      /* I2C EEPROM transaction completed             */
  95 #define IPR_I2C_DAC             0x00000200      /* I2C DAC transaction completed                */
  96 #define IPR_AI                  0x00000100      /* Audio pending register changed. See PTR reg 0x76     */
  97 #define IPR_GPI                 0x00000080      /* General Purpose input changed                */
  98 #define IPR_SRC_LOCKED          0x00000040      /* SRC lock status changed                      */
  99 #define IPR_SPDIF_STATUS        0x00000020      /* SPDIF status changed                         */
 100 #define IPR_TIMER2              0x00000010      /* 192000Hz Timer                               */
 101 #define IPR_TIMER1              0x00000008      /* 44100Hz Timer                                */
 102 #define IPR_MIDI_RX_A           0x00000004      /* MIDI UART-A Receive buffer non-empty         */
 103 #define IPR_MIDI_TX_A           0x00000002      /* MIDI UART-A Transmit buffer empty            */
 104 #define IPR_PCI                 0x00000001      /* PCI Bus error                                */
 105
 106 #define INTE                    0x0c            /* Interrupt enable register                    */
 107
 108 #define INTE_MIDI_RX_B          0x00020000      /* MIDI UART-B Receive buffer non-empty         */
 109 #define INTE_MIDI_TX_B          0x00010000      /* MIDI UART-B Transmit buffer empty            */
 110 #define INTE_SPDIF_IN_USER      0x00004000      /* SPDIF input user data has 16 more bits       */
 111 #define INTE_SPDIF_OUT_USER     0x00002000      /* SPDIF output user data needs 16 more bits    */
 112 #define INTE_SPDIF_OUT_FRAME    0x00001000      /* SPDIF frame about to start                   */
 113 #define INTE_SPI                0x00000800      /* SPI transaction completed                    */
 114 #define INTE_I2C_EEPROM         0x00000400      /* I2C EEPROM transaction completed             */
 115 #define INTE_I2C_DAC            0x00000200      /* I2C DAC transaction completed                */
 116 #define INTE_AI                 0x00000100      /* Audio pending register changed. See PTR reg 0x75 */
 117 #define INTE_GPI                0x00000080      /* General Purpose input changed                */
 118 #define INTE_SRC_LOCKED         0x00000040      /* SRC lock status changed                      */
 119 #define INTE_SPDIF_STATUS       0x00000020      /* SPDIF status changed                         */
 120 #define INTE_TIMER2             0x00000010      /* 192000Hz Timer                               */
 121 #define INTE_TIMER1             0x00000008      /* 44100Hz Timer                                */
 122 #define INTE_MIDI_RX_A          0x00000004      /* MIDI UART-A Receive buffer non-empty         */
 123 #define INTE_MIDI_TX_A          0x00000002      /* MIDI UART-A Transmit buffer empty            */
 124 #define INTE_PCI                0x00000001      /* PCI Bus error                                */
 125
 126 #define UNKNOWN10               0x10            /* Unknown ??. Defaults to 0 */
 127 #define HCFG                    0x14            /* Hardware config register                     */
 128                                                 /* 0x1000 causes AC3 to fails. It adds a dither bit. */
 129
 130 #define HCFG_STAC               0x10000000      /* Special mode for STAC9460 Codec. */
 131 #define HCFG_CAPTURE_I2S_BYPASS 0x08000000      /* 1 = bypass I2S input async SRC. */
 132 #define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000    /* 1 = bypass SPDIF input async SRC. */
 133 #define HCFG_PLAYBACK_I2S_BYPASS 0x02000000     /* 0 = I2S IN mixer output, 1 = I2S IN1. */
 134 #define HCFG_FORCE_LOCK         0x01000000      /* For test only. Force input SRC tracker to lock. */
 135 #define HCFG_PLAYBACK_ATTENUATION 0x00006000    /* Playback attenuation mask. 0 = 0dB, 1 = 6dB, 2 = 12dB, 3 = Mute. */
 136 #define HCFG_PLAYBACK_DITHER    0x00001000      /* 1 = Add dither bit to all playback channels. */
 137 #define HCFG_PLAYBACK_S32_LE    0x00000800      /* 1 = S32_LE, 0 = S16_LE                       */
 138 #define HCFG_CAPTURE_S32_LE     0x00000400      /* 1 = S32_LE, 0 = S16_LE (S32_LE current not working)  */
 139 #define HCFG_8_CHANNEL_PLAY     0x00000200      /* 1 = 8 channels, 0 = 2 channels per substream.*/
 140 #define HCFG_8_CHANNEL_CAPTURE  0x00000100      /* 1 = 8 channels, 0 = 2 channels per substream.*/
 141 #define HCFG_MONO               0x00000080      /* 1 = I2S Input mono                           */
 142 #define HCFG_I2S_OUTPUT         0x00000010      /* 1 = I2S Output disabled                      */
 143 #define HCFG_AC97               0x00000008      /* 0 = AC97 1.0, 1 = AC97 2.0                   */
 144 #define HCFG_LOCK_PLAYBACK_CACHE 0x00000004     /* 1 = Cancel bustmaster accesses to soundcache */
 145                                                 /* NOTE: This should generally never be used.   */
 146 #define HCFG_LOCK_CAPTURE_CACHE 0x00000002      /* 1 = Cancel bustmaster accesses to soundcache */
 147                                                 /* NOTE: This should generally never be used.   */
 148 #define HCFG_AUDIOENABLE        0x00000001      /* 0 = CODECs transmit zero-valued samples      */
 149                                                 /* Should be set to 1 when the EMU10K1 is       */
 150                                                 /* completely initialized.                      */
 151 #define GPIO                    0x18            /* Defaults: 005f03a3-Analog, 005f02a2-SPDIF.   */
 152                                                 /* Here pins 0,1,2,3,4,,6 are output. 5,7 are input */
 153                                                 /* For the Audigy LS, pin 0 (or bit 8) controls the SPDIF/Analog jack. */
 154                                                 /* SB Live 24bit:
 155                                                  * bit 8 0 = SPDIF in and out / 1 = Analog (Mic or Line)-in.
 156                                                  * bit 9 0 = Mute / 1 = Analog out.
 157                                                  * bit 10 0 = Line-in / 1 = Mic-in.
 158                                                  * bit 11 0 = ? / 1 = ?
 159                                                  * bit 12 0 = 48 Khz / 1 = 96 Khz Analog out on SB Live 24bit.
 160                                                  * bit 13 0 = ? / 1 = ?
 161                                                  * bit 14 0 = Mute / 1 = Analog out
 162                                                  * bit 15 0 = ? / 1 = ?
 163                                                  * Both bit 9 and bit 14 have to be set for analog sound to work on the SB Live 24bit.
 164                                                  */
 165                                                 /* 8 general purpose programmable In/Out pins.
 166                                                  * GPI [8:0] Read only. Default 0.
 167                                                  * GPO [15:8] Default 0x9. (Default to SPDIF jack enabled for SPDIF)
 168                                                  * GPO Enable [23:16] Default 0x0f. Setting a bit to 1, causes the pin to be an output pin.
 169                                                  */
 170 #define AC97DATA                0x1c            /* AC97 register set data register (16 bit)     */
 171
 172 #define AC97ADDRESS             0x1e            /* AC97 register set address register (8 bit)   */
 173
 174 /********************************************************************************************************/
 175 /* CA0106 pointer-offset register set, accessed through the PTR and DATA registers                     */
 176 /********************************************************************************************************/
 177
 178 /* Initally all registers from 0x00 to 0x3f have zero contents. */
 179 #define PLAYBACK_LIST_ADDR      0x00            /* Base DMA address of a list of pointers to each period/size */
 180                                                 /* One list entry: 4 bytes for DMA address,
 181                                                  * 4 bytes for period_size << 16.
 182                                                  * One list entry is 8 bytes long.
 183                                                  * One list entry for each period in the buffer.
 184                                                  */
 185                                                 /* ADDR[31:0], Default: 0x0 */
 186 #define PLAYBACK_LIST_SIZE      0x01            /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000  */
 187                                                 /* SIZE[21:16], Default: 0x8 */
 188 #define PLAYBACK_LIST_PTR       0x02            /* Pointer to the current period being played */
 189                                                 /* PTR[5:0], Default: 0x0 */
 190 #define PLAYBACK_UNKNOWN3       0x03            /* Not used ?? */
 191 #define PLAYBACK_DMA_ADDR       0x04            /* Playback DMA addresss */
 192                                                 /* DMA[31:0], Default: 0x0 */
 193 #define PLAYBACK_PERIOD_SIZE    0x05            /* Playback period size. win2000 uses 0x04000000 */
 194                                                 /* SIZE[31:16], Default: 0x0 */
 195 #define PLAYBACK_POINTER        0x06            /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */
 196                                                 /* POINTER[15:0], Default: 0x0 */
 197 #define PLAYBACK_PERIOD_END_ADDR 0x07           /* Playback fifo end address */
 198                                                 /* END_ADDR[15:0], FLAG[16] 0 = don't stop, 1 = stop */
 199 #define PLAYBACK_FIFO_OFFSET_ADDRESS    0x08    /* Current fifo offset address [21:16] */
 200                                                 /* Cache size valid [5:0] */
 201 #define PLAYBACK_UNKNOWN9       0x09            /* 0x9 to 0xf Unused */
 202 #define CAPTURE_DMA_ADDR        0x10            /* Capture DMA address */
 203                                                 /* DMA[31:0], Default: 0x0 */
 204 #define CAPTURE_BUFFER_SIZE     0x11            /* Capture buffer size */
 205                                                 /* SIZE[31:16], Default: 0x0 */
 206 #define CAPTURE_POINTER         0x12            /* Capture buffer pointer. Sample currently in ADC */
 207                                                 /* POINTER[15:0], Default: 0x0 */
 208 #define CAPTURE_FIFO_OFFSET_ADDRESS     0x13    /* Current fifo offset address [21:16] */
 209                                                 /* Cache size valid [5:0] */
 210 #define PLAYBACK_LAST_SAMPLE    0x20            /* The sample currently being played */
 211 /* 0x21 - 0x3f unused */
 212 #define BASIC_INTERRUPT         0x40            /* Used by both playback and capture interrupt handler */
 213                                                 /* Playback (0x1<<channel_id) */
 214                                                 /* Capture  (0x100<<channel_id) */
 215                                                 /* Playback sample rate 96000 = 0x20000 */
 216                                                 /* Start Playback [3:0] (one bit per channel)
 217                                                  * Start Capture [11:8] (one bit per channel)
 218                                                  * Playback rate [23:16] (2 bits per channel) (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
 219                                                  * Playback mixer in enable [27:24] (one bit per channel)
 220                                                  * Playback mixer out enable [31:28] (one bit per channel)
 221                                                  */
 222 /* The Digital out jack is shared with the Center/LFE Analogue output.
 223  * The jack has 4 poles. I will call 1 - Tip, 2 - Next to 1, 3 - Next to 2, 4 - Next to 3
 224  * For Analogue: 1 -> Center Speaker, 2 -> Sub Woofer, 3 -> Ground, 4 -> Ground
 225  * For Digital: 1 -> Front SPDIF, 2 -> Rear SPDIF, 3 -> Center/Subwoofer SPDIF, 4 -> Ground.
 226  * Standard 4 pole Video A/V cable with RCA outputs: 1 -> White, 2 -> Yellow, 3 -> Sheild on all three, 4 -> Red.
 227  * So, from this you can see that you cannot use a Standard 4 pole Video A/V cable with the SB Audigy LS card.
 228  */
 229 /* The Front SPDIF PCM gets mixed with samples from the AC97 codec, so can only work for Stereo PCM and not AC3/DTS
 230  * The Rear SPDIF can be used for Stereo PCM and also AC3/DTS
 231  * The Center/LFE SPDIF cannot be used for AC3/DTS, but can be used for Stereo PCM.
 232  * Summary: For ALSA we use the Rear channel for SPDIF Digital AC3/DTS output
 233  */
 234 /* A standard 2 pole mono mini-jack to RCA plug can be used for SPDIF Stereo PCM output from the Front channel.
 235  * A standard 3 pole stereo mini-jack to 2 RCA plugs can be used for SPDIF AC3/DTS and Stereo PCM output utilising the Rear channel and just one of the RCA plugs.
 236  */
 237 #define SPCS0                   0x41            /* SPDIF output Channel Status 0 register. For Rear. default=0x02108004, non-audio=0x02108006   */
 238 #define SPCS1                   0x42            /* SPDIF output Channel Status 1 register. For Front */
 239 #define SPCS2                   0x43            /* SPDIF output Channel Status 2 register. For Center/LFE */
 240 #define SPCS3                   0x44            /* SPDIF output Channel Status 3 register. Unknown */
 241                                                 /* When Channel set to 0: */
 242 #define SPCS_CLKACCYMASK        0x30000000      /* Clock accuracy                               */
 243 #define SPCS_CLKACCY_1000PPM    0x00000000      /* 1000 parts per million                       */
 244 #define SPCS_CLKACCY_50PPM      0x10000000      /* 50 parts per million                         */
 245 #define SPCS_CLKACCY_VARIABLE   0x20000000      /* Variable accuracy                            */
 246 #define SPCS_SAMPLERATEMASK     0x0f000000      /* Sample rate                                  */
 247 #define SPCS_SAMPLERATE_44      0x00000000      /* 44.1kHz sample rate                          */
 248 #define SPCS_SAMPLERATE_48      0x02000000      /* 48kHz sample rate                            */
 249 #define SPCS_SAMPLERATE_32      0x03000000      /* 32kHz sample rate                            */
 250 #define SPCS_CHANNELNUMMASK     0x00f00000      /* Channel number                               */
 251 #define SPCS_CHANNELNUM_UNSPEC  0x00000000      /* Unspecified channel number                   */
 252 #define SPCS_CHANNELNUM_LEFT    0x00100000      /* Left channel                                 */
 253 #define SPCS_CHANNELNUM_RIGHT   0x00200000      /* Right channel                                */
 254 #define SPCS_SOURCENUMMASK      0x000f0000      /* Source number                                */
 255 #define SPCS_SOURCENUM_UNSPEC   0x00000000      /* Unspecified source number                    */
 256 #define SPCS_GENERATIONSTATUS   0x00008000      /* Originality flag (see IEC-958 spec)          */
 257 #define SPCS_CATEGORYCODEMASK   0x00007f00      /* Category code (see IEC-958 spec)             */
 258 #define SPCS_MODEMASK           0x000000c0      /* Mode (see IEC-958 spec)                      */
 259 #define SPCS_EMPHASISMASK       0x00000038      /* Emphasis                                     */
 260 #define SPCS_EMPHASIS_NONE      0x00000000      /* No emphasis                                  */
 261 #define SPCS_EMPHASIS_50_15     0x00000008      /* 50/15 usec 2 channel                         */
 262 #define SPCS_COPYRIGHT          0x00000004      /* Copyright asserted flag -- do not modify     */
 263 #define SPCS_NOTAUDIODATA       0x00000002      /* 0 = Digital audio, 1 = not audio             */
 264 #define SPCS_PROFESSIONAL       0x00000001      /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992)  */
 265
 266                                                 /* When Channel set to 1: */
 267 #define SPCS_WORD_LENGTH_MASK   0x0000000f      /* Word Length Mask                             */
 268 #define SPCS_WORD_LENGTH_16     0x00000008      /* Word Length 16 bit                           */
 269 #define SPCS_WORD_LENGTH_17     0x00000006      /* Word Length 17 bit                           */
 270 #define SPCS_WORD_LENGTH_18     0x00000004      /* Word Length 18 bit                           */
 271 #define SPCS_WORD_LENGTH_19     0x00000002      /* Word Length 19 bit                           */
 272 #define SPCS_WORD_LENGTH_20A    0x0000000a      /* Word Length 20 bit                           */
 273 #define SPCS_WORD_LENGTH_20     0x00000009      /* Word Length 20 bit (both 0xa and 0x9 are 20 bit) */
 274 #define SPCS_WORD_LENGTH_21     0x00000007      /* Word Length 21 bit                           */
 275 #define SPCS_WORD_LENGTH_22     0x00000005      /* Word Length 22 bit                           */
 276 #define SPCS_WORD_LENGTH_23     0x00000003      /* Word Length 23 bit                           */
 277 #define SPCS_WORD_LENGTH_24     0x0000000b      /* Word Length 24 bit                           */
 278 #define SPCS_ORIGINAL_SAMPLE_RATE_MASK  0x000000f0 /* Original Sample rate                      */
 279 #define SPCS_ORIGINAL_SAMPLE_RATE_NONE  0x00000000 /* Original Sample rate not indicated        */
 280 #define SPCS_ORIGINAL_SAMPLE_RATE_16000 0x00000010 /* Original Sample rate      */
 281 #define SPCS_ORIGINAL_SAMPLE_RATE_RES1  0x00000020 /* Original Sample rate      */
 282 #define SPCS_ORIGINAL_SAMPLE_RATE_32000 0x00000030 /* Original Sample rate      */
 283 #define SPCS_ORIGINAL_SAMPLE_RATE_12000 0x00000040 /* Original Sample rate      */
 284 #define SPCS_ORIGINAL_SAMPLE_RATE_11025 0x00000050 /* Original Sample rate      */
 285 #define SPCS_ORIGINAL_SAMPLE_RATE_8000  0x00000060 /* Original Sample rate      */
 286 #define SPCS_ORIGINAL_SAMPLE_RATE_RES2  0x00000070 /* Original Sample rate      */
 287 #define SPCS_ORIGINAL_SAMPLE_RATE_192000 0x00000080 /* Original Sample rate     */
 288 #define SPCS_ORIGINAL_SAMPLE_RATE_24000 0x00000090 /* Original Sample rate      */
 289 #define SPCS_ORIGINAL_SAMPLE_RATE_96000 0x000000a0 /* Original Sample rate      */
 290 #define SPCS_ORIGINAL_SAMPLE_RATE_48000 0x000000b0 /* Original Sample rate      */
 291 #define SPCS_ORIGINAL_SAMPLE_RATE_176400 0x000000c0 /* Original Sample rate     */
 292 #define SPCS_ORIGINAL_SAMPLE_RATE_22050 0x000000d0 /* Original Sample rate      */
 293 #define SPCS_ORIGINAL_SAMPLE_RATE_88200 0x000000e0 /* Original Sample rate      */
 294 #define SPCS_ORIGINAL_SAMPLE_RATE_44100 0x000000f0 /* Original Sample rate      */
 295
 296 #define SPDIF_SELECT1           0x45            /* Enables SPDIF or Analogue outputs 0-SPDIF, 0xf00-Analogue */
 297                                                 /* 0x100 - Front, 0x800 - Rear, 0x200 - Center/LFE.
 298                                                  * But as the jack is shared, use 0xf00.
 299                                                  * The Windows2000 driver uses 0x0000000f for both digital and analog.
 300                                                  * 0xf00 introduces interesting noises onto the Center/LFE.
 301                                                  * If you turn the volume up, you hear computer noise,
 302                                                  * e.g. mouse moving, changing between app windows etc.
 303                                                  * So, I am going to set this to 0x0000000f all the time now,
 304                                                  * same as the windows driver does.
 305                                                  * Use register SPDIF_SELECT2(0x72) to switch between SPDIF and Analog.
 306                                                  */
 307                                                 /* When Channel = 0:
 308                                                  * Wide SPDIF format [3:0] (one bit for each channel) (0=20bit, 1=24bit)
 309                                                  * Tristate SPDIF Output [11:8] (one bit for each channel) (0=Not tristate, 1=Tristate)
 310                                                  * SPDIF Bypass enable [19:16] (one bit for each channel) (0=Not bypass, 1=Bypass)
 311                                                  */
 312                                                 /* When Channel = 1:
 313                                                  * SPDIF 0 User data [7:0]
 314                                                  * SPDIF 1 User data [15:8]
 315                                                  * SPDIF 0 User data [23:16]
 316                                                  * SPDIF 0 User data [31:24]
 317                                                  * User data can be sent by using the SPDIF output frame pending and SPDIF output user bit interrupts.
 318                                                  */
 319 #define WATERMARK               0x46            /* Test bit to indicate cache usage level */
 320 #define SPDIF_INPUT_STATUS      0x49            /* SPDIF Input status register. Bits the same as SPCS.
 321                                                  * When Channel = 0: Bits the same as SPCS channel 0.
 322                                                  * When Channel = 1: Bits the same as SPCS channel 1.
 323                                                  * When Channel = 2:
 324                                                  * SPDIF Input User data [16:0]
 325                                                  * SPDIF Input Frame count [21:16]
 326                                                  */
 327 #define CAPTURE_CACHE_DATA      0x50            /* 0x50-0x5f Recorded samples. */
 328 #define CAPTURE_SOURCE          0x60            /* Capture Source 0 = MIC */
 329 #define CAPTURE_SOURCE_CHANNEL0 0xf0000000      /* Mask for selecting the Capture sources */
 330 #define CAPTURE_SOURCE_CHANNEL1 0x0f000000      /* 0 - SPDIF mixer output. */
 331 #define CAPTURE_SOURCE_CHANNEL2 0x00f00000      /* 1 - What you hear or . 2 - ?? */
 332 #define CAPTURE_SOURCE_CHANNEL3 0x000f0000      /* 3 - Mic in, Line in, TAD in, Aux in. */
 333 #define CAPTURE_SOURCE_RECORD_MAP 0x0000ffff    /* Default 0x00e4 */
 334                                                 /* Record Map [7:0] (2 bits per channel) 0=mapped to channel 0, 1=mapped to channel 1, 2=mapped to channel2, 3=mapped to channel3
 335                                                  * Record source select for channel 0 [18:16]
 336                                                  * Record source select for channel 1 [22:20]
 337                                                  * Record source select for channel 2 [26:24]
 338                                                  * Record source select for channel 3 [30:28]
 339                                                  * 0 - SPDIF mixer output.
 340                                                  * 1 - i2s mixer output.
 341                                                  * 2 - SPDIF input.
 342                                                  * 3 - i2s input.
 343                                                  * 4 - AC97 capture.
 344                                                  * 5 - SRC output.
 345                                                  */
 346 #define CAPTURE_VOLUME1         0x61            /* Capture  volume per channel 0-3 */
 347 #define CAPTURE_VOLUME2         0x62            /* Capture  volume per channel 4-7 */
 348
 349 #define PLAYBACK_ROUTING1       0x63            /* Playback routing of channels 0-7. Effects AC3 output. Default 0x32765410 */
 350 #define ROUTING1_REAR           0x77000000      /* Channel_id 0 sends to 10, Channel_id 1 sends to 32 */
 351 #define ROUTING1_NULL           0x00770000      /* Channel_id 2 sends to 54, Channel_id 3 sends to 76 */
 352 #define ROUTING1_CENTER_LFE     0x00007700      /* 0x32765410 means, send Channel_id 0 to FRONT, Channel_id 1 to REAR */
 353 #define ROUTING1_FRONT          0x00000077      /* Channel_id 2 to CENTER_LFE, Channel_id 3 to NULL. */
 354                                                 /* Channel_id's handle stereo channels. Channel X is a single mono channel */
 355                                                 /* Host is input from the PCI bus. */
 356                                                 /* Host channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7.
 357                                                  * Host channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.
 358                                                  * Host channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.
 359                                                  * Host channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7.
 360                                                  * Host channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7.
 361                                                  * Host channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7.
 362                                                  * Host channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7.
 363                                                  * Host channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7.
 364                                                  */
 365
 366 #define PLAYBACK_ROUTING2       0x64            /* Playback Routing . Feeding Capture channels back into Playback. Effects AC3 output. Default 0x76767676 */
 367                                                 /* SRC is input from the capture inputs. */
 368                                                 /* SRC channel 0 [2:0] -> SPDIF Mixer/Router channel 0-7.
 369                                                  * SRC channel 1 [6:4] -> SPDIF Mixer/Router channel 0-7.
 370                                                  * SRC channel 2 [10:8] -> SPDIF Mixer/Router channel 0-7.
 371                                                  * SRC channel 3 [14:12] -> SPDIF Mixer/Router channel 0-7.
 372                                                  * SRC channel 4 [18:16] -> SPDIF Mixer/Router channel 0-7.
 373                                                  * SRC channel 5 [22:20] -> SPDIF Mixer/Router channel 0-7.
 374                                                  * SRC channel 6 [26:24] -> SPDIF Mixer/Router channel 0-7.
 375                                                  * SRC channel 7 [30:28] -> SPDIF Mixer/Router channel 0-7.
 376                                                  */
 377
 378 #define PLAYBACK_MUTE           0x65            /* Unknown. While playing 0x0, while silent 0x00fc0000 */
 379                                                 /* SPDIF Mixer input control:
 380                                                  * Invert SRC to SPDIF Mixer [7-0] (One bit per channel)
 381                                                  * Invert Host to SPDIF Mixer [15:8] (One bit per channel)
 382                                                  * SRC to SPDIF Mixer disable [23:16] (One bit per channel)
 383                                                  * Host to SPDIF Mixer disable [31:24] (One bit per channel)
 384                                                  */
 385 #define PLAYBACK_VOLUME1        0x66            /* Playback SPDIF volume per channel. Set to the same PLAYBACK_VOLUME(0x6a) */
 386                                                 /* PLAYBACK_VOLUME1 must be set to 30303030 for SPDIF AC3 Playback */
 387                                                 /* SPDIF mixer input volume. 0=12dB, 0x30=0dB, 0xFE=-51.5dB, 0xff=Mute */
 388                                                 /* One register for each of the 4 stereo streams. */
 389                                                 /* SRC Right volume [7:0]
 390                                                  * SRC Left  volume [15:8]
 391                                                  * Host Right volume [23:16]
 392                                                  * Host Left  volume [31:24]
 393                                                  */
 394 #define CAPTURE_ROUTING1        0x67            /* Capture Routing. Default 0x32765410 */
 395                                                 /* Similar to register 0x63, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */
 396 #define CAPTURE_ROUTING2        0x68            /* Unknown Routing. Default 0x76767676 */
 397                                                 /* Similar to register 0x64, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */
 398 #define CAPTURE_MUTE            0x69            /* Unknown. While capturing 0x0, while silent 0x00fc0000 */
 399                                                 /* Similar to register 0x65, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */
 400 #define PLAYBACK_VOLUME2        0x6a            /* Playback Analog volume per channel. Does not effect AC3 output */
 401                                                 /* Similar to register 0x66, except that the destination is the I2S mixer instead of the SPDIF mixer. I.E. Outputs to the Analog outputs instead of SPDIF. */
 402 #define UNKNOWN6b               0x6b            /* Unknown. Readonly. Default 00400000 00400000 00400000 00400000 */
 403 #define MIDI_UART_A_DATA                0x6c            /* Midi Uart A Data */
 404 #define MIDI_UART_A_CMD         0x6d            /* Midi Uart A Command/Status */
 405 #define MIDI_UART_B_DATA                0x6e            /* Midi Uart B Data (currently unused) */
 406 #define MIDI_UART_B_CMD         0x6f            /* Midi Uart B Command/Status (currently unused) */
 407
 408 /* unique channel identifier for midi->channel */
 409
 410 #define CA0106_MIDI_CHAN_A              0x1
 411 #define CA0106_MIDI_CHAN_B              0x2
 412
 413 /* from mpu401 */
 414
 415 #define CA0106_MIDI_INPUT_AVAIL         0x80
 416 #define CA0106_MIDI_OUTPUT_READY        0x40
 417 #define CA0106_MPU401_RESET             0xff
 418 #define CA0106_MPU401_ENTER_UART        0x3f
 419 #define CA0106_MPU401_ACK               0xfe
 420
 421 #define SAMPLE_RATE_TRACKER_STATUS 0x70         /* Readonly. Default 00108000 00108000 00500000 00500000 */
 422                                                 /* Estimated sample rate [19:0] Relative to 48kHz. 0x8000 =  1.0
 423                                                  * Rate Locked [20]
 424                                                  * SPDIF Locked [21] For SPDIF channel only.
 425                                                  * Valid Audio [22] For SPDIF channel only.
 426                                                  */
 427 #define CAPTURE_CONTROL         0x71            /* Some sort of routing. default = 40c81000 30303030 30300000 00700000 */
 428                                                 /* Channel_id 0: 0x40c81000 must be changed to 0x40c80000 for SPDIF AC3 input or output. */
 429                                                 /* Channel_id 1: 0xffffffff(mute) 0x30303030(max) controls CAPTURE feedback into PLAYBACK. */
 430                                                 /* Sample rate output control register Channel=0
 431                                                  * Sample output rate [1:0] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
 432                                                  * Sample input rate [3:2] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
 433                                                  * SRC input source select [4] 0=Audio from digital mixer, 1=Audio from analog source.
 434                                                  * Record rate [9:8] (0=48kHz, 1=Not available, 2=96kHz, 3=192Khz)
 435                                                  * Record mixer output enable [12:10]
 436                                                  * I2S input rate master mode [15:14] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
 437                                                  * I2S output rate [17:16] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
 438                                                  * I2S output source select [18] (0=Audio from host, 1=Audio from SRC)
 439                                                  * Record mixer I2S enable [20:19] (enable/disable i2sin1 and i2sin0)
 440                                                  * I2S output master clock select [21] (0=256*I2S output rate, 1=512*I2S output rate.)
 441                                                  * I2S input master clock select [22] (0=256*I2S input rate, 1=512*I2S input rate.)
 442                                                  * I2S input mode [23] (0=Slave, 1=Master)
 443                                                  * SPDIF output rate [25:24] (0=48kHz, 1=44.1kHz, 2=96kHz, 3=192Khz)
 444                                                  * SPDIF output source select [26] (0=host, 1=SRC)
 445                                                  * Not used [27]
 446                                                  * Record Source 0 input [29:28] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)
 447                                                  * Record Source 1 input [31:30] (0=SPDIF in, 1=I2S in, 2=AC97 Mic, 3=AC97 PCM)
 448                                                  */
 449                                                 /* Sample rate output control register Channel=1
 450                                                  * I2S Input 0 volume Right [7:0]
 451                                                  * I2S Input 0 volume Left [15:8]
 452                                                  * I2S Input 1 volume Right [23:16]
 453                                                  * I2S Input 1 volume Left [31:24]
 454                                                  */
 455                                                 /* Sample rate output control register Channel=2
 456                                                  * SPDIF Input volume Right [23:16]
 457                                                  * SPDIF Input volume Left [31:24]
 458                                                  */
 459                                                 /* Sample rate output control register Channel=3
 460                                                  * No used
 461                                                  */
 462 #define SPDIF_SELECT2           0x72            /* Some sort of routing. Channel_id 0 only. default = 0x0f0f003f. Analog 0x000b0000, Digital 0x0b000000 */
 463 #define ROUTING2_FRONT_MASK     0x00010000      /* Enable for Front speakers. */
 464 #define ROUTING2_CENTER_LFE_MASK 0x00020000     /* Enable for Center/LFE speakers. */
 465 #define ROUTING2_REAR_MASK      0x00080000      /* Enable for Rear speakers. */
 466                                                 /* Audio output control
 467                                                  * AC97 output enable [5:0]
 468                                                  * I2S output enable [19:16]
 469                                                  * SPDIF output enable [27:24]
 470                                                  */
 471 #define UNKNOWN73               0x73            /* Unknown. Readonly. Default 0x0 */
 472 #define CHIP_VERSION            0x74            /* P17 Chip version. Channel_id 0 only. Default 00000071 */
 473 #define EXTENDED_INT_MASK       0x75            /* Used by both playback and capture interrupt handler */
 474                                                 /* Sets which Interrupts are enabled. */
 475                                                 /* 0x00000001 = Half period. Playback.
 476                                                  * 0x00000010 = Full period. Playback.
 477                                                  * 0x00000100 = Half buffer. Playback.
 478                                                  * 0x00001000 = Full buffer. Playback.
 479                                                  * 0x00010000 = Half buffer. Capture.
 480                                                  * 0x00100000 = Full buffer. Capture.
 481                                                  * Capture can only do 2 periods.
 482                                                  * 0x01000000 = End audio. Playback.
 483                                                  * 0x40000000 = Half buffer Playback,Caputre xrun.
 484                                                  * 0x80000000 = Full buffer Playback,Caputre xrun.
 485                                                  */
 486 #define EXTENDED_INT            0x76            /* Used by both playback and capture interrupt handler */
 487                                                 /* Shows which interrupts are active at the moment. */
 488                                                 /* Same bit layout as EXTENDED_INT_MASK */
 489 #define COUNTER77               0x77            /* Counter range 0 to 0x3fffff, 192000 counts per second. */
 490 #define COUNTER78               0x78            /* Counter range 0 to 0x3fffff, 44100 counts per second. */
 491 #define EXTENDED_INT_TIMER      0x79            /* Channel_id 0 only. Used by both playback and capture interrupt handler */
 492                                                 /* Causes interrupts based on timer intervals. */
 493 #define SPI                     0x7a            /* SPI: Serial Interface Register */
 494 #define I2C_A                   0x7b            /* I2C Address. 32 bit */
 495 #define I2C_D0                  0x7c            /* I2C Data Port 0. 32 bit */
 496 #define I2C_D1                  0x7d            /* I2C Data Port 1. 32 bit */
 497 //I2C values
 498 #define I2C_A_ADC_ADD_MASK      0x000000fe      //The address is a 7 bit address
 499 #define I2C_A_ADC_RW_MASK       0x00000001      //bit mask for R/W
 500 #define I2C_A_ADC_TRANS_MASK    0x00000010      //Bit mask for I2c address DAC value
 501 #define I2C_A_ADC_ABORT_MASK    0x00000020      //Bit mask for I2C transaction abort flag
 502 #define I2C_A_ADC_LAST_MASK     0x00000040      //Bit mask for Last word transaction
 503 #define I2C_A_ADC_BYTE_MASK     0x00000080      //Bit mask for Byte Mode
 504
 505 #define I2C_A_ADC_ADD           0x00000034      //This is the Device address for ADC
 506 #define I2C_A_ADC_READ          0x00000001      //To perform a read operation
 507 #define I2C_A_ADC_START         0x00000100      //Start I2C transaction
 508 #define I2C_A_ADC_ABORT         0x00000200      //I2C transaction abort
 509 #define I2C_A_ADC_LAST          0x00000400      //I2C last transaction
 510 #define I2C_A_ADC_BYTE          0x00000800      //I2C one byte mode
 511
 512 #define I2C_D_ADC_REG_MASK      0xfe000000      //ADC address register
 513 #define I2C_D_ADC_DAT_MASK      0x01ff0000      //ADC data register
 514
 515 #define ADC_TIMEOUT             0x00000007      //ADC Timeout Clock Disable
 516 #define ADC_IFC_CTRL            0x0000000b      //ADC Interface Control
 517 #define ADC_MASTER              0x0000000c      //ADC Master Mode Control
 518 #define ADC_POWER               0x0000000d      //ADC PowerDown Control
 519 #define ADC_ATTEN_ADCL          0x0000000e      //ADC Attenuation ADCL
 520 #define ADC_ATTEN_ADCR          0x0000000f      //ADC Attenuation ADCR
 521 #define ADC_ALC_CTRL1           0x00000010      //ADC ALC Control 1
 522 #define ADC_ALC_CTRL2           0x00000011      //ADC ALC Control 2
 523 #define ADC_ALC_CTRL3           0x00000012      //ADC ALC Control 3
 524 #define ADC_NOISE_CTRL          0x00000013      //ADC Noise Gate Control
 525 #define ADC_LIMIT_CTRL          0x00000014      //ADC Limiter Control
 526 #define ADC_MUX                 0x00000015      //ADC Mux offset
 527
 528 #if 0
 529 /* FIXME: Not tested yet. */
 530 #define ADC_GAIN_MASK           0x000000ff      //Mask for ADC Gain
 531 #define ADC_ZERODB              0x000000cf      //Value to set ADC to 0dB
 532 #define ADC_MUTE_MASK           0x000000c0      //Mask for ADC mute
 533 #define ADC_MUTE                0x000000c0      //Value to mute ADC
 534 #define ADC_OSR                 0x00000008      //Mask for ADC oversample rate select
 535 #define ADC_TIMEOUT_DISABLE     0x00000008      //Value and mask to disable Timeout clock
 536 #define ADC_HPF_DISABLE         0x00000100      //Value and mask to disable High pass filter
 537 #define ADC_TRANWIN_MASK        0x00000070      //Mask for Length of Transient Window
 538 #endif
 539
 540 #define ADC_MUX_MASK            0x0000000f      //Mask for ADC Mux
 541 #define ADC_MUX_PHONE           0x00000001      //Value to select TAD at ADC Mux (Not used)
 542 #define ADC_MUX_MIC             0x00000002      //Value to select Mic at ADC Mux
 543 #define ADC_MUX_LINEIN          0x00000004      //Value to select LineIn at ADC Mux
 544 #define ADC_MUX_AUX             0x00000008      //Value to select Aux at ADC Mux
 545
 546 #define SET_CHANNEL 0  /* Testing channel outputs 0=Front, 1=Center/LFE, 2=Unknown, 3=Rear */
 547 #define PCM_FRONT_CHANNEL 0
 548 #define PCM_REAR_CHANNEL 1
 549 #define PCM_CENTER_LFE_CHANNEL 2
 550 #define PCM_UNKNOWN_CHANNEL 3
 551 #define CONTROL_FRONT_CHANNEL 0
 552 #define CONTROL_REAR_CHANNEL 3
 553 #define CONTROL_CENTER_LFE_CHANNEL 1
 554 #define CONTROL_UNKNOWN_CHANNEL 2
 555
 556
 557 /* Based on WM8768 Datasheet Rev 4.2 page 32 */
 558 #define SPI_REG_MASK    0x1ff   /* 16-bit SPI writes have a 7-bit address */
 559 #define SPI_REG_SHIFT   9       /* followed by 9 bits of data */
 560
 561 #define SPI_LDA1_REG            0       /* digital attenuation */
 562 #define SPI_RDA1_REG            1
 563 #define SPI_LDA2_REG            4
 564 #define SPI_RDA2_REG            5
 565 #define SPI_LDA3_REG            6
 566 #define SPI_RDA3_REG            7
 567 #define SPI_LDA4_REG            13
 568 #define SPI_RDA4_REG            14
 569 #define SPI_MASTDA_REG          8
 570
 571 #define SPI_DA_BIT_UPDATE       (1<<8)  /* update attenuation values */
 572 #define SPI_DA_BIT_0dB          0xff    /* 0 dB */
 573 #define SPI_DA_BIT_infdB        0x00    /* inf dB attenuation (mute) */
 574
 575 #define SPI_PL_REG              2
 576 #define SPI_PL_BIT_L_M          (0<<5)  /* left channel = mute */
 577 #define SPI_PL_BIT_L_L          (1<<5)  /* left channel = left */
 578 #define SPI_PL_BIT_L_R          (2<<5)  /* left channel = right */
 579 #define SPI_PL_BIT_L_C          (3<<5)  /* left channel = (L+R)/2 */
 580 #define SPI_PL_BIT_R_M          (0<<7)  /* right channel = mute */
 581 #define SPI_PL_BIT_R_L          (1<<7)  /* right channel = left */
 582 #define SPI_PL_BIT_R_R          (2<<7)  /* right channel = right */
 583 #define SPI_PL_BIT_R_C          (3<<7)  /* right channel = (L+R)/2 */
 584 #define SPI_IZD_REG             2
 585 #define SPI_IZD_BIT             (1<<4)  /* infinite zero detect */
 586
 587 #define SPI_FMT_REG             3
 588 #define SPI_FMT_BIT_RJ          (0<<0)  /* right justified mode */
 589 #define SPI_FMT_BIT_LJ          (1<<0)  /* left justified mode */
 590 #define SPI_FMT_BIT_I2S         (2<<0)  /* I2S mode */
 591 #define SPI_FMT_BIT_DSP         (3<<0)  /* DSP Modes A or B */
 592 #define SPI_LRP_REG             3
 593 #define SPI_LRP_BIT             (1<<2)  /* invert LRCLK polarity */
 594 #define SPI_BCP_REG             3
 595 #define SPI_BCP_BIT             (1<<3)  /* invert BCLK polarity */
 596 #define SPI_IWL_REG             3
 597 #define SPI_IWL_BIT_16          (0<<4)  /* 16-bit world length */
 598 #define SPI_IWL_BIT_20          (1<<4)  /* 20-bit world length */
 599 #define SPI_IWL_BIT_24          (2<<4)  /* 24-bit world length */
 600 #define SPI_IWL_BIT_32          (3<<4)  /* 32-bit world length */
 601
 602 #define SPI_MS_REG              10
 603 #define SPI_MS_BIT              (1<<5)  /* master mode */
 604 #define SPI_RATE_REG            10      /* only applies in master mode */
 605 #define SPI_RATE_BIT_128        (0<<6)  /* MCLK = LRCLK * 128 */
 606 #define SPI_RATE_BIT_192        (1<<6)
 607 #define SPI_RATE_BIT_256        (2<<6)
 608 #define SPI_RATE_BIT_384        (3<<6)
 609 #define SPI_RATE_BIT_512        (4<<6)
 610 #define SPI_RATE_BIT_768        (5<<6)
 611
 612 /* They really do label the bit for the 4th channel "4" and not "3" */
 613 #define SPI_DMUTE0_REG          9
 614 #define SPI_DMUTE1_REG          9
 615 #define SPI_DMUTE2_REG          9
 616 #define SPI_DMUTE4_REG          15
 617 #define SPI_DMUTE0_BIT          (1<<3)
 618 #define SPI_DMUTE1_BIT          (1<<4)
 619 #define SPI_DMUTE2_BIT          (1<<5)
 620 #define SPI_DMUTE4_BIT          (1<<2)
 621
 622 #define SPI_PHASE0_REG          3
 623 #define SPI_PHASE1_REG          3
 624 #define SPI_PHASE2_REG          3
 625 #define SPI_PHASE4_REG          15
 626 #define SPI_PHASE0_BIT          (1<<6)
 627 #define SPI_PHASE1_BIT          (1<<7)
 628 #define SPI_PHASE2_BIT          (1<<8)
 629 #define SPI_PHASE4_BIT          (1<<3)
 630
 631 #define SPI_PDWN_REG            2       /* power down all DACs */
 632 #define SPI_PDWN_BIT            (1<<2)
 633 #define SPI_DACD0_REG           10      /* power down individual DACs */
 634 #define SPI_DACD1_REG           10
 635 #define SPI_DACD2_REG           10
 636 #define SPI_DACD4_REG           15
 637 #define SPI_DACD0_BIT           (1<<1)
 638 #define SPI_DACD1_BIT           (1<<2)
 639 #define SPI_DACD2_BIT           (1<<3)
 640 #define SPI_DACD4_BIT           (1<<0)  /* datasheet error says it's 1 */
 641
 642 #define SPI_PWRDNALL_REG        10      /* power down everything */
 643 #define SPI_PWRDNALL_BIT        (1<<4)
 644
 645 #include "ca_midi.h"
 646
 647 struct snd_ca0106;
 648
 649 struct snd_ca0106_channel {
 650         struct snd_ca0106 *emu;
 651         int number;
 652         int use;
 653         void (*interrupt)(struct snd_ca0106 *emu, struct snd_ca0106_channel *channel);
 654         struct snd_ca0106_pcm *epcm;
 655 };
 656
 657 struct snd_ca0106_pcm {
 658         struct snd_ca0106 *emu;
 659         struct snd_pcm_substream *substream;
 660         int channel_id;
 661         unsigned short running;
 662 };
 663
 664 struct snd_ca0106_details {
 665         u32 serial;
 666         char * name;
 667         int ac97;
 668         int gpio_type;
 669         int i2c_adc;
 670         int spi_dac;
 671 };
 672
 673 // definition of the chip-specific record
 674 struct snd_ca0106 {
 675         struct snd_card *card;
 676         struct snd_ca0106_details *details;
 677         struct pci_dev *pci;
 678
 679         unsigned long port;
 680         struct resource *res_port;
 681         int irq;
 682
 683         unsigned int serial;            /* serial number */
 684         unsigned short model;           /* subsystem id */
 685
 686         spinlock_t emu_lock;
 687
 688         struct snd_ac97 *ac97;
 689         struct snd_pcm *pcm;
 690
 691         struct snd_ca0106_channel playback_channels[4];
 692         struct snd_ca0106_channel capture_channels[4];
 693         u32 spdif_bits[4];             /* s/pdif out setup */
 694         int spdif_enable;
 695         int capture_source;
 696         int i2c_capture_source;
 697         u8 i2c_capture_volume[4][2];
 698         int capture_mic_line_in;
 699
 700         struct snd_dma_buffer buffer;
 701
 702         struct snd_ca_midi midi;
 703         struct snd_ca_midi midi2;
 704
 705         u16 spi_dac_reg[16];
 706 };
 707
 708 int snd_ca0106_mixer(struct snd_ca0106 *emu);
 709 int snd_ca0106_proc_init(struct snd_ca0106 * emu);
 710
 711 unsigned int snd_ca0106_ptr_read(struct snd_ca0106 * emu,
 712                                  unsigned int reg,
 713                                  unsigned int chn);
 714
 715 void snd_ca0106_ptr_write(struct snd_ca0106 *emu,
 716                           unsigned int reg,
 717                           unsigned int chn,
 718                           unsigned int data);
 719
 720 int snd_ca0106_i2c_write(struct snd_ca0106 *emu, u32 reg, u32 value);
 721
 722 int snd_ca0106_spi_write(struct snd_ca0106 * emu,
 723                                    unsigned int data);