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Merge branch 'next' of git://selinuxproject.org/~jmorris/linux-security
[linux-btrfs-devel.git] / arch / arm / mach-integrator / integrator_ap.c
blob8cdc730dcb3a1bc273da69cc036c974f6cf34ca6
1 /*
2 * linux/arch/arm/mach-integrator/integrator_ap.c
3 *
4 * Copyright (C) 2000-2003 Deep Blue Solutions Ltd
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/platform_device.h>
25 #include <linux/slab.h>
26 #include <linux/string.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/amba/bus.h>
29 #include <linux/amba/kmi.h>
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/interrupt.h>
33 #include <linux/io.h>
34 #include <linux/mtd/physmap.h>
35 #include <video/vga.h>
36
37 #include <mach/hardware.h>
38 #include <mach/platform.h>
39 #include <asm/hardware/arm_timer.h>
40 #include <asm/irq.h>
41 #include <asm/setup.h>
42 #include <asm/param.h> /* HZ */
43 #include <asm/mach-types.h>
44
45 #include <mach/lm.h>
46
47 #include <asm/mach/arch.h>
48 #include <asm/mach/irq.h>
49 #include <asm/mach/map.h>
50 #include <asm/mach/time.h>
51
52 #include <plat/fpga-irq.h>
53
54 #include "common.h"
55
56 /*
57 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
58 * is the (PA >> 12).
59 *
60 * Setup a VA for the Integrator interrupt controller (for header #0,
61 * just for now).
62 */
63 #define VA_IC_BASE __io_address(INTEGRATOR_IC_BASE)
64 #define VA_SC_BASE __io_address(INTEGRATOR_SC_BASE)
65 #define VA_EBI_BASE __io_address(INTEGRATOR_EBI_BASE)
66 #define VA_CMIC_BASE __io_address(INTEGRATOR_HDR_IC)
67
68 /*
69 * Logical Physical
70 * e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
71 * ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
72 * ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
73 * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
74 * ef000000 Cache flush
75 * f1000000 10000000 Core module registers
76 * f1100000 11000000 System controller registers
77 * f1200000 12000000 EBI registers
78 * f1300000 13000000 Counter/Timer
79 * f1400000 14000000 Interrupt controller
80 * f1600000 16000000 UART 0
81 * f1700000 17000000 UART 1
82 * f1a00000 1a000000 Debug LEDs
83 * f1b00000 1b000000 GPIO
84 */
85
86 static struct map_desc ap_io_desc[] __initdata = {
87 {
88 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
89 .pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
90 .length = SZ_4K,
91 .type = MT_DEVICE
92 }, {
93 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE),
94 .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE),
95 .length = SZ_4K,
96 .type = MT_DEVICE
97 }, {
98 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE),
99 .pfn = __phys_to_pfn(INTEGRATOR_EBI_BASE),
100 .length = SZ_4K,
101 .type = MT_DEVICE
102 }, {
103 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
104 .pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
105 .length = SZ_4K,
106 .type = MT_DEVICE
107 }, {
108 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
109 .pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
110 .length = SZ_4K,
111 .type = MT_DEVICE
112 }, {
113 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
114 .pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
115 .length = SZ_4K,
116 .type = MT_DEVICE
117 }, {
118 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE),
119 .pfn = __phys_to_pfn(INTEGRATOR_UART1_BASE),
120 .length = SZ_4K,
121 .type = MT_DEVICE
122 }, {
123 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
124 .pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
125 .length = SZ_4K,
126 .type = MT_DEVICE
127 }, {
128 .virtual = IO_ADDRESS(INTEGRATOR_AP_GPIO_BASE),
129 .pfn = __phys_to_pfn(INTEGRATOR_AP_GPIO_BASE),
130 .length = SZ_4K,
131 .type = MT_DEVICE
132 }, {
133 .virtual = PCI_MEMORY_VADDR,
134 .pfn = __phys_to_pfn(PHYS_PCI_MEM_BASE),
135 .length = SZ_16M,
136 .type = MT_DEVICE
137 }, {
138 .virtual = PCI_CONFIG_VADDR,
139 .pfn = __phys_to_pfn(PHYS_PCI_CONFIG_BASE),
140 .length = SZ_16M,
141 .type = MT_DEVICE
142 }, {
143 .virtual = PCI_V3_VADDR,
144 .pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
145 .length = SZ_64K,
146 .type = MT_DEVICE
147 }, {
148 .virtual = PCI_IO_VADDR,
149 .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
150 .length = SZ_64K,
151 .type = MT_DEVICE
152 }
153 };
154
155 static void __init ap_map_io(void)
156 {
157 iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
158 vga_base = PCI_MEMORY_VADDR;
159 }
160
161 #define INTEGRATOR_SC_VALID_INT 0x003fffff
162
163 static struct fpga_irq_data sc_irq_data = {
164 .base = VA_IC_BASE,
165 .irq_start = 0,
166 .chip.name = "SC",
167 };
168
169 static void __init ap_init_irq(void)
170 {
171 /* Disable all interrupts initially. */
172 /* Do the core module ones */
173 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
174
175 /* do the header card stuff next */
176 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
177 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
178
179 fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
180 }
181
182 #ifdef CONFIG_PM
183 static unsigned long ic_irq_enable;
184
185 static int irq_suspend(void)
186 {
187 ic_irq_enable = readl(VA_IC_BASE + IRQ_ENABLE);
188 return 0;
189 }
190
191 static void irq_resume(void)
192 {
193 /* disable all irq sources */
194 writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR);
195 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
196 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
197
198 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET);
199 }
200 #else
201 #define irq_suspend NULL
202 #define irq_resume NULL
203 #endif
204
205 static struct syscore_ops irq_syscore_ops = {
206 .suspend = irq_suspend,
207 .resume = irq_resume,
208 };
209
210 static int __init irq_syscore_init(void)
211 {
212 register_syscore_ops(&irq_syscore_ops);
213
214 return 0;
215 }
216
217 device_initcall(irq_syscore_init);
218
219 /*
220 * Flash handling.
221 */
222 #define SC_CTRLC (VA_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
223 #define SC_CTRLS (VA_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
224 #define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
225 #define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
226
227 static int ap_flash_init(struct platform_device *dev)
228 {
229 u32 tmp;
230
231 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
232
233 tmp = readl(EBI_CSR1) | INTEGRATOR_EBI_WRITE_ENABLE;
234 writel(tmp, EBI_CSR1);
235
236 if (!(readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE)) {
237 writel(0xa05f, EBI_LOCK);
238 writel(tmp, EBI_CSR1);
239 writel(0, EBI_LOCK);
240 }
241 return 0;
242 }
243
244 static void ap_flash_exit(struct platform_device *dev)
245 {
246 u32 tmp;
247
248 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, SC_CTRLC);
249
250 tmp = readl(EBI_CSR1) & ~INTEGRATOR_EBI_WRITE_ENABLE;
251 writel(tmp, EBI_CSR1);
252
253 if (readl(EBI_CSR1) & INTEGRATOR_EBI_WRITE_ENABLE) {
254 writel(0xa05f, EBI_LOCK);
255 writel(tmp, EBI_CSR1);
256 writel(0, EBI_LOCK);
257 }
258 }
259
260 static void ap_flash_set_vpp(struct platform_device *pdev, int on)
261 {
262 void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
263
264 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
265 }
266
267 static struct physmap_flash_data ap_flash_data = {
268 .width = 4,
269 .init = ap_flash_init,
270 .exit = ap_flash_exit,
271 .set_vpp = ap_flash_set_vpp,
272 };
273
274 static struct resource cfi_flash_resource = {
275 .start = INTEGRATOR_FLASH_BASE,
276 .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1,
277 .flags = IORESOURCE_MEM,
278 };
279
280 static struct platform_device cfi_flash_device = {
281 .name = "physmap-flash",
282 .id = 0,
283 .dev = {
284 .platform_data = &ap_flash_data,
285 },
286 .num_resources = 1,
287 .resource = &cfi_flash_resource,
288 };
289
290 static void __init ap_init(void)
291 {
292 unsigned long sc_dec;
293 int i;
294
295 platform_device_register(&cfi_flash_device);
296
297 sc_dec = readl(VA_SC_BASE + INTEGRATOR_SC_DEC_OFFSET);
298 for (i = 0; i < 4; i++) {
299 struct lm_device *lmdev;
300
301 if ((sc_dec & (16 << i)) == 0)
302 continue;
303
304 lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL);
305 if (!lmdev)
306 continue;
307
308 lmdev->resource.start = 0xc0000000 + 0x10000000 * i;
309 lmdev->resource.end = lmdev->resource.start + 0x0fffffff;
310 lmdev->resource.flags = IORESOURCE_MEM;
311 lmdev->irq = IRQ_AP_EXPINT0 + i;
312 lmdev->id = i;
313
314 lm_device_register(lmdev);
315 }
316 }
317
318 /*
319 * Where is the timer (VA)?
320 */
321 #define TIMER0_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER0_BASE)
322 #define TIMER1_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER1_BASE)
323 #define TIMER2_VA_BASE IO_ADDRESS(INTEGRATOR_TIMER2_BASE)
324
325 /*
326 * How long is the timer interval?
327 */
328 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
329 #if TIMER_INTERVAL >= 0x100000
330 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
331 #elif TIMER_INTERVAL >= 0x10000
332 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
333 #else
334 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
335 #endif
336
337 static unsigned long timer_reload;
338
339 static void integrator_clocksource_init(u32 khz)
340 {
341 void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
342 u32 ctrl = TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC;
343
344 if (khz >= 1500) {
345 khz /= 16;
346 ctrl |= TIMER_CTRL_DIV16;
347 }
348
349 writel(0xffff, base + TIMER_LOAD);
350 writel(ctrl, base + TIMER_CTRL);
351
352 clocksource_mmio_init(base + TIMER_VALUE, "timer2",
353 khz * 1000, 200, 16, clocksource_mmio_readl_down);
354 }
355
356 static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
357
358 /*
359 * IRQ handler for the timer
360 */
361 static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
362 {
363 struct clock_event_device *evt = dev_id;
364
365 /* clear the interrupt */
366 writel(1, clkevt_base + TIMER_INTCLR);
367
368 evt->event_handler(evt);
369
370 return IRQ_HANDLED;
371 }
372
373 static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
374 {
375 u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
376
377 BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
378
379 if (mode == CLOCK_EVT_MODE_PERIODIC) {
380 writel(ctrl, clkevt_base + TIMER_CTRL);
381 writel(timer_reload, clkevt_base + TIMER_LOAD);
382 ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
383 }
384
385 writel(ctrl, clkevt_base + TIMER_CTRL);
386 }
387
388 static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
389 {
390 unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
391
392 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
393 writel(next, clkevt_base + TIMER_LOAD);
394 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
395
396 return 0;
397 }
398
399 static struct clock_event_device integrator_clockevent = {
400 .name = "timer1",
401 .shift = 34,
402 .features = CLOCK_EVT_FEAT_PERIODIC,
403 .set_mode = clkevt_set_mode,
404 .set_next_event = clkevt_set_next_event,
405 .rating = 300,
406 .cpumask = cpu_all_mask,
407 };
408
409 static struct irqaction integrator_timer_irq = {
410 .name = "timer",
411 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
412 .handler = integrator_timer_interrupt,
413 .dev_id = &integrator_clockevent,
414 };
415
416 static void integrator_clockevent_init(u32 khz)
417 {
418 struct clock_event_device *evt = &integrator_clockevent;
419 unsigned int ctrl = 0;
420
421 if (khz * 1000 > 0x100000 * HZ) {
422 khz /= 256;
423 ctrl |= TIMER_CTRL_DIV256;
424 } else if (khz * 1000 > 0x10000 * HZ) {
425 khz /= 16;
426 ctrl |= TIMER_CTRL_DIV16;
427 }
428
429 timer_reload = khz * 1000 / HZ;
430 writel(ctrl, clkevt_base + TIMER_CTRL);
431
432 evt->irq = IRQ_TIMERINT1;
433 evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
434 evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
435 evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
436
437 setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
438 clockevents_register_device(evt);
439 }
440
441 /*
442 * Set up timer(s).
443 */
444 static void __init ap_init_timer(void)
445 {
446 u32 khz = TICKS_PER_uSEC * 1000;
447
448 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
449 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
450 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
451
452 integrator_clocksource_init(khz);
453 integrator_clockevent_init(khz);
454 }
455
456 static struct sys_timer ap_timer = {
457 .init = ap_init_timer,
458 };
459
460 MACHINE_START(INTEGRATOR, "ARM-Integrator")
461 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
462 .boot_params = 0x00000100,
463 .reserve = integrator_reserve,
464 .map_io = ap_map_io,
465 .init_early = integrator_init_early,
466 .init_irq = ap_init_irq,
467 .timer = &ap_timer,
468 .init_machine = ap_init,
469 MACHINE_END
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