arch/unicore32/include/mach/regs-pm.h

   1 /*
   2  * PKUNITY Power Manager (PM) Registers
   3  */
   4 /*
   5  * PM Control Reg PM_PMCR
   6  */
   7 #define PM_PMCR                 (PKUNITY_PM_BASE + 0x0000)
   8 /*
   9  * PM General Conf. Reg PM_PGCR
  10  */
  11 #define PM_PGCR                 (PKUNITY_PM_BASE + 0x0004)
  12 /*
  13  * PM PLL Conf. Reg PM_PPCR
  14  */
  15 #define PM_PPCR                 (PKUNITY_PM_BASE + 0x0008)
  16 /*
  17  * PM Wakeup Enable Reg PM_PWER
  18  */
  19 #define PM_PWER                 (PKUNITY_PM_BASE + 0x000C)
  20 /*
  21  * PM GPIO Sleep Status Reg PM_PGSR
  22  */
  23 #define PM_PGSR                 (PKUNITY_PM_BASE + 0x0010)
  24 /*
  25  * PM Clock Gate Reg PM_PCGR
  26  */
  27 #define PM_PCGR                 (PKUNITY_PM_BASE + 0x0014)
  28 /*
  29  * PM SYS PLL Conf. Reg PM_PLLSYSCFG
  30  */
  31 #define PM_PLLSYSCFG            (PKUNITY_PM_BASE + 0x0018)
  32 /*
  33  * PM DDR PLL Conf. Reg PM_PLLDDRCFG
  34  */
  35 #define PM_PLLDDRCFG            (PKUNITY_PM_BASE + 0x001C)
  36 /*
  37  * PM VGA PLL Conf. Reg PM_PLLVGACFG
  38  */
  39 #define PM_PLLVGACFG            (PKUNITY_PM_BASE + 0x0020)
  40 /*
  41  * PM Div Conf. Reg PM_DIVCFG
  42  */
  43 #define PM_DIVCFG               (PKUNITY_PM_BASE + 0x0024)
  44 /*
  45  * PM SYS PLL Status Reg PM_PLLSYSSTATUS
  46  */
  47 #define PM_PLLSYSSTATUS         (PKUNITY_PM_BASE + 0x0028)
  48 /*
  49  * PM DDR PLL Status Reg PM_PLLDDRSTATUS
  50  */
  51 #define PM_PLLDDRSTATUS         (PKUNITY_PM_BASE + 0x002C)
  52 /*
  53  * PM VGA PLL Status Reg PM_PLLVGASTATUS
  54  */
  55 #define PM_PLLVGASTATUS         (PKUNITY_PM_BASE + 0x0030)
  56 /*
  57  * PM Div Status Reg PM_DIVSTATUS
  58  */
  59 #define PM_DIVSTATUS            (PKUNITY_PM_BASE + 0x0034)
  60 /*
  61  * PM Software Reset Reg PM_SWRESET
  62  */
  63 #define PM_SWRESET              (PKUNITY_PM_BASE + 0x0038)
  64 /*
  65  * PM DDR2 PAD Start Reg PM_DDR2START
  66  */
  67 #define PM_DDR2START            (PKUNITY_PM_BASE + 0x003C)
  68 /*
  69  * PM DDR2 PAD Status Reg PM_DDR2CAL0
  70  */
  71 #define PM_DDR2CAL0             (PKUNITY_PM_BASE + 0x0040)
  72 /*
  73  * PM PLL DFC Done Reg PM_PLLDFCDONE
  74  */
  75 #define PM_PLLDFCDONE           (PKUNITY_PM_BASE + 0x0044)
  76
  77 #define PM_PMCR_SFB             FIELD(1, 1, 0)
  78 #define PM_PMCR_IFB             FIELD(1, 1, 1)
  79 #define PM_PMCR_CFBSYS          FIELD(1, 1, 2)
  80 #define PM_PMCR_CFBDDR          FIELD(1, 1, 3)
  81 #define PM_PMCR_CFBVGA          FIELD(1, 1, 4)
  82 #define PM_PMCR_CFBDIVBCLK      FIELD(1, 1, 5)
  83
  84 /*
  85  * GPIO 8~27 wake-up enable PM_PWER_GPIOHIGH
  86  */
  87 #define PM_PWER_GPIOHIGH        FIELD(1, 1, 8)
  88 /*
  89  * RTC alarm wake-up enable PM_PWER_RTC
  90  */
  91 #define PM_PWER_RTC             FIELD(1, 1, 31)
  92
  93 #define PM_PCGR_BCLK64DDR       FIELD(1, 1, 0)
  94 #define PM_PCGR_BCLK64VGA       FIELD(1, 1, 1)
  95 #define PM_PCGR_BCLKDDR         FIELD(1, 1, 2)
  96 #define PM_PCGR_BCLKPCI         FIELD(1, 1, 4)
  97 #define PM_PCGR_BCLKDMAC        FIELD(1, 1, 5)
  98 #define PM_PCGR_BCLKUMAL        FIELD(1, 1, 6)
  99 #define PM_PCGR_BCLKUSB         FIELD(1, 1, 7)
 100 #define PM_PCGR_BCLKMME         FIELD(1, 1, 10)
 101 #define PM_PCGR_BCLKNAND        FIELD(1, 1, 11)
 102 #define PM_PCGR_BCLKH264E       FIELD(1, 1, 12)
 103 #define PM_PCGR_BCLKVGA         FIELD(1, 1, 13)
 104 #define PM_PCGR_BCLKH264D       FIELD(1, 1, 14)
 105 #define PM_PCGR_VECLK           FIELD(1, 1, 15)
 106 #define PM_PCGR_HECLK           FIELD(1, 1, 16)
 107 #define PM_PCGR_HDCLK           FIELD(1, 1, 17)
 108 #define PM_PCGR_NANDCLK         FIELD(1, 1, 18)
 109 #define PM_PCGR_GECLK           FIELD(1, 1, 19)
 110 #define PM_PCGR_VGACLK          FIELD(1, 1, 20)
 111 #define PM_PCGR_PCICLK          FIELD(1, 1, 21)
 112 #define PM_PCGR_SATACLK         FIELD(1, 1, 25)
 113
 114 /*
 115  * [23:20]PM_DIVCFG_VGACLK(v)
 116  */
 117 #define PM_DIVCFG_VGACLK_MASK   FMASK(4, 20)
 118 #define PM_DIVCFG_VGACLK(v)     FIELD((v), 4, 20)
 119
 120 #define PM_SWRESET_USB          FIELD(1, 1, 6)
 121 #define PM_SWRESET_VGADIV       FIELD(1, 1, 26)
 122 #define PM_SWRESET_GEDIV        FIELD(1, 1, 27)
 123
 124 #define PM_PLLDFCDONE_SYSDFC    FIELD(1, 1, 0)
 125 #define PM_PLLDFCDONE_DDRDFC    FIELD(1, 1, 1)
 126 #define PM_PLLDFCDONE_VGADFC    FIELD(1, 1, 2)