nfsd4: typo logical vs bitwise negate for want_mask
[linux-btrfs-devel.git] / arch / arm / plat-s3c24xx / dma.c
blob539bd0e3defdc2ab9be00294a997a80fd060f6d6
1 /* linux/arch/arm/plat-s3c24xx/dma.c
3 * Copyright 2003-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 DMA core
8 * http://armlinux.simtec.co.uk/
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
16 #ifdef CONFIG_S3C2410_DMA_DEBUG
17 #define DEBUG
18 #endif
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/sched.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/slab.h>
27 #include <linux/errno.h>
28 #include <linux/io.h>
30 #include <asm/system.h>
31 #include <asm/irq.h>
32 #include <mach/hardware.h>
33 #include <mach/dma.h>
34 #include <mach/map.h>
36 #include <plat/dma-s3c24xx.h>
37 #include <plat/regs-dma.h>
39 /* io map for dma */
40 static void __iomem *dma_base;
41 static struct kmem_cache *dma_kmem;
43 static int dma_channels;
45 static struct s3c24xx_dma_selection dma_sel;
48 /* debugging functions */
50 #define BUF_MAGIC (0xcafebabe)
52 #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
54 #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
56 #if 1
57 #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
58 #else
59 static inline void
60 dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
62 pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
63 writel(val, dma_regaddr(chan, reg));
65 #endif
67 #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
69 /* captured register state for debug */
71 struct s3c2410_dma_regstate {
72 unsigned long dcsrc;
73 unsigned long disrc;
74 unsigned long dstat;
75 unsigned long dcon;
76 unsigned long dmsktrig;
79 #ifdef CONFIG_S3C2410_DMA_DEBUG
81 /* dmadbg_showregs
83 * simple debug routine to print the current state of the dma registers
86 static void
87 dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
89 regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
90 regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
91 regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
92 regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
93 regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
96 static void
97 dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
98 struct s3c2410_dma_regstate *regs)
100 printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
101 chan->number, fname, line,
102 regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
103 regs->dcon);
106 static void
107 dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
109 struct s3c2410_dma_regstate state;
111 dmadbg_capture(chan, &state);
113 printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
114 chan->number, fname, line, chan->load_state,
115 chan->curr, chan->next, chan->end);
117 dmadbg_dumpregs(fname, line, chan, &state);
120 static void
121 dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
123 struct s3c2410_dma_regstate state;
125 dmadbg_capture(chan, &state);
126 dmadbg_dumpregs(fname, line, chan, &state);
129 #define dbg_showregs(chan) dmadbg_showregs(__func__, __LINE__, (chan))
130 #define dbg_showchan(chan) dmadbg_showchan(__func__, __LINE__, (chan))
131 #else
132 #define dbg_showregs(chan) do { } while(0)
133 #define dbg_showchan(chan) do { } while(0)
134 #endif /* CONFIG_S3C2410_DMA_DEBUG */
136 /* s3c2410_dma_stats_timeout
138 * Update DMA stats from timeout info
141 static void
142 s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
144 if (stats == NULL)
145 return;
147 if (val > stats->timeout_longest)
148 stats->timeout_longest = val;
149 if (val < stats->timeout_shortest)
150 stats->timeout_shortest = val;
152 stats->timeout_avg += val;
155 /* s3c2410_dma_waitforload
157 * wait for the DMA engine to load a buffer, and update the state accordingly
160 static int
161 s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
163 int timeout = chan->load_timeout;
164 int took;
166 if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
167 printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
168 return 0;
171 if (chan->stats != NULL)
172 chan->stats->loads++;
174 while (--timeout > 0) {
175 if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
176 took = chan->load_timeout - timeout;
178 s3c2410_dma_stats_timeout(chan->stats, took);
180 switch (chan->load_state) {
181 case S3C2410_DMALOAD_1LOADED:
182 chan->load_state = S3C2410_DMALOAD_1RUNNING;
183 break;
185 default:
186 printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
189 return 1;
193 if (chan->stats != NULL) {
194 chan->stats->timeout_failed++;
197 return 0;
200 /* s3c2410_dma_loadbuffer
202 * load a buffer, and update the channel state
205 static inline int
206 s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
207 struct s3c2410_dma_buf *buf)
209 unsigned long reload;
211 if (buf == NULL) {
212 dmawarn("buffer is NULL\n");
213 return -EINVAL;
216 pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
217 buf, (unsigned long)buf->data, buf->size);
219 /* check the state of the channel before we do anything */
221 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
222 dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
225 if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
226 dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
229 /* it would seem sensible if we are the last buffer to not bother
230 * with the auto-reload bit, so that the DMA engine will not try
231 * and load another transfer after this one has finished...
233 if (chan->load_state == S3C2410_DMALOAD_NONE) {
234 pr_debug("load_state is none, checking for noreload (next=%p)\n",
235 buf->next);
236 reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
237 } else {
238 //pr_debug("load_state is %d => autoreload\n", chan->load_state);
239 reload = S3C2410_DCON_AUTORELOAD;
242 if ((buf->data & 0xf0000000) != 0x30000000) {
243 dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
246 writel(buf->data, chan->addr_reg);
248 dma_wrreg(chan, S3C2410_DMA_DCON,
249 chan->dcon | reload | (buf->size/chan->xfer_unit));
251 chan->next = buf->next;
253 /* update the state of the channel */
255 switch (chan->load_state) {
256 case S3C2410_DMALOAD_NONE:
257 chan->load_state = S3C2410_DMALOAD_1LOADED;
258 break;
260 case S3C2410_DMALOAD_1RUNNING:
261 chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
262 break;
264 default:
265 dmawarn("dmaload: unknown state %d in loadbuffer\n",
266 chan->load_state);
267 break;
270 return 0;
273 /* s3c2410_dma_call_op
275 * small routine to call the op routine with the given op if it has been
276 * registered
279 static void
280 s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
282 if (chan->op_fn != NULL) {
283 (chan->op_fn)(chan, op);
287 /* s3c2410_dma_buffdone
289 * small wrapper to check if callback routine needs to be called, and
290 * if so, call it
293 static inline void
294 s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
295 enum s3c2410_dma_buffresult result)
297 #if 0
298 pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
299 chan->callback_fn, buf, buf->id, buf->size, result);
300 #endif
302 if (chan->callback_fn != NULL) {
303 (chan->callback_fn)(chan, buf->id, buf->size, result);
307 /* s3c2410_dma_start
309 * start a dma channel going
312 static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
314 unsigned long tmp;
315 unsigned long flags;
317 pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
319 local_irq_save(flags);
321 if (chan->state == S3C2410_DMA_RUNNING) {
322 pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
323 local_irq_restore(flags);
324 return 0;
327 chan->state = S3C2410_DMA_RUNNING;
329 /* check wether there is anything to load, and if not, see
330 * if we can find anything to load
333 if (chan->load_state == S3C2410_DMALOAD_NONE) {
334 if (chan->next == NULL) {
335 printk(KERN_ERR "dma%d: channel has nothing loaded\n",
336 chan->number);
337 chan->state = S3C2410_DMA_IDLE;
338 local_irq_restore(flags);
339 return -EINVAL;
342 s3c2410_dma_loadbuffer(chan, chan->next);
345 dbg_showchan(chan);
347 /* enable the channel */
349 if (!chan->irq_enabled) {
350 enable_irq(chan->irq);
351 chan->irq_enabled = 1;
354 /* start the channel going */
356 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
357 tmp &= ~S3C2410_DMASKTRIG_STOP;
358 tmp |= S3C2410_DMASKTRIG_ON;
359 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
361 pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
363 #if 0
364 /* the dma buffer loads should take care of clearing the AUTO
365 * reloading feature */
366 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
367 tmp &= ~S3C2410_DCON_NORELOAD;
368 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
369 #endif
371 s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
373 dbg_showchan(chan);
375 /* if we've only loaded one buffer onto the channel, then chec
376 * to see if we have another, and if so, try and load it so when
377 * the first buffer is finished, the new one will be loaded onto
378 * the channel */
380 if (chan->next != NULL) {
381 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
383 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
384 pr_debug("%s: buff not yet loaded, no more todo\n",
385 __func__);
386 } else {
387 chan->load_state = S3C2410_DMALOAD_1RUNNING;
388 s3c2410_dma_loadbuffer(chan, chan->next);
391 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
392 s3c2410_dma_loadbuffer(chan, chan->next);
397 local_irq_restore(flags);
399 return 0;
402 /* s3c2410_dma_canload
404 * work out if we can queue another buffer into the DMA engine
407 static int
408 s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
410 if (chan->load_state == S3C2410_DMALOAD_NONE ||
411 chan->load_state == S3C2410_DMALOAD_1RUNNING)
412 return 1;
414 return 0;
417 /* s3c2410_dma_enqueue
419 * queue an given buffer for dma transfer.
421 * id the device driver's id information for this buffer
422 * data the physical address of the buffer data
423 * size the size of the buffer in bytes
425 * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
426 * is checked, and if set, the channel is started. If this flag isn't set,
427 * then an error will be returned.
429 * It is possible to queue more than one DMA buffer onto a channel at
430 * once, and the code will deal with the re-loading of the next buffer
431 * when necessary.
434 int s3c2410_dma_enqueue(unsigned int channel, void *id,
435 dma_addr_t data, int size)
437 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
438 struct s3c2410_dma_buf *buf;
439 unsigned long flags;
441 if (chan == NULL)
442 return -EINVAL;
444 pr_debug("%s: id=%p, data=%08x, size=%d\n",
445 __func__, id, (unsigned int)data, size);
447 buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
448 if (buf == NULL) {
449 pr_debug("%s: out of memory (%ld alloc)\n",
450 __func__, (long)sizeof(*buf));
451 return -ENOMEM;
454 //pr_debug("%s: new buffer %p\n", __func__, buf);
455 //dbg_showchan(chan);
457 buf->next = NULL;
458 buf->data = buf->ptr = data;
459 buf->size = size;
460 buf->id = id;
461 buf->magic = BUF_MAGIC;
463 local_irq_save(flags);
465 if (chan->curr == NULL) {
466 /* we've got nothing loaded... */
467 pr_debug("%s: buffer %p queued onto empty channel\n",
468 __func__, buf);
470 chan->curr = buf;
471 chan->end = buf;
472 chan->next = NULL;
473 } else {
474 pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
475 chan->number, __func__, buf);
477 if (chan->end == NULL)
478 pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
479 chan->number, __func__, chan);
481 chan->end->next = buf;
482 chan->end = buf;
485 /* if necessary, update the next buffer field */
486 if (chan->next == NULL)
487 chan->next = buf;
489 /* check to see if we can load a buffer */
490 if (chan->state == S3C2410_DMA_RUNNING) {
491 if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
492 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
493 printk(KERN_ERR "dma%d: loadbuffer:"
494 "timeout loading buffer\n",
495 chan->number);
496 dbg_showchan(chan);
497 local_irq_restore(flags);
498 return -EINVAL;
502 while (s3c2410_dma_canload(chan) && chan->next != NULL) {
503 s3c2410_dma_loadbuffer(chan, chan->next);
505 } else if (chan->state == S3C2410_DMA_IDLE) {
506 if (chan->flags & S3C2410_DMAF_AUTOSTART) {
507 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
508 S3C2410_DMAOP_START);
512 local_irq_restore(flags);
513 return 0;
516 EXPORT_SYMBOL(s3c2410_dma_enqueue);
518 static inline void
519 s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
521 int magicok = (buf->magic == BUF_MAGIC);
523 buf->magic = -1;
525 if (magicok) {
526 kmem_cache_free(dma_kmem, buf);
527 } else {
528 printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
532 /* s3c2410_dma_lastxfer
534 * called when the system is out of buffers, to ensure that the channel
535 * is prepared for shutdown.
538 static inline void
539 s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
541 #if 0
542 pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
543 chan->number, chan->load_state);
544 #endif
546 switch (chan->load_state) {
547 case S3C2410_DMALOAD_NONE:
548 break;
550 case S3C2410_DMALOAD_1LOADED:
551 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
552 /* flag error? */
553 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
554 chan->number, __func__);
555 return;
557 break;
559 case S3C2410_DMALOAD_1LOADED_1RUNNING:
560 /* I believe in this case we do not have anything to do
561 * until the next buffer comes along, and we turn off the
562 * reload */
563 return;
565 default:
566 pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
567 chan->number, chan->load_state);
568 return;
572 /* hopefully this'll shut the damned thing up after the transfer... */
573 dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
577 #define dmadbg2(x...)
579 static irqreturn_t
580 s3c2410_dma_irq(int irq, void *devpw)
582 struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
583 struct s3c2410_dma_buf *buf;
585 buf = chan->curr;
587 dbg_showchan(chan);
589 /* modify the channel state */
591 switch (chan->load_state) {
592 case S3C2410_DMALOAD_1RUNNING:
593 /* TODO - if we are running only one buffer, we probably
594 * want to reload here, and then worry about the buffer
595 * callback */
597 chan->load_state = S3C2410_DMALOAD_NONE;
598 break;
600 case S3C2410_DMALOAD_1LOADED:
601 /* iirc, we should go back to NONE loaded here, we
602 * had a buffer, and it was never verified as being
603 * loaded.
606 chan->load_state = S3C2410_DMALOAD_NONE;
607 break;
609 case S3C2410_DMALOAD_1LOADED_1RUNNING:
610 /* we'll worry about checking to see if another buffer is
611 * ready after we've called back the owner. This should
612 * ensure we do not wait around too long for the DMA
613 * engine to start the next transfer
616 chan->load_state = S3C2410_DMALOAD_1LOADED;
617 break;
619 case S3C2410_DMALOAD_NONE:
620 printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
621 chan->number);
622 break;
624 default:
625 printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
626 chan->number, chan->load_state);
627 break;
630 if (buf != NULL) {
631 /* update the chain to make sure that if we load any more
632 * buffers when we call the callback function, things should
633 * work properly */
635 chan->curr = buf->next;
636 buf->next = NULL;
638 if (buf->magic != BUF_MAGIC) {
639 printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
640 chan->number, __func__, buf);
641 return IRQ_HANDLED;
644 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
646 /* free resouces */
647 s3c2410_dma_freebuf(buf);
648 } else {
651 /* only reload if the channel is still running... our buffer done
652 * routine may have altered the state by requesting the dma channel
653 * to stop or shutdown... */
655 /* todo: check that when the channel is shut-down from inside this
656 * function, we cope with unsetting reload, etc */
658 if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
659 unsigned long flags;
661 switch (chan->load_state) {
662 case S3C2410_DMALOAD_1RUNNING:
663 /* don't need to do anything for this state */
664 break;
666 case S3C2410_DMALOAD_NONE:
667 /* can load buffer immediately */
668 break;
670 case S3C2410_DMALOAD_1LOADED:
671 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
672 /* flag error? */
673 printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
674 chan->number, __func__);
675 return IRQ_HANDLED;
678 break;
680 case S3C2410_DMALOAD_1LOADED_1RUNNING:
681 goto no_load;
683 default:
684 printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
685 chan->number, chan->load_state);
686 return IRQ_HANDLED;
689 local_irq_save(flags);
690 s3c2410_dma_loadbuffer(chan, chan->next);
691 local_irq_restore(flags);
692 } else {
693 s3c2410_dma_lastxfer(chan);
695 /* see if we can stop this channel.. */
696 if (chan->load_state == S3C2410_DMALOAD_NONE) {
697 pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
698 chan->number, jiffies);
699 s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
700 S3C2410_DMAOP_STOP);
704 no_load:
705 return IRQ_HANDLED;
708 static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
710 /* s3c2410_request_dma
712 * get control of an dma channel
715 int s3c2410_dma_request(enum dma_ch channel,
716 struct s3c2410_dma_client *client,
717 void *dev)
719 struct s3c2410_dma_chan *chan;
720 unsigned long flags;
721 int err;
723 pr_debug("dma%d: s3c2410_request_dma: client=%s, dev=%p\n",
724 channel, client->name, dev);
726 local_irq_save(flags);
728 chan = s3c2410_dma_map_channel(channel);
729 if (chan == NULL) {
730 local_irq_restore(flags);
731 return -EBUSY;
734 dbg_showchan(chan);
736 chan->client = client;
737 chan->in_use = 1;
739 if (!chan->irq_claimed) {
740 pr_debug("dma%d: %s : requesting irq %d\n",
741 channel, __func__, chan->irq);
743 chan->irq_claimed = 1;
744 local_irq_restore(flags);
746 err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
747 client->name, (void *)chan);
749 local_irq_save(flags);
751 if (err) {
752 chan->in_use = 0;
753 chan->irq_claimed = 0;
754 local_irq_restore(flags);
756 printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
757 client->name, chan->irq, chan->number);
758 return err;
761 chan->irq_enabled = 1;
764 local_irq_restore(flags);
766 /* need to setup */
768 pr_debug("%s: channel initialised, %p\n", __func__, chan);
770 return chan->number | DMACH_LOW_LEVEL;
773 EXPORT_SYMBOL(s3c2410_dma_request);
775 /* s3c2410_dma_free
777 * release the given channel back to the system, will stop and flush
778 * any outstanding transfers, and ensure the channel is ready for the
779 * next claimant.
781 * Note, although a warning is currently printed if the freeing client
782 * info is not the same as the registrant's client info, the free is still
783 * allowed to go through.
786 int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *client)
788 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
789 unsigned long flags;
791 if (chan == NULL)
792 return -EINVAL;
794 local_irq_save(flags);
796 if (chan->client != client) {
797 printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
798 channel, chan->client, client);
801 /* sort out stopping and freeing the channel */
803 if (chan->state != S3C2410_DMA_IDLE) {
804 pr_debug("%s: need to stop dma channel %p\n",
805 __func__, chan);
807 /* possibly flush the channel */
808 s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
811 chan->client = NULL;
812 chan->in_use = 0;
814 if (chan->irq_claimed)
815 free_irq(chan->irq, (void *)chan);
817 chan->irq_claimed = 0;
819 if (!(channel & DMACH_LOW_LEVEL))
820 s3c_dma_chan_map[channel] = NULL;
822 local_irq_restore(flags);
824 return 0;
827 EXPORT_SYMBOL(s3c2410_dma_free);
829 static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
831 unsigned long flags;
832 unsigned long tmp;
834 pr_debug("%s:\n", __func__);
836 dbg_showchan(chan);
838 local_irq_save(flags);
840 s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
842 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
843 tmp |= S3C2410_DMASKTRIG_STOP;
844 //tmp &= ~S3C2410_DMASKTRIG_ON;
845 dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
847 #if 0
848 /* should also clear interrupts, according to WinCE BSP */
849 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
850 tmp |= S3C2410_DCON_NORELOAD;
851 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
852 #endif
854 /* should stop do this, or should we wait for flush? */
855 chan->state = S3C2410_DMA_IDLE;
856 chan->load_state = S3C2410_DMALOAD_NONE;
858 local_irq_restore(flags);
860 return 0;
863 static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
865 unsigned long tmp;
866 unsigned int timeout = 0x10000;
868 while (timeout-- > 0) {
869 tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
871 if (!(tmp & S3C2410_DMASKTRIG_ON))
872 return;
875 pr_debug("dma%d: failed to stop?\n", chan->number);
879 /* s3c2410_dma_flush
881 * stop the channel, and remove all current and pending transfers
884 static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
886 struct s3c2410_dma_buf *buf, *next;
887 unsigned long flags;
889 pr_debug("%s: chan %p (%d)\n", __func__, chan, chan->number);
891 dbg_showchan(chan);
893 local_irq_save(flags);
895 if (chan->state != S3C2410_DMA_IDLE) {
896 pr_debug("%s: stopping channel...\n", __func__ );
897 s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
900 buf = chan->curr;
901 if (buf == NULL)
902 buf = chan->next;
904 chan->curr = chan->next = chan->end = NULL;
906 if (buf != NULL) {
907 for ( ; buf != NULL; buf = next) {
908 next = buf->next;
910 pr_debug("%s: free buffer %p, next %p\n",
911 __func__, buf, buf->next);
913 s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
914 s3c2410_dma_freebuf(buf);
918 dbg_showregs(chan);
920 s3c2410_dma_waitforstop(chan);
922 #if 0
923 /* should also clear interrupts, according to WinCE BSP */
925 unsigned long tmp;
927 tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
928 tmp |= S3C2410_DCON_NORELOAD;
929 dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
931 #endif
933 dbg_showregs(chan);
935 local_irq_restore(flags);
937 return 0;
940 static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
942 unsigned long flags;
944 local_irq_save(flags);
946 dbg_showchan(chan);
948 /* if we've only loaded one buffer onto the channel, then chec
949 * to see if we have another, and if so, try and load it so when
950 * the first buffer is finished, the new one will be loaded onto
951 * the channel */
953 if (chan->next != NULL) {
954 if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
956 if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
957 pr_debug("%s: buff not yet loaded, no more todo\n",
958 __func__);
959 } else {
960 chan->load_state = S3C2410_DMALOAD_1RUNNING;
961 s3c2410_dma_loadbuffer(chan, chan->next);
964 } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
965 s3c2410_dma_loadbuffer(chan, chan->next);
970 local_irq_restore(flags);
972 return 0;
977 s3c2410_dma_ctrl(enum dma_ch channel, enum s3c2410_chan_op op)
979 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
981 if (chan == NULL)
982 return -EINVAL;
984 switch (op) {
985 case S3C2410_DMAOP_START:
986 return s3c2410_dma_start(chan);
988 case S3C2410_DMAOP_STOP:
989 return s3c2410_dma_dostop(chan);
991 case S3C2410_DMAOP_PAUSE:
992 case S3C2410_DMAOP_RESUME:
993 return -ENOENT;
995 case S3C2410_DMAOP_FLUSH:
996 return s3c2410_dma_flush(chan);
998 case S3C2410_DMAOP_STARTED:
999 return s3c2410_dma_started(chan);
1001 case S3C2410_DMAOP_TIMEOUT:
1002 return 0;
1006 return -ENOENT; /* unknown, don't bother */
1009 EXPORT_SYMBOL(s3c2410_dma_ctrl);
1011 /* DMA configuration for each channel
1013 * DISRCC -> source of the DMA (AHB,APB)
1014 * DISRC -> source address of the DMA
1015 * DIDSTC -> destination of the DMA (AHB,APD)
1016 * DIDST -> destination address of the DMA
1019 /* s3c2410_dma_config
1021 * xfersize: size of unit in bytes (1,2,4)
1024 int s3c2410_dma_config(enum dma_ch channel,
1025 int xferunit)
1027 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1028 unsigned int dcon;
1030 pr_debug("%s: chan=%d, xfer_unit=%d\n", __func__, channel, xferunit);
1032 if (chan == NULL)
1033 return -EINVAL;
1035 dcon = chan->dcon & dma_sel.dcon_mask;
1036 pr_debug("%s: dcon is %08x\n", __func__, dcon);
1038 switch (chan->req_ch) {
1039 case DMACH_I2S_IN:
1040 case DMACH_I2S_OUT:
1041 case DMACH_PCM_IN:
1042 case DMACH_PCM_OUT:
1043 case DMACH_MIC_IN:
1044 default:
1045 dcon |= S3C2410_DCON_HANDSHAKE;
1046 dcon |= S3C2410_DCON_SYNC_PCLK;
1047 break;
1049 case DMACH_SDI:
1050 /* note, ensure if need HANDSHAKE or not */
1051 dcon |= S3C2410_DCON_SYNC_PCLK;
1052 break;
1054 case DMACH_XD0:
1055 case DMACH_XD1:
1056 dcon |= S3C2410_DCON_HANDSHAKE;
1057 dcon |= S3C2410_DCON_SYNC_HCLK;
1058 break;
1061 switch (xferunit) {
1062 case 1:
1063 dcon |= S3C2410_DCON_BYTE;
1064 break;
1066 case 2:
1067 dcon |= S3C2410_DCON_HALFWORD;
1068 break;
1070 case 4:
1071 dcon |= S3C2410_DCON_WORD;
1072 break;
1074 default:
1075 pr_debug("%s: bad transfer size %d\n", __func__, xferunit);
1076 return -EINVAL;
1079 dcon |= S3C2410_DCON_HWTRIG;
1080 dcon |= S3C2410_DCON_INTREQ;
1082 pr_debug("%s: dcon now %08x\n", __func__, dcon);
1084 chan->dcon = dcon;
1085 chan->xfer_unit = xferunit;
1087 return 0;
1090 EXPORT_SYMBOL(s3c2410_dma_config);
1093 /* s3c2410_dma_devconfig
1095 * configure the dma source/destination hardware type and address
1097 * source: S3C2410_DMASRC_HW: source is hardware
1098 * S3C2410_DMASRC_MEM: source is memory
1100 * devaddr: physical address of the source
1103 int s3c2410_dma_devconfig(enum dma_ch channel,
1104 enum s3c2410_dmasrc source,
1105 unsigned long devaddr)
1107 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1108 unsigned int hwcfg;
1110 if (chan == NULL)
1111 return -EINVAL;
1113 pr_debug("%s: source=%d, devaddr=%08lx\n",
1114 __func__, (int)source, devaddr);
1116 chan->source = source;
1117 chan->dev_addr = devaddr;
1119 switch (chan->req_ch) {
1120 case DMACH_XD0:
1121 case DMACH_XD1:
1122 hwcfg = 0; /* AHB */
1123 break;
1125 default:
1126 hwcfg = S3C2410_DISRCC_APB;
1129 /* always assume our peripheral desintation is a fixed
1130 * address in memory. */
1131 hwcfg |= S3C2410_DISRCC_INC;
1133 switch (source) {
1134 case S3C2410_DMASRC_HW:
1135 /* source is hardware */
1136 pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
1137 __func__, devaddr, hwcfg);
1138 dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
1139 dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
1140 dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
1142 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
1143 break;
1145 case S3C2410_DMASRC_MEM:
1146 /* source is memory */
1147 pr_debug("%s: mem source, devaddr=%08lx, hwcfg=%d\n",
1148 __func__, devaddr, hwcfg);
1149 dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
1150 dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
1151 dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
1153 chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
1154 break;
1156 default:
1157 printk(KERN_ERR "dma%d: invalid source type (%d)\n",
1158 channel, source);
1160 return -EINVAL;
1163 if (dma_sel.direction != NULL)
1164 (dma_sel.direction)(chan, chan->map, source);
1166 return 0;
1169 EXPORT_SYMBOL(s3c2410_dma_devconfig);
1171 /* s3c2410_dma_getposition
1173 * returns the current transfer points for the dma source and destination
1176 int s3c2410_dma_getposition(enum dma_ch channel, dma_addr_t *src, dma_addr_t *dst)
1178 struct s3c2410_dma_chan *chan = s3c_dma_lookup_channel(channel);
1180 if (chan == NULL)
1181 return -EINVAL;
1183 if (src != NULL)
1184 *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
1186 if (dst != NULL)
1187 *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
1189 return 0;
1192 EXPORT_SYMBOL(s3c2410_dma_getposition);
1194 /* system core operations */
1196 #ifdef CONFIG_PM
1198 static void s3c2410_dma_suspend_chan(struct s3c2410_dma_chan *cp)
1200 printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
1202 if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
1203 /* the dma channel is still working, which is probably
1204 * a bad thing to do over suspend/resume. We stop the
1205 * channel and assume that the client is either going to
1206 * retry after resume, or that it is broken.
1209 printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
1210 cp->number);
1212 s3c2410_dma_dostop(cp);
1216 static int s3c2410_dma_suspend(void)
1218 struct s3c2410_dma_chan *cp = s3c2410_chans;
1219 int channel;
1221 for (channel = 0; channel < dma_channels; cp++, channel++)
1222 s3c2410_dma_suspend_chan(cp);
1224 return 0;
1227 static void s3c2410_dma_resume_chan(struct s3c2410_dma_chan *cp)
1229 unsigned int no = cp->number | DMACH_LOW_LEVEL;
1231 /* restore channel's hardware configuration */
1233 if (!cp->in_use)
1234 return;
1236 printk(KERN_INFO "dma%d: restoring configuration\n", cp->number);
1238 s3c2410_dma_config(no, cp->xfer_unit);
1239 s3c2410_dma_devconfig(no, cp->source, cp->dev_addr);
1241 /* re-select the dma source for this channel */
1243 if (cp->map != NULL)
1244 dma_sel.select(cp, cp->map);
1247 static void s3c2410_dma_resume(void)
1249 struct s3c2410_dma_chan *cp = s3c2410_chans + dma_channels - 1;
1250 int channel;
1252 for (channel = dma_channels - 1; channel >= 0; cp++, channel--)
1253 s3c2410_dma_resume_chan(cp);
1256 #else
1257 #define s3c2410_dma_suspend NULL
1258 #define s3c2410_dma_resume NULL
1259 #endif /* CONFIG_PM */
1261 struct syscore_ops dma_syscore_ops = {
1262 .suspend = s3c2410_dma_suspend,
1263 .resume = s3c2410_dma_resume,
1266 /* kmem cache implementation */
1268 static void s3c2410_dma_cache_ctor(void *p)
1270 memset(p, 0, sizeof(struct s3c2410_dma_buf));
1273 /* initialisation code */
1275 static int __init s3c24xx_dma_syscore_init(void)
1277 register_syscore_ops(&dma_syscore_ops);
1279 return 0;
1282 late_initcall(s3c24xx_dma_syscore_init);
1284 int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
1285 unsigned int stride)
1287 struct s3c2410_dma_chan *cp;
1288 int channel;
1289 int ret;
1291 printk("S3C24XX DMA Driver, Copyright 2003-2006 Simtec Electronics\n");
1293 dma_channels = channels;
1295 dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
1296 if (dma_base == NULL) {
1297 printk(KERN_ERR "dma failed to remap register block\n");
1298 return -ENOMEM;
1301 dma_kmem = kmem_cache_create("dma_desc",
1302 sizeof(struct s3c2410_dma_buf), 0,
1303 SLAB_HWCACHE_ALIGN,
1304 s3c2410_dma_cache_ctor);
1306 if (dma_kmem == NULL) {
1307 printk(KERN_ERR "dma failed to make kmem cache\n");
1308 ret = -ENOMEM;
1309 goto err;
1312 for (channel = 0; channel < channels; channel++) {
1313 cp = &s3c2410_chans[channel];
1315 memset(cp, 0, sizeof(struct s3c2410_dma_chan));
1317 /* dma channel irqs are in order.. */
1318 cp->number = channel;
1319 cp->irq = channel + irq;
1320 cp->regs = dma_base + (channel * stride);
1322 /* point current stats somewhere */
1323 cp->stats = &cp->stats_store;
1324 cp->stats_store.timeout_shortest = LONG_MAX;
1326 /* basic channel configuration */
1328 cp->load_timeout = 1<<18;
1330 printk("DMA channel %d at %p, irq %d\n",
1331 cp->number, cp->regs, cp->irq);
1334 return 0;
1336 err:
1337 kmem_cache_destroy(dma_kmem);
1338 iounmap(dma_base);
1339 dma_base = NULL;
1340 return ret;
1343 int __init s3c2410_dma_init(void)
1345 return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
1348 static inline int is_channel_valid(unsigned int channel)
1350 return (channel & DMA_CH_VALID);
1353 static struct s3c24xx_dma_order *dma_order;
1356 /* s3c2410_dma_map_channel()
1358 * turn the virtual channel number into a real, and un-used hardware
1359 * channel.
1361 * first, try the dma ordering given to us by either the relevant
1362 * dma code, or the board. Then just find the first usable free
1363 * channel
1366 static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
1368 struct s3c24xx_dma_order_ch *ord = NULL;
1369 struct s3c24xx_dma_map *ch_map;
1370 struct s3c2410_dma_chan *dmach;
1371 int ch;
1373 if (dma_sel.map == NULL || channel > dma_sel.map_size)
1374 return NULL;
1376 ch_map = dma_sel.map + channel;
1378 /* first, try the board mapping */
1380 if (dma_order) {
1381 ord = &dma_order->channels[channel];
1383 for (ch = 0; ch < dma_channels; ch++) {
1384 int tmp;
1385 if (!is_channel_valid(ord->list[ch]))
1386 continue;
1388 tmp = ord->list[ch] & ~DMA_CH_VALID;
1389 if (s3c2410_chans[tmp].in_use == 0) {
1390 ch = tmp;
1391 goto found;
1395 if (ord->flags & DMA_CH_NEVER)
1396 return NULL;
1399 /* second, search the channel map for first free */
1401 for (ch = 0; ch < dma_channels; ch++) {
1402 if (!is_channel_valid(ch_map->channels[ch]))
1403 continue;
1405 if (s3c2410_chans[ch].in_use == 0) {
1406 printk("mapped channel %d to %d\n", channel, ch);
1407 break;
1411 if (ch >= dma_channels)
1412 return NULL;
1414 /* update our channel mapping */
1416 found:
1417 dmach = &s3c2410_chans[ch];
1418 dmach->map = ch_map;
1419 dmach->req_ch = channel;
1420 s3c_dma_chan_map[channel] = dmach;
1422 /* select the channel */
1424 (dma_sel.select)(dmach, ch_map);
1426 return dmach;
1429 static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
1431 return 0;
1434 int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
1436 struct s3c24xx_dma_map *nmap;
1437 size_t map_sz = sizeof(*nmap) * sel->map_size;
1438 int ptr;
1440 nmap = kmalloc(map_sz, GFP_KERNEL);
1441 if (nmap == NULL)
1442 return -ENOMEM;
1444 memcpy(nmap, sel->map, map_sz);
1445 memcpy(&dma_sel, sel, sizeof(*sel));
1447 dma_sel.map = nmap;
1449 for (ptr = 0; ptr < sel->map_size; ptr++)
1450 s3c24xx_dma_check_entry(nmap+ptr, ptr);
1452 return 0;
1455 int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
1457 struct s3c24xx_dma_order *nord = dma_order;
1459 if (nord == NULL)
1460 nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
1462 if (nord == NULL) {
1463 printk(KERN_ERR "no memory to store dma channel order\n");
1464 return -ENOMEM;
1467 dma_order = nord;
1468 memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
1469 return 0;