| blob | 35376a1c3f1bc109fb8bea9deb54cec9b7acf0c8 |
1 /*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2010 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7 #ifndef __QLA_NX_H
8 #define __QLA_NX_H
10 /*
11 * Following are the states of the Phantom. Phantom will set them and
12 * Host will read to check if the fields are correct.
13 */
14 #define PHAN_INITIALIZE_FAILED 0xffff
15 #define PHAN_INITIALIZE_COMPLETE 0xff01
17 /* Host writes the following to notify that it has done the init-handshake */
18 #define PHAN_INITIALIZE_ACK 0xf00f
19 #define PHAN_PEG_RCV_INITIALIZED 0xff01
21 /*CRB_RELATED*/
22 #define QLA82XX_CRB_BASE QLA82XX_CAM_RAM(0x200)
23 #define QLA82XX_REG(X) (QLA82XX_CRB_BASE+(X))
25 #define CRB_CMDPEG_STATE QLA82XX_REG(0x50)
26 #define CRB_RCVPEG_STATE QLA82XX_REG(0x13c)
27 #define CRB_DMA_SHIFT QLA82XX_REG(0xcc)
29 #define QLA82XX_HW_H0_CH_HUB_ADR 0x05
30 #define QLA82XX_HW_H1_CH_HUB_ADR 0x0E
31 #define QLA82XX_HW_H2_CH_HUB_ADR 0x03
32 #define QLA82XX_HW_H3_CH_HUB_ADR 0x01
33 #define QLA82XX_HW_H4_CH_HUB_ADR 0x06
34 #define QLA82XX_HW_H5_CH_HUB_ADR 0x07
35 #define QLA82XX_HW_H6_CH_HUB_ADR 0x08
37 /* Hub 0 */
38 #define QLA82XX_HW_MN_CRB_AGT_ADR 0x15
39 #define QLA82XX_HW_MS_CRB_AGT_ADR 0x25
41 /* Hub 1 */
42 #define QLA82XX_HW_PS_CRB_AGT_ADR 0x73
43 #define QLA82XX_HW_QMS_CRB_AGT_ADR 0x00
44 #define QLA82XX_HW_RPMX3_CRB_AGT_ADR 0x0b
45 #define QLA82XX_HW_SQGS0_CRB_AGT_ADR 0x01
46 #define QLA82XX_HW_SQGS1_CRB_AGT_ADR 0x02
47 #define QLA82XX_HW_SQGS2_CRB_AGT_ADR 0x03
48 #define QLA82XX_HW_SQGS3_CRB_AGT_ADR 0x04
49 #define QLA82XX_HW_C2C0_CRB_AGT_ADR 0x58
50 #define QLA82XX_HW_C2C1_CRB_AGT_ADR 0x59
51 #define QLA82XX_HW_C2C2_CRB_AGT_ADR 0x5a
52 #define QLA82XX_HW_RPMX2_CRB_AGT_ADR 0x0a
53 #define QLA82XX_HW_RPMX4_CRB_AGT_ADR 0x0c
54 #define QLA82XX_HW_RPMX7_CRB_AGT_ADR 0x0f
55 #define QLA82XX_HW_RPMX9_CRB_AGT_ADR 0x12
56 #define QLA82XX_HW_SMB_CRB_AGT_ADR 0x18
58 /* Hub 2 */
59 #define QLA82XX_HW_NIU_CRB_AGT_ADR 0x31
60 #define QLA82XX_HW_I2C0_CRB_AGT_ADR 0x19
61 #define QLA82XX_HW_I2C1_CRB_AGT_ADR 0x29
63 #define QLA82XX_HW_SN_CRB_AGT_ADR 0x10
64 #define QLA82XX_HW_I2Q_CRB_AGT_ADR 0x20
65 #define QLA82XX_HW_LPC_CRB_AGT_ADR 0x22
66 #define QLA82XX_HW_ROMUSB_CRB_AGT_ADR 0x21
67 #define QLA82XX_HW_QM_CRB_AGT_ADR 0x66
68 #define QLA82XX_HW_SQG0_CRB_AGT_ADR 0x60
69 #define QLA82XX_HW_SQG1_CRB_AGT_ADR 0x61
70 #define QLA82XX_HW_SQG2_CRB_AGT_ADR 0x62
71 #define QLA82XX_HW_SQG3_CRB_AGT_ADR 0x63
72 #define QLA82XX_HW_RPMX1_CRB_AGT_ADR 0x09
73 #define QLA82XX_HW_RPMX5_CRB_AGT_ADR 0x0d
74 #define QLA82XX_HW_RPMX6_CRB_AGT_ADR 0x0e
75 #define QLA82XX_HW_RPMX8_CRB_AGT_ADR 0x11
77 /* Hub 3 */
78 #define QLA82XX_HW_PH_CRB_AGT_ADR 0x1A
79 #define QLA82XX_HW_SRE_CRB_AGT_ADR 0x50
80 #define QLA82XX_HW_EG_CRB_AGT_ADR 0x51
81 #define QLA82XX_HW_RPMX0_CRB_AGT_ADR 0x08
83 /* Hub 4 */
84 #define QLA82XX_HW_PEGN0_CRB_AGT_ADR 0x40
85 #define QLA82XX_HW_PEGN1_CRB_AGT_ADR 0x41
86 #define QLA82XX_HW_PEGN2_CRB_AGT_ADR 0x42
87 #define QLA82XX_HW_PEGN3_CRB_AGT_ADR 0x43
88 #define QLA82XX_HW_PEGNI_CRB_AGT_ADR 0x44
89 #define QLA82XX_HW_PEGND_CRB_AGT_ADR 0x45
90 #define QLA82XX_HW_PEGNC_CRB_AGT_ADR 0x46
91 #define QLA82XX_HW_PEGR0_CRB_AGT_ADR 0x47
92 #define QLA82XX_HW_PEGR1_CRB_AGT_ADR 0x48
93 #define QLA82XX_HW_PEGR2_CRB_AGT_ADR 0x49
94 #define QLA82XX_HW_PEGR3_CRB_AGT_ADR 0x4a
95 #define QLA82XX_HW_PEGN4_CRB_AGT_ADR 0x4b
97 /* Hub 5 */
98 #define QLA82XX_HW_PEGS0_CRB_AGT_ADR 0x40
99 #define QLA82XX_HW_PEGS1_CRB_AGT_ADR 0x41
100 #define QLA82XX_HW_PEGS2_CRB_AGT_ADR 0x42
101 #define QLA82XX_HW_PEGS3_CRB_AGT_ADR 0x43
103 #define QLA82XX_HW_PEGSI_CRB_AGT_ADR 0x44
104 #define QLA82XX_HW_PEGSD_CRB_AGT_ADR 0x45
105 #define QLA82XX_HW_PEGSC_CRB_AGT_ADR 0x46
107 /* Hub 6 */
108 #define QLA82XX_HW_CAS0_CRB_AGT_ADR 0x46
109 #define QLA82XX_HW_CAS1_CRB_AGT_ADR 0x47
110 #define QLA82XX_HW_CAS2_CRB_AGT_ADR 0x48
111 #define QLA82XX_HW_CAS3_CRB_AGT_ADR 0x49
112 #define QLA82XX_HW_NCM_CRB_AGT_ADR 0x16
113 #define QLA82XX_HW_TMR_CRB_AGT_ADR 0x17
114 #define QLA82XX_HW_XDMA_CRB_AGT_ADR 0x05
115 #define QLA82XX_HW_OCM0_CRB_AGT_ADR 0x06
116 #define QLA82XX_HW_OCM1_CRB_AGT_ADR 0x07
118 /* This field defines PCI/X adr [25:20] of agents on the CRB */
119 /* */
120 #define QLA82XX_HW_PX_MAP_CRB_PH 0
121 #define QLA82XX_HW_PX_MAP_CRB_PS 1
122 #define QLA82XX_HW_PX_MAP_CRB_MN 2
123 #define QLA82XX_HW_PX_MAP_CRB_MS 3
124 #define QLA82XX_HW_PX_MAP_CRB_SRE 5
125 #define QLA82XX_HW_PX_MAP_CRB_NIU 6
126 #define QLA82XX_HW_PX_MAP_CRB_QMN 7
127 #define QLA82XX_HW_PX_MAP_CRB_SQN0 8
128 #define QLA82XX_HW_PX_MAP_CRB_SQN1 9
129 #define QLA82XX_HW_PX_MAP_CRB_SQN2 10
130 #define QLA82XX_HW_PX_MAP_CRB_SQN3 11
131 #define QLA82XX_HW_PX_MAP_CRB_QMS 12
132 #define QLA82XX_HW_PX_MAP_CRB_SQS0 13
133 #define QLA82XX_HW_PX_MAP_CRB_SQS1 14
134 #define QLA82XX_HW_PX_MAP_CRB_SQS2 15
135 #define QLA82XX_HW_PX_MAP_CRB_SQS3 16
136 #define QLA82XX_HW_PX_MAP_CRB_PGN0 17
137 #define QLA82XX_HW_PX_MAP_CRB_PGN1 18
138 #define QLA82XX_HW_PX_MAP_CRB_PGN2 19
139 #define QLA82XX_HW_PX_MAP_CRB_PGN3 20
140 #define QLA82XX_HW_PX_MAP_CRB_PGN4 QLA82XX_HW_PX_MAP_CRB_SQS2
141 #define QLA82XX_HW_PX_MAP_CRB_PGND 21
142 #define QLA82XX_HW_PX_MAP_CRB_PGNI 22
143 #define QLA82XX_HW_PX_MAP_CRB_PGS0 23
144 #define QLA82XX_HW_PX_MAP_CRB_PGS1 24
145 #define QLA82XX_HW_PX_MAP_CRB_PGS2 25
146 #define QLA82XX_HW_PX_MAP_CRB_PGS3 26
147 #define QLA82XX_HW_PX_MAP_CRB_PGSD 27
148 #define QLA82XX_HW_PX_MAP_CRB_PGSI 28
149 #define QLA82XX_HW_PX_MAP_CRB_SN 29
150 #define QLA82XX_HW_PX_MAP_CRB_EG 31
151 #define QLA82XX_HW_PX_MAP_CRB_PH2 32
152 #define QLA82XX_HW_PX_MAP_CRB_PS2 33
153 #define QLA82XX_HW_PX_MAP_CRB_CAM 34
154 #define QLA82XX_HW_PX_MAP_CRB_CAS0 35
155 #define QLA82XX_HW_PX_MAP_CRB_CAS1 36
156 #define QLA82XX_HW_PX_MAP_CRB_CAS2 37
157 #define QLA82XX_HW_PX_MAP_CRB_C2C0 38
158 #define QLA82XX_HW_PX_MAP_CRB_C2C1 39
159 #define QLA82XX_HW_PX_MAP_CRB_TIMR 40
160 #define QLA82XX_HW_PX_MAP_CRB_RPMX1 42
161 #define QLA82XX_HW_PX_MAP_CRB_RPMX2 43
162 #define QLA82XX_HW_PX_MAP_CRB_RPMX3 44
163 #define QLA82XX_HW_PX_MAP_CRB_RPMX4 45
164 #define QLA82XX_HW_PX_MAP_CRB_RPMX5 46
165 #define QLA82XX_HW_PX_MAP_CRB_RPMX6 47
166 #define QLA82XX_HW_PX_MAP_CRB_RPMX7 48
167 #define QLA82XX_HW_PX_MAP_CRB_XDMA 49
168 #define QLA82XX_HW_PX_MAP_CRB_I2Q 50
169 #define QLA82XX_HW_PX_MAP_CRB_ROMUSB 51
170 #define QLA82XX_HW_PX_MAP_CRB_CAS3 52
171 #define QLA82XX_HW_PX_MAP_CRB_RPMX0 53
172 #define QLA82XX_HW_PX_MAP_CRB_RPMX8 54
173 #define QLA82XX_HW_PX_MAP_CRB_RPMX9 55
174 #define QLA82XX_HW_PX_MAP_CRB_OCM0 56
175 #define QLA82XX_HW_PX_MAP_CRB_OCM1 57
176 #define QLA82XX_HW_PX_MAP_CRB_SMB 58
177 #define QLA82XX_HW_PX_MAP_CRB_I2C0 59
178 #define QLA82XX_HW_PX_MAP_CRB_I2C1 60
179 #define QLA82XX_HW_PX_MAP_CRB_LPC 61
180 #define QLA82XX_HW_PX_MAP_CRB_PGNC 62
181 #define QLA82XX_HW_PX_MAP_CRB_PGR0 63
182 #define QLA82XX_HW_PX_MAP_CRB_PGR1 4
183 #define QLA82XX_HW_PX_MAP_CRB_PGR2 30
184 #define QLA82XX_HW_PX_MAP_CRB_PGR3 41
186 /* This field defines CRB adr [31:20] of the agents */
187 /* */
189 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MN ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
190 QLA82XX_HW_MN_CRB_AGT_ADR)
191 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PH ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
192 QLA82XX_HW_PH_CRB_AGT_ADR)
193 #define QLA82XX_HW_CRB_HUB_AGT_ADR_MS ((QLA82XX_HW_H0_CH_HUB_ADR << 7) | \
194 QLA82XX_HW_MS_CRB_AGT_ADR)
195 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
196 QLA82XX_HW_PS_CRB_AGT_ADR)
197 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
198 QLA82XX_HW_SS_CRB_AGT_ADR)
199 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
200 QLA82XX_HW_RPMX3_CRB_AGT_ADR)
201 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMS ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
202 QLA82XX_HW_QMS_CRB_AGT_ADR)
203 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
204 QLA82XX_HW_SQGS0_CRB_AGT_ADR)
205 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
206 QLA82XX_HW_SQGS1_CRB_AGT_ADR)
207 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
208 QLA82XX_HW_SQGS2_CRB_AGT_ADR)
209 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQS3 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
210 QLA82XX_HW_SQGS3_CRB_AGT_ADR)
211 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C0 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
212 QLA82XX_HW_C2C0_CRB_AGT_ADR)
213 #define QLA82XX_HW_CRB_HUB_AGT_ADR_C2C1 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
214 QLA82XX_HW_C2C1_CRB_AGT_ADR)
215 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
216 QLA82XX_HW_RPMX2_CRB_AGT_ADR)
217 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
218 QLA82XX_HW_RPMX4_CRB_AGT_ADR)
219 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
220 QLA82XX_HW_RPMX7_CRB_AGT_ADR)
221 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9 ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
222 QLA82XX_HW_RPMX9_CRB_AGT_ADR)
223 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SMB ((QLA82XX_HW_H1_CH_HUB_ADR << 7) | \
224 QLA82XX_HW_SMB_CRB_AGT_ADR)
226 #define QLA82XX_HW_CRB_HUB_AGT_ADR_NIU ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
227 QLA82XX_HW_NIU_CRB_AGT_ADR)
228 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
229 QLA82XX_HW_I2C0_CRB_AGT_ADR)
230 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1 ((QLA82XX_HW_H2_CH_HUB_ADR << 7) | \
231 QLA82XX_HW_I2C1_CRB_AGT_ADR)
233 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SRE ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
234 QLA82XX_HW_SRE_CRB_AGT_ADR)
235 #define QLA82XX_HW_CRB_HUB_AGT_ADR_EG ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
236 QLA82XX_HW_EG_CRB_AGT_ADR)
237 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
238 QLA82XX_HW_RPMX0_CRB_AGT_ADR)
239 #define QLA82XX_HW_CRB_HUB_AGT_ADR_QMN ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
240 QLA82XX_HW_QM_CRB_AGT_ADR)
241 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
242 QLA82XX_HW_SQG0_CRB_AGT_ADR)
243 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
244 QLA82XX_HW_SQG1_CRB_AGT_ADR)
245 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
246 QLA82XX_HW_SQG2_CRB_AGT_ADR)
247 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
248 QLA82XX_HW_SQG3_CRB_AGT_ADR)
249 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
250 QLA82XX_HW_RPMX1_CRB_AGT_ADR)
251 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
252 QLA82XX_HW_RPMX5_CRB_AGT_ADR)
253 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
254 QLA82XX_HW_RPMX6_CRB_AGT_ADR)
255 #define QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
256 QLA82XX_HW_RPMX8_CRB_AGT_ADR)
257 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS0 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
258 QLA82XX_HW_CAS0_CRB_AGT_ADR)
259 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS1 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
260 QLA82XX_HW_CAS1_CRB_AGT_ADR)
261 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS2 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
262 QLA82XX_HW_CAS2_CRB_AGT_ADR)
263 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAS3 ((QLA82XX_HW_H3_CH_HUB_ADR << 7) | \
264 QLA82XX_HW_CAS3_CRB_AGT_ADR)
266 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
267 QLA82XX_HW_PEGNI_CRB_AGT_ADR)
268 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGND ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
269 QLA82XX_HW_PEGND_CRB_AGT_ADR)
270 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
271 QLA82XX_HW_PEGN0_CRB_AGT_ADR)
272 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
273 QLA82XX_HW_PEGN1_CRB_AGT_ADR)
274 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
275 QLA82XX_HW_PEGN2_CRB_AGT_ADR)
276 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
277 QLA82XX_HW_PEGN3_CRB_AGT_ADR)
278 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
279 QLA82XX_HW_PEGN4_CRB_AGT_ADR)
281 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
282 QLA82XX_HW_PEGNC_CRB_AGT_ADR)
283 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR0 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
284 QLA82XX_HW_PEGR0_CRB_AGT_ADR)
285 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR1 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
286 QLA82XX_HW_PEGR1_CRB_AGT_ADR)
287 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR2 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
288 QLA82XX_HW_PEGR2_CRB_AGT_ADR)
289 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGR3 ((QLA82XX_HW_H4_CH_HUB_ADR << 7) | \
290 QLA82XX_HW_PEGR3_CRB_AGT_ADR)
292 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
293 QLA82XX_HW_PEGSI_CRB_AGT_ADR)
294 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSD ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
295 QLA82XX_HW_PEGSD_CRB_AGT_ADR)
296 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
297 QLA82XX_HW_PEGS0_CRB_AGT_ADR)
298 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
299 QLA82XX_HW_PEGS1_CRB_AGT_ADR)
300 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
301 QLA82XX_HW_PEGS2_CRB_AGT_ADR)
302 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3 ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
303 QLA82XX_HW_PEGS3_CRB_AGT_ADR)
304 #define QLA82XX_HW_CRB_HUB_AGT_ADR_PGSC ((QLA82XX_HW_H5_CH_HUB_ADR << 7) | \
305 QLA82XX_HW_PEGSC_CRB_AGT_ADR)
307 #define QLA82XX_HW_CRB_HUB_AGT_ADR_CAM ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
308 QLA82XX_HW_NCM_CRB_AGT_ADR)
309 #define QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
310 QLA82XX_HW_TMR_CRB_AGT_ADR)
311 #define QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
312 QLA82XX_HW_XDMA_CRB_AGT_ADR)
313 #define QLA82XX_HW_CRB_HUB_AGT_ADR_SN ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
314 QLA82XX_HW_SN_CRB_AGT_ADR)
315 #define QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
316 QLA82XX_HW_I2Q_CRB_AGT_ADR)
317 #define QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
318 QLA82XX_HW_ROMUSB_CRB_AGT_ADR)
319 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
320 QLA82XX_HW_OCM0_CRB_AGT_ADR)
321 #define QLA82XX_HW_CRB_HUB_AGT_ADR_OCM1 ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
322 QLA82XX_HW_OCM1_CRB_AGT_ADR)
323 #define QLA82XX_HW_CRB_HUB_AGT_ADR_LPC ((QLA82XX_HW_H6_CH_HUB_ADR << 7) | \
324 QLA82XX_HW_LPC_CRB_AGT_ADR)
326 #define ROMUSB_GLB (QLA82XX_CRB_ROMUSB + 0x00000)
327 #define QLA82XX_ROMUSB_GLB_PEGTUNE_DONE (ROMUSB_GLB + 0x005c)
328 #define QLA82XX_ROMUSB_GLB_STATUS (ROMUSB_GLB + 0x0004)
329 #define QLA82XX_ROMUSB_GLB_SW_RESET (ROMUSB_GLB + 0x0008)
330 #define QLA82XX_ROMUSB_ROM_ADDRESS (ROMUSB_ROM + 0x0008)
331 #define QLA82XX_ROMUSB_ROM_WDATA (ROMUSB_ROM + 0x000c)
332 #define QLA82XX_ROMUSB_ROM_ABYTE_CNT (ROMUSB_ROM + 0x0010)
333 #define QLA82XX_ROMUSB_ROM_DUMMY_BYTE_CNT (ROMUSB_ROM + 0x0014)
334 #define QLA82XX_ROMUSB_ROM_RDATA (ROMUSB_ROM + 0x0018)
336 #define ROMUSB_ROM (QLA82XX_CRB_ROMUSB + 0x10000)
337 #define QLA82XX_ROMUSB_ROM_INSTR_OPCODE (ROMUSB_ROM + 0x0004)
338 #define QLA82XX_ROMUSB_GLB_CAS_RST (ROMUSB_GLB + 0x0038)
340 /* Lock IDs for ROM lock */
341 #define ROM_LOCK_DRIVER 0x0d417340
344 #define QLA82XX_PCI_CRB_WINDOW(A) (QLA82XX_PCI_CRBSPACE + \
345 (A)*QLA82XX_PCI_CRB_WINDOWSIZE)
347 #define QLA82XX_CRB_C2C_0 \
348 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C0)
349 #define QLA82XX_CRB_C2C_1 \
350 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C1)
351 #define QLA82XX_CRB_C2C_2 \
352 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_C2C2)
353 #define QLA82XX_CRB_CAM \
354 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAM)
355 #define QLA82XX_CRB_CASPER \
356 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS)
357 #define QLA82XX_CRB_CASPER_0 \
358 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS0)
359 #define QLA82XX_CRB_CASPER_1 \
360 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS1)
361 #define QLA82XX_CRB_CASPER_2 \
362 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_CAS2)
363 #define QLA82XX_CRB_DDR_MD \
364 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MS)
365 #define QLA82XX_CRB_DDR_NET \
366 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_MN)
367 #define QLA82XX_CRB_EPG \
368 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_EG)
369 #define QLA82XX_CRB_I2Q \
370 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2Q)
371 #define QLA82XX_CRB_NIU \
372 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_NIU)
373 /* HACK upon HACK upon HACK (for PCIE builds) */
374 #define QLA82XX_CRB_PCIX_HOST \
375 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH)
376 #define QLA82XX_CRB_PCIX_HOST2 \
377 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PH2)
378 #define QLA82XX_CRB_PCIX_MD \
379 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS)
380 #define QLA82XX_CRB_PCIE QLA82XX_CRB_PCIX_MD
381 /* window 1 pcie slot */
382 #define QLA82XX_CRB_PCIE2 \
383 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PS2)
385 #define QLA82XX_CRB_PEG_MD_0 \
386 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS0)
387 #define QLA82XX_CRB_PEG_MD_1 \
388 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS1)
389 #define QLA82XX_CRB_PEG_MD_2 \
390 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS2)
391 #define QLA82XX_CRB_PEG_MD_3 \
392 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
393 #define QLA82XX_CRB_PEG_MD_3 \
394 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGS3)
395 #define QLA82XX_CRB_PEG_MD_D \
396 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSD)
397 #define QLA82XX_CRB_PEG_MD_I \
398 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGSI)
399 #define QLA82XX_CRB_PEG_NET_0 \
400 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN0)
401 #define QLA82XX_CRB_PEG_NET_1 \
402 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN1)
403 #define QLA82XX_CRB_PEG_NET_2 \
404 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN2)
405 #define QLA82XX_CRB_PEG_NET_3 \
406 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN3)
407 #define QLA82XX_CRB_PEG_NET_4 \
408 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGN4)
409 #define QLA82XX_CRB_PEG_NET_D \
410 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGND)
411 #define QLA82XX_CRB_PEG_NET_I \
412 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_PGNI)
413 #define QLA82XX_CRB_PQM_MD \
414 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMS)
415 #define QLA82XX_CRB_PQM_NET \
416 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_QMN)
417 #define QLA82XX_CRB_QDR_MD \
418 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SS)
419 #define QLA82XX_CRB_QDR_NET \
420 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SN)
421 #define QLA82XX_CRB_ROMUSB \
422 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_ROMUSB)
423 #define QLA82XX_CRB_RPMX_0 \
424 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX0)
425 #define QLA82XX_CRB_RPMX_1 \
426 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX1)
427 #define QLA82XX_CRB_RPMX_2 \
428 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX2)
429 #define QLA82XX_CRB_RPMX_3 \
430 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX3)
431 #define QLA82XX_CRB_RPMX_4 \
432 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX4)
433 #define QLA82XX_CRB_RPMX_5 \
434 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX5)
435 #define QLA82XX_CRB_RPMX_6 \
436 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX6)
437 #define QLA82XX_CRB_RPMX_7 \
438 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_RPMX7)
439 #define QLA82XX_CRB_SQM_MD_0 \
440 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS0)
441 #define QLA82XX_CRB_SQM_MD_1 \
442 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS1)
443 #define QLA82XX_CRB_SQM_MD_2 \
444 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS2)
445 #define QLA82XX_CRB_SQM_MD_3 \
446 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQS3)
447 #define QLA82XX_CRB_SQM_NET_0 \
448 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN0)
449 #define QLA82XX_CRB_SQM_NET_1 \
450 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN1)
451 #define QLA82XX_CRB_SQM_NET_2 \
452 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN2)
453 #define QLA82XX_CRB_SQM_NET_3 \
454 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SQN3)
455 #define QLA82XX_CRB_SRE \
456 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SRE)
457 #define QLA82XX_CRB_TIMER \
458 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_TIMR)
459 #define QLA82XX_CRB_XDMA \
460 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_XDMA)
461 #define QLA82XX_CRB_I2C0 \
462 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C0)
463 #define QLA82XX_CRB_I2C1 \
464 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_I2C1)
465 #define QLA82XX_CRB_OCM0 \
466 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_OCM0)
467 #define QLA82XX_CRB_SMB \
468 QLA82XX_PCI_CRB_WINDOW(QLA82XX_HW_PX_MAP_CRB_SMB)
470 #define QLA82XX_CRB_MAX QLA82XX_PCI_CRB_WINDOW(64)
472 /*
473 * ====================== BASE ADDRESSES ON-CHIP ======================
474 * Base addresses of major components on-chip.
475 * ====================== BASE ADDRESSES ON-CHIP ======================
476 */
477 #define QLA82XX_ADDR_DDR_NET (0x0000000000000000ULL)
478 #define QLA82XX_ADDR_DDR_NET_MAX (0x000000000fffffffULL)
480 /* Imbus address bit used to indicate a host address. This bit is
481 * eliminated by the pcie bar and bar select before presentation
482 * over pcie. */
483 /* host memory via IMBUS */
484 #define QLA82XX_P2_ADDR_PCIE (0x0000000800000000ULL)
485 #define QLA82XX_P3_ADDR_PCIE (0x0000008000000000ULL)
486 #define QLA82XX_ADDR_PCIE_MAX (0x0000000FFFFFFFFFULL)
487 #define QLA82XX_ADDR_OCM0 (0x0000000200000000ULL)
488 #define QLA82XX_ADDR_OCM0_MAX (0x00000002000fffffULL)
489 #define QLA82XX_ADDR_OCM1 (0x0000000200400000ULL)
490 #define QLA82XX_ADDR_OCM1_MAX (0x00000002004fffffULL)
491 #define QLA82XX_ADDR_QDR_NET (0x0000000300000000ULL)
493 #define QLA82XX_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
494 #define QLA82XX_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
496 #define QLA82XX_PCI_CRBSPACE (unsigned long)0x06000000
497 #define QLA82XX_PCI_DIRECT_CRB (unsigned long)0x04400000
498 #define QLA82XX_PCI_CAMQM (unsigned long)0x04800000
499 #define QLA82XX_PCI_CAMQM_MAX (unsigned long)0x04ffffff
500 #define QLA82XX_PCI_DDR_NET (unsigned long)0x00000000
501 #define QLA82XX_PCI_QDR_NET (unsigned long)0x04000000
502 #define QLA82XX_PCI_QDR_NET_MAX (unsigned long)0x043fffff
504 /*
505 * Register offsets for MN
506 */
507 #define MIU_CONTROL (0x000)
508 #define MIU_TAG (0x004)
509 #define MIU_TEST_AGT_CTRL (0x090)
510 #define MIU_TEST_AGT_ADDR_LO (0x094)
511 #define MIU_TEST_AGT_ADDR_HI (0x098)
512 #define MIU_TEST_AGT_WRDATA_LO (0x0a0)
513 #define MIU_TEST_AGT_WRDATA_HI (0x0a4)
514 #define MIU_TEST_AGT_WRDATA(i) (0x0a0+(4*(i)))
515 #define MIU_TEST_AGT_RDDATA_LO (0x0a8)
516 #define MIU_TEST_AGT_RDDATA_HI (0x0ac)
517 #define MIU_TEST_AGT_RDDATA(i) (0x0a8+(4*(i)))
518 #define MIU_TEST_AGT_ADDR_MASK 0xfffffff8
519 #define MIU_TEST_AGT_UPPER_ADDR(off) (0)
521 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
522 #define MIU_TA_CTL_START 1
523 #define MIU_TA_CTL_ENABLE 2
524 #define MIU_TA_CTL_WRITE 4
525 #define MIU_TA_CTL_BUSY 8
527 /*CAM RAM */
528 # define QLA82XX_CAM_RAM_BASE (QLA82XX_CRB_CAM + 0x02000)
529 # define QLA82XX_CAM_RAM(reg) (QLA82XX_CAM_RAM_BASE + (reg))
531 #define QLA82XX_PORT_MODE_ADDR (QLA82XX_CAM_RAM(0x24))
532 #define QLA82XX_PEG_HALT_STATUS1 (QLA82XX_CAM_RAM(0xa8))
533 #define QLA82XX_PEG_HALT_STATUS2 (QLA82XX_CAM_RAM(0xac))
534 #define QLA82XX_PEG_ALIVE_COUNTER (QLA82XX_CAM_RAM(0xb0))
535 #define QLA82XX_CAM_RAM_DB1 (QLA82XX_CAM_RAM(0x1b0))
536 #define QLA82XX_CAM_RAM_DB2 (QLA82XX_CAM_RAM(0x1b4))
538 #define HALT_STATUS_UNRECOVERABLE 0x80000000
539 #define HALT_STATUS_RECOVERABLE 0x40000000
542 #define QLA82XX_ROM_LOCK_ID (QLA82XX_CAM_RAM(0x100))
543 #define QLA82XX_CRB_WIN_LOCK_ID (QLA82XX_CAM_RAM(0x124))
544 #define QLA82XX_FW_VERSION_MAJOR (QLA82XX_CAM_RAM(0x150))
545 #define QLA82XX_FW_VERSION_MINOR (QLA82XX_CAM_RAM(0x154))
546 #define QLA82XX_FW_VERSION_SUB (QLA82XX_CAM_RAM(0x158))
547 #define QLA82XX_PCIE_REG(reg) (QLA82XX_CRB_PCIE + (reg))
549 /* Driver Coexistence Defines */
550 #define QLA82XX_CRB_DRV_ACTIVE (QLA82XX_CAM_RAM(0x138))
551 #define QLA82XX_CRB_DEV_STATE (QLA82XX_CAM_RAM(0x140))
552 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
553 #define QLA82XX_CRB_DRV_IDC_VERSION (QLA82XX_CAM_RAM(0x174))
554 #define QLA82XX_CRB_DRV_STATE (QLA82XX_CAM_RAM(0x144))
555 #define QLA82XX_CRB_DRV_SCRATCH (QLA82XX_CAM_RAM(0x148))
556 #define QLA82XX_CRB_DEV_PART_INFO (QLA82XX_CAM_RAM(0x14c))
558 /* Every driver should use these Device State */
559 #define QLA82XX_DEV_COLD 1
560 #define QLA82XX_DEV_INITIALIZING 2
561 #define QLA82XX_DEV_READY 3
562 #define QLA82XX_DEV_NEED_RESET 4
563 #define QLA82XX_DEV_NEED_QUIESCENT 5
564 #define QLA82XX_DEV_FAILED 6
565 #define QLA82XX_DEV_QUIESCENT 7
568 #define QLA82XX_IDC_VERSION 0x1
569 #define ROM_DEV_INIT_TIMEOUT 30
570 #define ROM_DRV_RESET_ACK_TIMEOUT 10
572 #define PCIE_SETUP_FUNCTION (0x12040)
573 #define PCIE_SETUP_FUNCTION2 (0x12048)
575 #define QLA82XX_PCIX_PS_REG(reg) (QLA82XX_CRB_PCIX_MD + (reg))
576 #define QLA82XX_PCIX_PS2_REG(reg) (QLA82XX_CRB_PCIE2 + (reg))
585 /*
586 * The PCI VendorID and DeviceID for our board.
587 */
588 #define QLA82XX_MSIX_TBL_SPACE 8192
589 #define QLA82XX_PCI_REG_MSIX_TBL 0x44
590 #define QLA82XX_PCI_MSIX_CONTROL 0x40
597 };
601 };
606 };
608 #define ADDR_ERROR ((unsigned long) 0xffffffff)
609 #define MAX_CTL_CHECK 1000
611 /***************************************************************************
612 * PCI related defines.
613 **************************************************************************/
615 /*
616 * Interrupt related defines.
617 */
618 #define PCIX_TARGET_STATUS (0x10118)
619 #define PCIX_TARGET_STATUS_F1 (0x10160)
620 #define PCIX_TARGET_STATUS_F2 (0x10164)
621 #define PCIX_TARGET_STATUS_F3 (0x10168)
622 #define PCIX_TARGET_STATUS_F4 (0x10360)
623 #define PCIX_TARGET_STATUS_F5 (0x10364)
624 #define PCIX_TARGET_STATUS_F6 (0x10368)
625 #define PCIX_TARGET_STATUS_F7 (0x1036c)
627 #define PCIX_TARGET_MASK (0x10128)
628 #define PCIX_TARGET_MASK_F1 (0x10170)
629 #define PCIX_TARGET_MASK_F2 (0x10174)
630 #define PCIX_TARGET_MASK_F3 (0x10178)
631 #define PCIX_TARGET_MASK_F4 (0x10370)
632 #define PCIX_TARGET_MASK_F5 (0x10374)
633 #define PCIX_TARGET_MASK_F6 (0x10378)
634 #define PCIX_TARGET_MASK_F7 (0x1037c)
636 /*
637 * Message Signaled Interrupts
638 */
639 #define PCIX_MSI_F0 (0x13000)
640 #define PCIX_MSI_F1 (0x13004)
641 #define PCIX_MSI_F2 (0x13008)
642 #define PCIX_MSI_F3 (0x1300c)
643 #define PCIX_MSI_F4 (0x13010)
644 #define PCIX_MSI_F5 (0x13014)
645 #define PCIX_MSI_F6 (0x13018)
646 #define PCIX_MSI_F7 (0x1301c)
647 #define PCIX_MSI_F(FUNC) (0x13000 + ((FUNC) * 4))
649 /*
650 *
651 */
652 #define PCIX_INT_VECTOR (0x10100)
653 #define PCIX_INT_MASK (0x10104)
655 /*
656 * Interrupt state machine and other bits.
657 */
658 #define PCIE_MISCCFG_RC (0x1206c)
661 #define ISR_INT_TARGET_STATUS \
662 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS))
663 #define ISR_INT_TARGET_STATUS_F1 \
664 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F1))
665 #define ISR_INT_TARGET_STATUS_F2 \
666 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F2))
667 #define ISR_INT_TARGET_STATUS_F3 \
668 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F3))
669 #define ISR_INT_TARGET_STATUS_F4 \
670 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F4))
671 #define ISR_INT_TARGET_STATUS_F5 \
672 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F5))
673 #define ISR_INT_TARGET_STATUS_F6 \
674 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F6))
675 #define ISR_INT_TARGET_STATUS_F7 \
676 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_STATUS_F7))
678 #define ISR_INT_TARGET_MASK \
679 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK))
680 #define ISR_INT_TARGET_MASK_F1 \
681 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F1))
682 #define ISR_INT_TARGET_MASK_F2 \
683 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F2))
684 #define ISR_INT_TARGET_MASK_F3 \
685 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F3))
686 #define ISR_INT_TARGET_MASK_F4 \
687 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F4))
688 #define ISR_INT_TARGET_MASK_F5 \
689 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F5))
690 #define ISR_INT_TARGET_MASK_F6 \
691 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F6))
692 #define ISR_INT_TARGET_MASK_F7 \
693 (QLA82XX_PCIX_PS_REG(PCIX_TARGET_MASK_F7))
695 #define ISR_INT_VECTOR (QLA82XX_PCIX_PS_REG(PCIX_INT_VECTOR))
696 #define ISR_INT_MASK (QLA82XX_PCIX_PS_REG(PCIX_INT_MASK))
697 #define ISR_INT_STATE_REG (QLA82XX_PCIX_PS_REG(PCIE_MISCCFG_RC))
699 #define ISR_MSI_INT_TRIGGER(FUNC) (QLA82XX_PCIX_PS_REG(PCIX_MSI_F(FUNC)))
702 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0)
703 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200)
705 /*
706 * PCI Interrupt Vector Values.
707 */
708 #define PCIX_INT_VECTOR_BIT_F0 0x0080
709 #define PCIX_INT_VECTOR_BIT_F1 0x0100
710 #define PCIX_INT_VECTOR_BIT_F2 0x0200
711 #define PCIX_INT_VECTOR_BIT_F3 0x0400
712 #define PCIX_INT_VECTOR_BIT_F4 0x0800
713 #define PCIX_INT_VECTOR_BIT_F5 0x1000
714 #define PCIX_INT_VECTOR_BIT_F6 0x2000
715 #define PCIX_INT_VECTOR_BIT_F7 0x4000
717 /* struct qla4_8xxx_legacy_intr_set defined in ql4_def.h */
719 #define QLA82XX_LEGACY_INTR_CONFIG \
720 { \
721 { \
722 .int_vec_bit = PCIX_INT_VECTOR_BIT_F0, \
723 .tgt_status_reg = ISR_INT_TARGET_STATUS, \
724 .tgt_mask_reg = ISR_INT_TARGET_MASK, \
725 .pci_int_reg = ISR_MSI_INT_TRIGGER(0) }, \
726 \
727 { \
728 .int_vec_bit = PCIX_INT_VECTOR_BIT_F1, \
729 .tgt_status_reg = ISR_INT_TARGET_STATUS_F1, \
730 .tgt_mask_reg = ISR_INT_TARGET_MASK_F1, \
731 .pci_int_reg = ISR_MSI_INT_TRIGGER(1) }, \
732 \
733 { \
734 .int_vec_bit = PCIX_INT_VECTOR_BIT_F2, \
735 .tgt_status_reg = ISR_INT_TARGET_STATUS_F2, \
736 .tgt_mask_reg = ISR_INT_TARGET_MASK_F2, \
737 .pci_int_reg = ISR_MSI_INT_TRIGGER(2) }, \
738 \
739 { \
740 .int_vec_bit = PCIX_INT_VECTOR_BIT_F3, \
741 .tgt_status_reg = ISR_INT_TARGET_STATUS_F3, \
742 .tgt_mask_reg = ISR_INT_TARGET_MASK_F3, \
743 .pci_int_reg = ISR_MSI_INT_TRIGGER(3) }, \
744 \
745 { \
746 .int_vec_bit = PCIX_INT_VECTOR_BIT_F4, \
747 .tgt_status_reg = ISR_INT_TARGET_STATUS_F4, \
748 .tgt_mask_reg = ISR_INT_TARGET_MASK_F4, \
749 .pci_int_reg = ISR_MSI_INT_TRIGGER(4) }, \
750 \
751 { \
752 .int_vec_bit = PCIX_INT_VECTOR_BIT_F5, \
753 .tgt_status_reg = ISR_INT_TARGET_STATUS_F5, \
754 .tgt_mask_reg = ISR_INT_TARGET_MASK_F5, \
755 .pci_int_reg = ISR_MSI_INT_TRIGGER(5) }, \
756 \
757 { \
758 .int_vec_bit = PCIX_INT_VECTOR_BIT_F6, \
759 .tgt_status_reg = ISR_INT_TARGET_STATUS_F6, \
760 .tgt_mask_reg = ISR_INT_TARGET_MASK_F6, \
761 .pci_int_reg = ISR_MSI_INT_TRIGGER(6) }, \
762 \
763 { \
764 .int_vec_bit = PCIX_INT_VECTOR_BIT_F7, \
765 .tgt_status_reg = ISR_INT_TARGET_STATUS_F7, \
766 .tgt_mask_reg = ISR_INT_TARGET_MASK_F7, \
767 .pci_int_reg = ISR_MSI_INT_TRIGGER(7) }, \
768 }
770 /* Magic number to let user know flash is programmed */
771 #define QLA82XX_BDINFO_MAGIC 0x12345678
772 #define FW_SIZE_OFFSET (0x3e840c)
774 /* QLA82XX additions */
775 #define MIU_TEST_AGT_WRDATA_UPPER_LO (0x0b0)
776 #define MIU_TEST_AGT_WRDATA_UPPER_HI (0x0b4)
778 #endif