| blob | 239703dbdf4f6f1942f6ab944121a1c6c1851e9d |
1 /*
2 * linux/arch/arm/kernel/head.S
3 *
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Kernel startup code for all 32-bit CPUs
13 */
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include <asm/assembler.h>
18 #include <asm/domain.h>
19 #include <asm/ptrace.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/memory.h>
22 #include <asm/thread_info.h>
23 #include <asm/system.h>
24 #include <asm/pgtable.h>
26 #ifdef CONFIG_DEBUG_LL
27 #include <mach/debug-macro.S>
28 #endif
30 /*
31 * swapper_pg_dir is the virtual address of the initial page table.
32 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
33 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
34 * the least significant 16 bits to be 0x8000, but we could probably
35 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
36 */
37 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
38 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
39 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
40 #endif
42 #define PG_DIR_SIZE 0x4000
43 #define PMD_ORDER 2
45 .globl swapper_pg_dir
46 .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE
48 .macro pgtbl, rd, phys
49 add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE
50 .endm
52 #ifdef CONFIG_XIP_KERNEL
53 #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
54 #define KERNEL_END _edata_loc
55 #else
56 #define KERNEL_START KERNEL_RAM_VADDR
57 #define KERNEL_END _end
58 #endif
60 /*
61 * Kernel startup entry point.
62 * ---------------------------
63 *
64 * This is normally called from the decompressor code. The requirements
65 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
66 * r1 = machine nr, r2 = atags or dtb pointer.
67 *
68 * This code is mostly position independent, so if you link the kernel at
69 * 0xc0008000, you call this at __pa(0xc0008000).
70 *
71 * See linux/arch/arm/tools/mach-types for the complete list of machine
72 * numbers for r1.
73 *
74 * We're trying to keep crap to a minimum; DO NOT add any machine specific
75 * crap here - that's what the boot loader (or in extreme, well justified
76 * circumstances, zImage) is for.
77 */
78 .arm
80 __HEAD
81 ENTRY(stext)
83 THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
84 THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
85 THUMB( .thumb ) @ switch to Thumb now.
86 THUMB(1: )
88 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
89 @ and irqs disabled
90 mrc p15, 0, r9, c0, c0 @ get processor id
91 bl __lookup_processor_type @ r5=procinfo r9=cpuid
92 movs r10, r5 @ invalid processor (r5=0)?
93 THUMB( it eq ) @ force fixup-able long branch encoding
94 beq __error_p @ yes, error 'p'
96 #ifndef CONFIG_XIP_KERNEL
97 adr r3, 2f
98 ldmia r3, {r4, r8}
99 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
100 add r8, r8, r4 @ PHYS_OFFSET
101 #else
102 ldr r8, =PLAT_PHYS_OFFSET
103 #endif
105 /*
106 * r1 = machine no, r2 = atags or dtb,
107 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
108 */
109 bl __vet_atags
110 #ifdef CONFIG_SMP_ON_UP
111 bl __fixup_smp
112 #endif
113 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
114 bl __fixup_pv_table
115 #endif
116 bl __create_page_tables
118 /*
119 * The following calls CPU specific code in a position independent
120 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
121 * xxx_proc_info structure selected by __lookup_processor_type
122 * above. On return, the CPU will be ready for the MMU to be
123 * turned on, and r0 will hold the CPU control register value.
124 */
125 ldr r13, =__mmap_switched @ address to jump to after
126 @ mmu has been enabled
127 adr lr, BSYM(1f) @ return (PIC) address
128 mov r8, r4 @ set TTBR1 to swapper_pg_dir
129 ARM( add pc, r10, #PROCINFO_INITFUNC )
130 THUMB( add r12, r10, #PROCINFO_INITFUNC )
131 THUMB( mov pc, r12 )
132 1: b __enable_mmu
133 ENDPROC(stext)
134 .ltorg
135 #ifndef CONFIG_XIP_KERNEL
136 2: .long .
137 .long PAGE_OFFSET
138 #endif
140 /*
141 * Setup the initial page tables. We only setup the barest
142 * amount which are required to get the kernel running, which
143 * generally means mapping in the kernel code.
144 *
145 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
146 *
147 * Returns:
148 * r0, r3, r5-r7 corrupted
149 * r4 = physical page table address
150 */
151 __create_page_tables:
152 pgtbl r4, r8 @ page table address
154 /*
155 * Clear the swapper page table
156 */
157 mov r0, r4
158 mov r3, #0
159 add r6, r0, #PG_DIR_SIZE
160 1: str r3, [r0], #4
161 str r3, [r0], #4
162 str r3, [r0], #4
163 str r3, [r0], #4
164 teq r0, r6
165 bne 1b
167 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
169 /*
170 * Create identity mapping to cater for __enable_mmu.
171 * This identity mapping will be removed by paging_init().
172 */
173 adr r0, __enable_mmu_loc
174 ldmia r0, {r3, r5, r6}
175 sub r0, r0, r3 @ virt->phys offset
176 add r5, r5, r0 @ phys __enable_mmu
177 add r6, r6, r0 @ phys __enable_mmu_end
178 mov r5, r5, lsr #SECTION_SHIFT
179 mov r6, r6, lsr #SECTION_SHIFT
181 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base
182 str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping
183 cmp r5, r6
184 addlo r5, r5, #1 @ next section
185 blo 1b
187 /*
188 * Now setup the pagetables for our kernel direct
189 * mapped region.
190 */
191 mov r3, pc
192 mov r3, r3, lsr #SECTION_SHIFT
193 orr r3, r7, r3, lsl #SECTION_SHIFT
194 add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
195 str r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]!
196 ldr r6, =(KERNEL_END - 1)
197 add r0, r0, #1 << PMD_ORDER
198 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
199 1: cmp r0, r6
200 add r3, r3, #1 << SECTION_SHIFT
201 strls r3, [r0], #1 << PMD_ORDER
202 bls 1b
204 #ifdef CONFIG_XIP_KERNEL
205 /*
206 * Map some ram to cover our .data and .bss areas.
207 */
208 add r3, r8, #TEXT_OFFSET
209 orr r3, r3, r7
210 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER)
211 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]!
212 ldr r6, =(_end - 1)
213 add r0, r0, #4
214 add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
215 1: cmp r0, r6
216 add r3, r3, #1 << 20
217 strls r3, [r0], #4
218 bls 1b
219 #endif
221 /*
222 * Then map boot params address in r2 or
223 * the first 1MB of ram if boot params address is not specified.
224 */
225 mov r0, r2, lsr #SECTION_SHIFT
226 movs r0, r0, lsl #SECTION_SHIFT
227 moveq r0, r8
228 sub r3, r0, r8
229 add r3, r3, #PAGE_OFFSET
230 add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER)
231 orr r6, r7, r0
232 str r6, [r3]
234 #ifdef CONFIG_DEBUG_LL
235 #ifndef CONFIG_DEBUG_ICEDCC
236 /*
237 * Map in IO space for serial debugging.
238 * This allows debug messages to be output
239 * via a serial console before paging_init.
240 */
241 addruart r7, r3
243 mov r3, r3, lsr #SECTION_SHIFT
244 mov r3, r3, lsl #PMD_ORDER
246 add r0, r4, r3
247 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
248 cmp r3, #0x0800 @ limit to 512MB
249 movhi r3, #0x0800
250 add r6, r0, r3
251 mov r3, r7, lsr #SECTION_SHIFT
252 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
253 orr r3, r7, r3, lsl #SECTION_SHIFT
254 1: str r3, [r0], #4
255 add r3, r3, #1 << SECTION_SHIFT
256 cmp r0, r6
257 blo 1b
259 #else /* CONFIG_DEBUG_ICEDCC */
260 /* we don't need any serial debugging mappings for ICEDCC */
261 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
262 #endif /* !CONFIG_DEBUG_ICEDCC */
264 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
265 /*
266 * If we're using the NetWinder or CATS, we also need to map
267 * in the 16550-type serial port for the debug messages
268 */
269 add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER)
270 orr r3, r7, #0x7c000000
271 str r3, [r0]
272 #endif
273 #ifdef CONFIG_ARCH_RPC
274 /*
275 * Map in screen at 0x02000000 & SCREEN2_BASE
276 * Similar reasons here - for debug. This is
277 * only for Acorn RiscPC architectures.
278 */
279 add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER)
280 orr r3, r7, #0x02000000
281 str r3, [r0]
282 add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER)
283 str r3, [r0]
284 #endif
285 #endif
286 mov pc, lr
287 ENDPROC(__create_page_tables)
288 .ltorg
289 .align
290 __enable_mmu_loc:
291 .long .
292 .long __enable_mmu
293 .long __enable_mmu_end
295 #if defined(CONFIG_SMP)
296 __CPUINIT
297 ENTRY(secondary_startup)
298 /*
299 * Common entry point for secondary CPUs.
300 *
301 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
302 * the processor type - there is no need to check the machine type
303 * as it has already been validated by the primary processor.
304 */
305 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
306 mrc p15, 0, r9, c0, c0 @ get processor id
307 bl __lookup_processor_type
308 movs r10, r5 @ invalid processor?
309 moveq r0, #'p' @ yes, error 'p'
310 THUMB( it eq ) @ force fixup-able long branch encoding
311 beq __error_p
313 /*
314 * Use the page tables supplied from __cpu_up.
315 */
316 adr r4, __secondary_data
317 ldmia r4, {r5, r7, r12} @ address to jump to after
318 sub lr, r4, r5 @ mmu has been enabled
319 ldr r4, [r7, lr] @ get secondary_data.pgdir
320 add r7, r7, #4
321 ldr r8, [r7, lr] @ get secondary_data.swapper_pg_dir
322 adr lr, BSYM(__enable_mmu) @ return address
323 mov r13, r12 @ __secondary_switched address
324 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
325 @ (return control reg)
326 THUMB( add r12, r10, #PROCINFO_INITFUNC )
327 THUMB( mov pc, r12 )
328 ENDPROC(secondary_startup)
330 /*
331 * r6 = &secondary_data
332 */
333 ENTRY(__secondary_switched)
334 ldr sp, [r7, #4] @ get secondary_data.stack
335 mov fp, #0
336 b secondary_start_kernel
337 ENDPROC(__secondary_switched)
339 .align
341 .type __secondary_data, %object
342 __secondary_data:
343 .long .
344 .long secondary_data
345 .long __secondary_switched
346 #endif /* defined(CONFIG_SMP) */
350 /*
351 * Setup common bits before finally enabling the MMU. Essentially
352 * this is just loading the page table pointer and domain access
353 * registers.
354 *
355 * r0 = cp#15 control register
356 * r1 = machine ID
357 * r2 = atags or dtb pointer
358 * r4 = page table pointer
359 * r9 = processor ID
360 * r13 = *virtual* address to jump to upon completion
361 */
362 __enable_mmu:
363 #ifdef CONFIG_ALIGNMENT_TRAP
364 orr r0, r0, #CR_A
365 #else
366 bic r0, r0, #CR_A
367 #endif
368 #ifdef CONFIG_CPU_DCACHE_DISABLE
369 bic r0, r0, #CR_C
370 #endif
371 #ifdef CONFIG_CPU_BPREDICT_DISABLE
372 bic r0, r0, #CR_Z
373 #endif
374 #ifdef CONFIG_CPU_ICACHE_DISABLE
375 bic r0, r0, #CR_I
376 #endif
377 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
378 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
379 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
380 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
381 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
382 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
383 b __turn_mmu_on
384 ENDPROC(__enable_mmu)
386 /*
387 * Enable the MMU. This completely changes the structure of the visible
388 * memory space. You will not be able to trace execution through this.
389 * If you have an enquiry about this, *please* check the linux-arm-kernel
390 * mailing list archives BEFORE sending another post to the list.
391 *
392 * r0 = cp#15 control register
393 * r1 = machine ID
394 * r2 = atags or dtb pointer
395 * r9 = processor ID
396 * r13 = *virtual* address to jump to upon completion
397 *
398 * other registers depend on the function called upon completion
399 */
400 .align 5
401 __turn_mmu_on:
402 mov r0, r0
403 mcr p15, 0, r0, c1, c0, 0 @ write control reg
404 mrc p15, 0, r3, c0, c0, 0 @ read id reg
405 mov r3, r3
406 mov r3, r13
407 mov pc, r3
408 __enable_mmu_end:
409 ENDPROC(__turn_mmu_on)
412 #ifdef CONFIG_SMP_ON_UP
413 __INIT
414 __fixup_smp:
415 and r3, r9, #0x000f0000 @ architecture version
416 teq r3, #0x000f0000 @ CPU ID supported?
417 bne __fixup_smp_on_up @ no, assume UP
419 bic r3, r9, #0x00ff0000
420 bic r3, r3, #0x0000000f @ mask 0xff00fff0
421 mov r4, #0x41000000
422 orr r4, r4, #0x0000b000
423 orr r4, r4, #0x00000020 @ val 0x4100b020
424 teq r3, r4 @ ARM 11MPCore?
425 moveq pc, lr @ yes, assume SMP
427 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
428 and r0, r0, #0xc0000000 @ multiprocessing extensions and
429 teq r0, #0x80000000 @ not part of a uniprocessor system?
430 moveq pc, lr @ yes, assume SMP
432 __fixup_smp_on_up:
433 adr r0, 1f
434 ldmia r0, {r3 - r5}
435 sub r3, r0, r3
436 add r4, r4, r3
437 add r5, r5, r3
438 b __do_fixup_smp_on_up
439 ENDPROC(__fixup_smp)
441 .align
442 1: .word .
443 .word __smpalt_begin
444 .word __smpalt_end
446 .pushsection .data
447 .globl smp_on_up
448 smp_on_up:
449 ALT_SMP(.long 1)
450 ALT_UP(.long 0)
451 .popsection
452 #endif
454 .text
455 __do_fixup_smp_on_up:
456 cmp r4, r5
457 movhs pc, lr
458 ldmia r4!, {r0, r6}
459 ARM( str r6, [r0, r3] )
460 THUMB( add r0, r0, r3 )
461 #ifdef __ARMEB__
462 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
463 #endif
464 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
465 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
466 THUMB( strh r6, [r0] )
467 b __do_fixup_smp_on_up
468 ENDPROC(__do_fixup_smp_on_up)
470 ENTRY(fixup_smp)
471 stmfd sp!, {r4 - r6, lr}
472 mov r4, r0
473 add r5, r0, r1
474 mov r3, #0
475 bl __do_fixup_smp_on_up
476 ldmfd sp!, {r4 - r6, pc}
477 ENDPROC(fixup_smp)
479 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
481 /* __fixup_pv_table - patch the stub instructions with the delta between
482 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
483 * can be expressed by an immediate shifter operand. The stub instruction
484 * has a form of '(add|sub) rd, rn, #imm'.
485 */
486 __HEAD
487 __fixup_pv_table:
488 adr r0, 1f
489 ldmia r0, {r3-r5, r7}
490 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
491 add r4, r4, r3 @ adjust table start address
492 add r5, r5, r3 @ adjust table end address
493 add r7, r7, r3 @ adjust __pv_phys_offset address
494 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
495 mov r6, r3, lsr #24 @ constant for add/sub instructions
496 teq r3, r6, lsl #24 @ must be 16MiB aligned
497 THUMB( it ne @ cross section branch )
498 bne __error
499 str r6, [r7, #4] @ save to __pv_offset
500 b __fixup_a_pv_table
501 ENDPROC(__fixup_pv_table)
503 .align
504 1: .long .
505 .long __pv_table_begin
506 .long __pv_table_end
507 2: .long __pv_phys_offset
509 .text
510 __fixup_a_pv_table:
511 #ifdef CONFIG_THUMB2_KERNEL
512 lsls r6, #24
513 beq 2f
514 clz r7, r6
515 lsr r6, #24
516 lsl r6, r7
517 bic r6, #0x0080
518 lsrs r7, #1
519 orrcs r6, #0x0080
520 orr r6, r6, r7, lsl #12
521 orr r6, #0x4000
522 b 2f
523 1: add r7, r3
524 ldrh ip, [r7, #2]
525 and ip, 0x8f00
526 orr ip, r6 @ mask in offset bits 31-24
527 strh ip, [r7, #2]
528 2: cmp r4, r5
529 ldrcc r7, [r4], #4 @ use branch for delay slot
530 bcc 1b
531 bx lr
532 #else
533 b 2f
534 1: ldr ip, [r7, r3]
535 bic ip, ip, #0x000000ff
536 orr ip, ip, r6 @ mask in offset bits 31-24
537 str ip, [r7, r3]
538 2: cmp r4, r5
539 ldrcc r7, [r4], #4 @ use branch for delay slot
540 bcc 1b
541 mov pc, lr
542 #endif
543 ENDPROC(__fixup_a_pv_table)
545 ENTRY(fixup_pv_table)
546 stmfd sp!, {r4 - r7, lr}
547 ldr r2, 2f @ get address of __pv_phys_offset
548 mov r3, #0 @ no offset
549 mov r4, r0 @ r0 = table start
550 add r5, r0, r1 @ r1 = table size
551 ldr r6, [r2, #4] @ get __pv_offset
552 bl __fixup_a_pv_table
553 ldmfd sp!, {r4 - r7, pc}
554 ENDPROC(fixup_pv_table)
556 .align
557 2: .long __pv_phys_offset
559 .data
560 .globl __pv_phys_offset
561 .type __pv_phys_offset, %object
562 __pv_phys_offset:
563 .long 0
564 .size __pv_phys_offset, . - __pv_phys_offset
565 __pv_offset:
566 .long 0
567 #endif
569 #include "head-common.S"