Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / arch / frv / include / asm / bitops.h
blob57bf85db893f167b0cb3695c26f6e546d0b7dd04
1 /* bitops.h: bit operations for the Fujitsu FR-V CPUs
3 * For an explanation of how atomic ops work in this arch, see:
4 * Documentation/frv/atomic-ops.txt
6 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
7 * Written by David Howells (dhowells@redhat.com)
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #ifndef _ASM_BITOPS_H
15 #define _ASM_BITOPS_H
17 #include <linux/compiler.h>
18 #include <asm/byteorder.h>
20 #ifdef __KERNEL__
22 #ifndef _LINUX_BITOPS_H
23 #error only <linux/bitops.h> can be included directly
24 #endif
26 #include <asm-generic/bitops/ffz.h>
29 * clear_bit() doesn't provide any barrier for the compiler.
31 #define smp_mb__before_clear_bit() barrier()
32 #define smp_mb__after_clear_bit() barrier()
34 #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
35 static inline
36 unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v)
38 unsigned long old, tmp;
40 asm volatile(
41 "0: \n"
42 " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
43 " ckeq icc3,cc7 \n"
44 " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
45 " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
46 " and%I3 %1,%3,%2 \n"
47 " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
48 " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
49 " beq icc3,#0,0b \n"
50 : "+U"(*v), "=&r"(old), "=r"(tmp)
51 : "NPr"(~mask)
52 : "memory", "cc7", "cc3", "icc3"
55 return old;
58 static inline
59 unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v)
61 unsigned long old, tmp;
63 asm volatile(
64 "0: \n"
65 " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
66 " ckeq icc3,cc7 \n"
67 " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
68 " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
69 " or%I3 %1,%3,%2 \n"
70 " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
71 " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
72 " beq icc3,#0,0b \n"
73 : "+U"(*v), "=&r"(old), "=r"(tmp)
74 : "NPr"(mask)
75 : "memory", "cc7", "cc3", "icc3"
78 return old;
81 static inline
82 unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v)
84 unsigned long old, tmp;
86 asm volatile(
87 "0: \n"
88 " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
89 " ckeq icc3,cc7 \n"
90 " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
91 " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
92 " xor%I3 %1,%3,%2 \n"
93 " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
94 " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
95 " beq icc3,#0,0b \n"
96 : "+U"(*v), "=&r"(old), "=r"(tmp)
97 : "NPr"(mask)
98 : "memory", "cc7", "cc3", "icc3"
101 return old;
104 #else
106 extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask, volatile unsigned long *v);
107 extern unsigned long atomic_test_and_OR_mask(unsigned long mask, volatile unsigned long *v);
108 extern unsigned long atomic_test_and_XOR_mask(unsigned long mask, volatile unsigned long *v);
110 #endif
112 #define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v))
113 #define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v))
115 static inline int test_and_clear_bit(unsigned long nr, volatile void *addr)
117 volatile unsigned long *ptr = addr;
118 unsigned long mask = 1UL << (nr & 31);
119 ptr += nr >> 5;
120 return (atomic_test_and_ANDNOT_mask(mask, ptr) & mask) != 0;
123 static inline int test_and_set_bit(unsigned long nr, volatile void *addr)
125 volatile unsigned long *ptr = addr;
126 unsigned long mask = 1UL << (nr & 31);
127 ptr += nr >> 5;
128 return (atomic_test_and_OR_mask(mask, ptr) & mask) != 0;
131 static inline int test_and_change_bit(unsigned long nr, volatile void *addr)
133 volatile unsigned long *ptr = addr;
134 unsigned long mask = 1UL << (nr & 31);
135 ptr += nr >> 5;
136 return (atomic_test_and_XOR_mask(mask, ptr) & mask) != 0;
139 static inline void clear_bit(unsigned long nr, volatile void *addr)
141 test_and_clear_bit(nr, addr);
144 static inline void set_bit(unsigned long nr, volatile void *addr)
146 test_and_set_bit(nr, addr);
149 static inline void change_bit(unsigned long nr, volatile void *addr)
151 test_and_change_bit(nr, addr);
154 static inline void __clear_bit(unsigned long nr, volatile void *addr)
156 volatile unsigned long *a = addr;
157 int mask;
159 a += nr >> 5;
160 mask = 1 << (nr & 31);
161 *a &= ~mask;
164 static inline void __set_bit(unsigned long nr, volatile void *addr)
166 volatile unsigned long *a = addr;
167 int mask;
169 a += nr >> 5;
170 mask = 1 << (nr & 31);
171 *a |= mask;
174 static inline void __change_bit(unsigned long nr, volatile void *addr)
176 volatile unsigned long *a = addr;
177 int mask;
179 a += nr >> 5;
180 mask = 1 << (nr & 31);
181 *a ^= mask;
184 static inline int __test_and_clear_bit(unsigned long nr, volatile void *addr)
186 volatile unsigned long *a = addr;
187 int mask, retval;
189 a += nr >> 5;
190 mask = 1 << (nr & 31);
191 retval = (mask & *a) != 0;
192 *a &= ~mask;
193 return retval;
196 static inline int __test_and_set_bit(unsigned long nr, volatile void *addr)
198 volatile unsigned long *a = addr;
199 int mask, retval;
201 a += nr >> 5;
202 mask = 1 << (nr & 31);
203 retval = (mask & *a) != 0;
204 *a |= mask;
205 return retval;
208 static inline int __test_and_change_bit(unsigned long nr, volatile void *addr)
210 volatile unsigned long *a = addr;
211 int mask, retval;
213 a += nr >> 5;
214 mask = 1 << (nr & 31);
215 retval = (mask & *a) != 0;
216 *a ^= mask;
217 return retval;
221 * This routine doesn't need to be atomic.
223 static inline int
224 __constant_test_bit(unsigned long nr, const volatile void *addr)
226 return ((1UL << (nr & 31)) & (((const volatile unsigned int *) addr)[nr >> 5])) != 0;
229 static inline int __test_bit(unsigned long nr, const volatile void *addr)
231 int * a = (int *) addr;
232 int mask;
234 a += nr >> 5;
235 mask = 1 << (nr & 0x1f);
236 return ((mask & *a) != 0);
239 #define test_bit(nr,addr) \
240 (__builtin_constant_p(nr) ? \
241 __constant_test_bit((nr),(addr)) : \
242 __test_bit((nr),(addr)))
244 #include <asm-generic/bitops/find.h>
247 * fls - find last bit set
248 * @x: the word to search
250 * This is defined the same way as ffs:
251 * - return 32..1 to indicate bit 31..0 most significant bit set
252 * - return 0 to indicate no bits set
254 #define fls(x) \
255 ({ \
256 int bit; \
258 asm(" subcc %1,gr0,gr0,icc0 \n" \
259 " ckne icc0,cc4 \n" \
260 " cscan.p %1,gr0,%0 ,cc4,#1 \n" \
261 " csub %0,%0,%0 ,cc4,#0 \n" \
262 " csub %2,%0,%0 ,cc4,#1 \n" \
263 : "=&r"(bit) \
264 : "r"(x), "r"(32) \
265 : "icc0", "cc4" \
266 ); \
268 bit; \
272 * fls64 - find last bit set in a 64-bit value
273 * @n: the value to search
275 * This is defined the same way as ffs:
276 * - return 64..1 to indicate bit 63..0 most significant bit set
277 * - return 0 to indicate no bits set
279 static inline __attribute__((const))
280 int fls64(u64 n)
282 union {
283 u64 ll;
284 struct { u32 h, l; };
285 } _;
286 int bit, x, y;
288 _.ll = n;
290 asm(" subcc.p %3,gr0,gr0,icc0 \n"
291 " subcc %4,gr0,gr0,icc1 \n"
292 " ckne icc0,cc4 \n"
293 " ckne icc1,cc5 \n"
294 " norcr cc4,cc5,cc6 \n"
295 " csub.p %0,%0,%0 ,cc6,1 \n"
296 " orcr cc5,cc4,cc4 \n"
297 " andcr cc4,cc5,cc4 \n"
298 " cscan.p %3,gr0,%0 ,cc4,0 \n"
299 " setlos #64,%1 \n"
300 " cscan.p %4,gr0,%0 ,cc4,1 \n"
301 " setlos #32,%2 \n"
302 " csub.p %1,%0,%0 ,cc4,0 \n"
303 " csub %2,%0,%0 ,cc4,1 \n"
304 : "=&r"(bit), "=r"(x), "=r"(y)
305 : "0r"(_.h), "r"(_.l)
306 : "icc0", "icc1", "cc4", "cc5", "cc6"
308 return bit;
313 * ffs - find first bit set
314 * @x: the word to search
316 * - return 32..1 to indicate bit 31..0 most least significant bit set
317 * - return 0 to indicate no bits set
319 static inline __attribute__((const))
320 int ffs(int x)
322 /* Note: (x & -x) gives us a mask that is the least significant
323 * (rightmost) 1-bit of the value in x.
325 return fls(x & -x);
329 * __ffs - find first bit set
330 * @x: the word to search
332 * - return 31..0 to indicate bit 31..0 most least significant bit set
333 * - if no bits are set in x, the result is undefined
335 static inline __attribute__((const))
336 int __ffs(unsigned long x)
338 int bit;
339 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(x & -x));
340 return 31 - bit;
344 * __fls - find last (most-significant) set bit in a long word
345 * @word: the word to search
347 * Undefined if no set bit exists, so code should check against 0 first.
349 static inline unsigned long __fls(unsigned long word)
351 unsigned long bit;
352 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(word));
353 return bit;
357 * special slimline version of fls() for calculating ilog2_u32()
358 * - note: no protection against n == 0
360 #define ARCH_HAS_ILOG2_U32
361 static inline __attribute__((const))
362 int __ilog2_u32(u32 n)
364 int bit;
365 asm("scan %1,gr0,%0" : "=r"(bit) : "r"(n));
366 return 31 - bit;
370 * special slimline version of fls64() for calculating ilog2_u64()
371 * - note: no protection against n == 0
373 #define ARCH_HAS_ILOG2_U64
374 static inline __attribute__((const))
375 int __ilog2_u64(u64 n)
377 union {
378 u64 ll;
379 struct { u32 h, l; };
380 } _;
381 int bit, x, y;
383 _.ll = n;
385 asm(" subcc %3,gr0,gr0,icc0 \n"
386 " ckeq icc0,cc4 \n"
387 " cscan.p %3,gr0,%0 ,cc4,0 \n"
388 " setlos #63,%1 \n"
389 " cscan.p %4,gr0,%0 ,cc4,1 \n"
390 " setlos #31,%2 \n"
391 " csub.p %1,%0,%0 ,cc4,0 \n"
392 " csub %2,%0,%0 ,cc4,1 \n"
393 : "=&r"(bit), "=r"(x), "=r"(y)
394 : "0r"(_.h), "r"(_.l)
395 : "icc0", "cc4"
397 return bit;
400 #include <asm-generic/bitops/sched.h>
401 #include <asm-generic/bitops/hweight.h>
402 #include <asm-generic/bitops/lock.h>
404 #include <asm-generic/bitops/le.h>
406 #include <asm-generic/bitops/ext2-atomic-setbit.h>
408 #endif /* __KERNEL__ */
410 #endif /* _ASM_BITOPS_H */