drivers/net/wireless/mwifiex/pcie.h

   1 /* @file mwifiex_pcie.h
   2  *
   3  * @brief This file contains definitions for PCI-E interface.
   4  * driver.
   5  *
   6  * Copyright (C) 2011, Marvell International Ltd.
   7  *
   8  * This software file (the "File") is distributed by Marvell International
   9  * Ltd. under the terms of the GNU General Public License Version 2, June 1991
  10  * (the "License").  You may use, redistribute and/or modify this File in
  11  * accordance with the terms and conditions of the License, a copy of which
  12  * is available by writing to the Free Software Foundation, Inc.,
  13  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA or on the
  14  * worldwide web at http://www.gnu.org/licenses/old-licenses/gpl-2.0.txt.
  15  *
  16  * THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE EXPRESSLY DISCLAIMED.  The License provides additional details about
  19  * this warranty disclaimer.
  20  */
  21
  22 #ifndef _MWIFIEX_PCIE_H
  23 #define _MWIFIEX_PCIE_H
  24
  25 #include    <linux/pci.h>
  26 #include    <linux/pcieport_if.h>
  27 #include    <linux/interrupt.h>
  28
  29 #include    "main.h"
  30
  31 #define PCIE8766_DEFAULT_FW_NAME "mrvl/pcie8766_uapsta.bin"
  32
  33 /* Constants for Buffer Descriptor (BD) rings */
  34 #define MWIFIEX_MAX_TXRX_BD                     0x20
  35 #define MWIFIEX_TXBD_MASK                       0x3F
  36 #define MWIFIEX_RXBD_MASK                       0x3F
  37
  38 #define MWIFIEX_MAX_EVT_BD                      0x04
  39 #define MWIFIEX_EVTBD_MASK                      0x07
  40
  41 /* PCIE INTERNAL REGISTERS */
  42 #define PCIE_SCRATCH_0_REG                              0xC10
  43 #define PCIE_SCRATCH_1_REG                              0xC14
  44 #define PCIE_CPU_INT_EVENT                              0xC18
  45 #define PCIE_CPU_INT_STATUS                             0xC1C
  46 #define PCIE_HOST_INT_STATUS                            0xC30
  47 #define PCIE_HOST_INT_MASK                              0xC34
  48 #define PCIE_HOST_INT_STATUS_MASK                       0xC3C
  49 #define PCIE_SCRATCH_2_REG                              0xC40
  50 #define PCIE_SCRATCH_3_REG                              0xC44
  51 #define PCIE_SCRATCH_4_REG                              0xCC0
  52 #define PCIE_SCRATCH_5_REG                              0xCC4
  53 #define PCIE_SCRATCH_6_REG                              0xCC8
  54 #define PCIE_SCRATCH_7_REG                              0xCCC
  55 #define PCIE_SCRATCH_8_REG                              0xCD0
  56 #define PCIE_SCRATCH_9_REG                              0xCD4
  57 #define PCIE_SCRATCH_10_REG                             0xCD8
  58 #define PCIE_SCRATCH_11_REG                             0xCDC
  59 #define PCIE_SCRATCH_12_REG                             0xCE0
  60
  61 #define CPU_INTR_DNLD_RDY                               BIT(0)
  62 #define CPU_INTR_DOOR_BELL                              BIT(1)
  63 #define CPU_INTR_SLEEP_CFM_DONE                 BIT(2)
  64 #define CPU_INTR_RESET                                  BIT(3)
  65
  66 #define HOST_INTR_DNLD_DONE                             BIT(0)
  67 #define HOST_INTR_UPLD_RDY                              BIT(1)
  68 #define HOST_INTR_CMD_DONE                              BIT(2)
  69 #define HOST_INTR_EVENT_RDY                             BIT(3)
  70 #define HOST_INTR_MASK                                  (HOST_INTR_DNLD_DONE | \
  71                                                          HOST_INTR_UPLD_RDY  | \
  72                                                          HOST_INTR_CMD_DONE  | \
  73                                                          HOST_INTR_EVENT_RDY)
  74
  75 #define MWIFIEX_BD_FLAG_ROLLOVER_IND                    BIT(7)
  76 #define MWIFIEX_BD_FLAG_FIRST_DESC                      BIT(0)
  77 #define MWIFIEX_BD_FLAG_LAST_DESC                       BIT(1)
  78 #define REG_CMD_ADDR_LO                                 PCIE_SCRATCH_0_REG
  79 #define REG_CMD_ADDR_HI                                 PCIE_SCRATCH_1_REG
  80 #define REG_CMD_SIZE                                    PCIE_SCRATCH_2_REG
  81
  82 #define REG_CMDRSP_ADDR_LO                              PCIE_SCRATCH_4_REG
  83 #define REG_CMDRSP_ADDR_HI                              PCIE_SCRATCH_5_REG
  84
  85 /* TX buffer description read pointer */
  86 #define REG_TXBD_RDPTR                                  PCIE_SCRATCH_6_REG
  87 /* TX buffer description write pointer */
  88 #define REG_TXBD_WRPTR                                  PCIE_SCRATCH_7_REG
  89 /* RX buffer description read pointer */
  90 #define REG_RXBD_RDPTR                                  PCIE_SCRATCH_8_REG
  91 /* RX buffer description write pointer */
  92 #define REG_RXBD_WRPTR                                  PCIE_SCRATCH_9_REG
  93 /* Event buffer description read pointer */
  94 #define REG_EVTBD_RDPTR                                 PCIE_SCRATCH_10_REG
  95 /* Event buffer description write pointer */
  96 #define REG_EVTBD_WRPTR                                 PCIE_SCRATCH_11_REG
  97 /* Driver ready signature write pointer */
  98 #define REG_DRV_READY                                   PCIE_SCRATCH_12_REG
  99
 100 /* Max retry number of command write */
 101 #define MAX_WRITE_IOMEM_RETRY                           2
 102 /* Define PCIE block size for firmware download */
 103 #define MWIFIEX_PCIE_BLOCK_SIZE_FW_DNLD         256
 104 /* FW awake cookie after FW ready */
 105 #define FW_AWAKE_COOKIE                                         (0xAA55AA55)
 106
 107 struct mwifiex_pcie_buf_desc {
 108         u64 paddr;
 109         u16 len;
 110         u16 flags;
 111 } __packed;
 112
 113 struct pcie_service_card {
 114         struct pci_dev *dev;
 115         struct mwifiex_adapter *adapter;
 116
 117         u32 txbd_wrptr;
 118         u32 txbd_rdptr;
 119         u32 txbd_ring_size;
 120         u8 *txbd_ring_vbase;
 121         phys_addr_t txbd_ring_pbase;
 122         struct mwifiex_pcie_buf_desc *txbd_ring[MWIFIEX_MAX_TXRX_BD];
 123         struct sk_buff *tx_buf_list[MWIFIEX_MAX_TXRX_BD];
 124
 125         u32 rxbd_wrptr;
 126         u32 rxbd_rdptr;
 127         u32 rxbd_ring_size;
 128         u8 *rxbd_ring_vbase;
 129         phys_addr_t rxbd_ring_pbase;
 130         struct mwifiex_pcie_buf_desc *rxbd_ring[MWIFIEX_MAX_TXRX_BD];
 131         struct sk_buff *rx_buf_list[MWIFIEX_MAX_TXRX_BD];
 132
 133         u32 evtbd_wrptr;
 134         u32 evtbd_rdptr;
 135         u32 evtbd_ring_size;
 136         u8 *evtbd_ring_vbase;
 137         phys_addr_t evtbd_ring_pbase;
 138         struct mwifiex_pcie_buf_desc *evtbd_ring[MWIFIEX_MAX_EVT_BD];
 139         struct sk_buff *evt_buf_list[MWIFIEX_MAX_EVT_BD];
 140
 141         struct sk_buff *cmd_buf;
 142         struct sk_buff *cmdrsp_buf;
 143         struct sk_buff *sleep_cookie;
 144         void __iomem *pci_mmap;
 145         void __iomem *pci_mmap1;
 146 };
 147
 148 #endif /* _MWIFIEX_PCIE_H */