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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-btrfs-devel.git] / drivers / staging / iio / adc / ad7793.c
bloba831b92cd08250707cdaf1ff0783f19f00cf87ff
1 /*
2 * AD7792/AD7793 SPI ADC driver
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19
20 #include "../iio.h"
21 #include "../sysfs.h"
22 #include "../buffer_generic.h"
23 #include "../ring_sw.h"
24 #include "../trigger.h"
25 #include "../trigger_consumer.h"
26
27 #include "ad7793.h"
28
29 /* NOTE:
30 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
31 * In order to avoid contentions on the SPI bus, it's therefore necessary
32 * to use spi bus locking.
33 *
34 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
35 */
36
37 struct ad7793_chip_info {
38 struct iio_chan_spec channel[7];
39 };
40
41 struct ad7793_state {
42 struct spi_device *spi;
43 struct iio_trigger *trig;
44 const struct ad7793_chip_info *chip_info;
45 struct regulator *reg;
46 struct ad7793_platform_data *pdata;
47 wait_queue_head_t wq_data_avail;
48 bool done;
49 bool irq_dis;
50 u16 int_vref_mv;
51 u16 mode;
52 u16 conf;
53 u32 scale_avail[8][2];
54 /* Note this uses fact that 8 the mask always fits in a long */
55 unsigned long available_scan_masks[7];
56 /*
57 * DMA (thus cache coherency maintenance) requires the
58 * transfer buffers to live in their own cache lines.
59 */
60 u8 data[4] ____cacheline_aligned;
61 };
62
63 enum ad7793_supported_device_ids {
64 ID_AD7792,
65 ID_AD7793,
66 };
67
68 static int __ad7793_write_reg(struct ad7793_state *st, bool locked,
69 bool cs_change, unsigned char reg,
70 unsigned size, unsigned val)
71 {
72 u8 *data = st->data;
73 struct spi_transfer t = {
74 .tx_buf = data,
75 .len = size + 1,
76 .cs_change = cs_change,
77 };
78 struct spi_message m;
79
80 data[0] = AD7793_COMM_WRITE | AD7793_COMM_ADDR(reg);
81
82 switch (size) {
83 case 3:
84 data[1] = val >> 16;
85 data[2] = val >> 8;
86 data[3] = val;
87 break;
88 case 2:
89 data[1] = val >> 8;
90 data[2] = val;
91 break;
92 case 1:
93 data[1] = val;
94 break;
95 default:
96 return -EINVAL;
97 }
98
99 spi_message_init(&m);
100 spi_message_add_tail(&t, &m);
101
102 if (locked)
103 return spi_sync_locked(st->spi, &m);
104 else
105 return spi_sync(st->spi, &m);
106 }
107
108 static int ad7793_write_reg(struct ad7793_state *st,
109 unsigned reg, unsigned size, unsigned val)
110 {
111 return __ad7793_write_reg(st, false, false, reg, size, val);
112 }
113
114 static int __ad7793_read_reg(struct ad7793_state *st, bool locked,
115 bool cs_change, unsigned char reg,
116 int *val, unsigned size)
117 {
118 u8 *data = st->data;
119 int ret;
120 struct spi_transfer t[] = {
121 {
122 .tx_buf = data,
123 .len = 1,
124 }, {
125 .rx_buf = data,
126 .len = size,
127 .cs_change = cs_change,
128 },
129 };
130 struct spi_message m;
131
132 data[0] = AD7793_COMM_READ | AD7793_COMM_ADDR(reg);
133
134 spi_message_init(&m);
135 spi_message_add_tail(&t[0], &m);
136 spi_message_add_tail(&t[1], &m);
137
138 if (locked)
139 ret = spi_sync_locked(st->spi, &m);
140 else
141 ret = spi_sync(st->spi, &m);
142
143 if (ret < 0)
144 return ret;
145
146 switch (size) {
147 case 3:
148 *val = data[0] << 16 | data[1] << 8 | data[2];
149 break;
150 case 2:
151 *val = data[0] << 8 | data[1];
152 break;
153 case 1:
154 *val = data[0];
155 break;
156 default:
157 return -EINVAL;
158 }
159
160 return 0;
161 }
162
163 static int ad7793_read_reg(struct ad7793_state *st,
164 unsigned reg, int *val, unsigned size)
165 {
166 return __ad7793_read_reg(st, 0, 0, reg, val, size);
167 }
168
169 static int ad7793_read(struct ad7793_state *st, unsigned ch,
170 unsigned len, int *val)
171 {
172 int ret;
173 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
174 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
175 AD7793_MODE_SEL(AD7793_MODE_SINGLE);
176
177 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
178
179 spi_bus_lock(st->spi->master);
180 st->done = false;
181
182 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
183 sizeof(st->mode), st->mode);
184 if (ret < 0)
185 goto out;
186
187 st->irq_dis = false;
188 enable_irq(st->spi->irq);
189 wait_event_interruptible(st->wq_data_avail, st->done);
190
191 ret = __ad7793_read_reg(st, 1, 0, AD7793_REG_DATA, val, len);
192 out:
193 spi_bus_unlock(st->spi->master);
194
195 return ret;
196 }
197
198 static int ad7793_calibrate(struct ad7793_state *st, unsigned mode, unsigned ch)
199 {
200 int ret;
201
202 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) | AD7793_CONF_CHAN(ch);
203 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) | AD7793_MODE_SEL(mode);
204
205 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
206
207 spi_bus_lock(st->spi->master);
208 st->done = false;
209
210 ret = __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
211 sizeof(st->mode), st->mode);
212 if (ret < 0)
213 goto out;
214
215 st->irq_dis = false;
216 enable_irq(st->spi->irq);
217 wait_event_interruptible(st->wq_data_avail, st->done);
218
219 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
220 AD7793_MODE_SEL(AD7793_MODE_IDLE);
221
222 ret = __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
223 sizeof(st->mode), st->mode);
224 out:
225 spi_bus_unlock(st->spi->master);
226
227 return ret;
228 }
229
230 static const u8 ad7793_calib_arr[6][2] = {
231 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
232 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
233 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
234 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
235 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
236 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
237 };
238
239 static int ad7793_calibrate_all(struct ad7793_state *st)
240 {
241 int i, ret;
242
243 for (i = 0; i < ARRAY_SIZE(ad7793_calib_arr); i++) {
244 ret = ad7793_calibrate(st, ad7793_calib_arr[i][0],
245 ad7793_calib_arr[i][1]);
246 if (ret)
247 goto out;
248 }
249
250 return 0;
251 out:
252 dev_err(&st->spi->dev, "Calibration failed\n");
253 return ret;
254 }
255
256 static int ad7793_setup(struct ad7793_state *st)
257 {
258 int i, ret = -1;
259 unsigned long long scale_uv;
260 u32 id;
261
262 /* reset the serial interface */
263 ret = spi_write(st->spi, (u8 *)&ret, sizeof(ret));
264 if (ret < 0)
265 goto out;
266 msleep(1); /* Wait for at least 500us */
267
268 /* write/read test for device presence */
269 ret = ad7793_read_reg(st, AD7793_REG_ID, &id, 1);
270 if (ret)
271 goto out;
272
273 id &= AD7793_ID_MASK;
274
275 if (!((id == AD7792_ID) || (id == AD7793_ID))) {
276 dev_err(&st->spi->dev, "device ID query failed\n");
277 goto out;
278 }
279
280 st->mode = (st->pdata->mode & ~AD7793_MODE_SEL(-1)) |
281 AD7793_MODE_SEL(AD7793_MODE_IDLE);
282 st->conf = st->pdata->conf & ~AD7793_CONF_CHAN(-1);
283
284 ret = ad7793_write_reg(st, AD7793_REG_MODE, sizeof(st->mode), st->mode);
285 if (ret)
286 goto out;
287
288 ret = ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
289 if (ret)
290 goto out;
291
292 ret = ad7793_write_reg(st, AD7793_REG_IO,
293 sizeof(st->pdata->io), st->pdata->io);
294 if (ret)
295 goto out;
296
297 ret = ad7793_calibrate_all(st);
298 if (ret)
299 goto out;
300
301 /* Populate available ADC input ranges */
302 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
303 scale_uv = ((u64)st->int_vref_mv * 100000000)
304 >> (st->chip_info->channel[0].scan_type.realbits -
305 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
306 scale_uv >>= i;
307
308 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
309 st->scale_avail[i][0] = scale_uv;
310 }
311
312 return 0;
313 out:
314 dev_err(&st->spi->dev, "setup failed\n");
315 return ret;
316 }
317
318 static int ad7793_scan_from_ring(struct ad7793_state *st, unsigned ch, int *val)
319 {
320 struct iio_buffer *ring = iio_priv_to_dev(st)->buffer;
321 int ret;
322 s64 dat64[2];
323 u32 *dat32 = (u32 *)dat64;
324
325 if (!(test_bit(ch, ring->scan_mask)))
326 return -EBUSY;
327
328 ret = ring->access->read_last(ring, (u8 *) &dat64);
329 if (ret)
330 return ret;
331
332 *val = *dat32;
333
334 return 0;
335 }
336
337 static int ad7793_ring_preenable(struct iio_dev *indio_dev)
338 {
339 struct ad7793_state *st = iio_priv(indio_dev);
340 struct iio_buffer *ring = indio_dev->buffer;
341 size_t d_size;
342 unsigned channel;
343
344 if (!ring->scan_count)
345 return -EINVAL;
346
347 channel = find_first_bit(ring->scan_mask,
348 indio_dev->masklength);
349
350 d_size = ring->scan_count *
351 indio_dev->channels[0].scan_type.storagebits / 8;
352
353 if (ring->scan_timestamp) {
354 d_size += sizeof(s64);
355
356 if (d_size % sizeof(s64))
357 d_size += sizeof(s64) - (d_size % sizeof(s64));
358 }
359
360 if (indio_dev->buffer->access->set_bytes_per_datum)
361 indio_dev->buffer->access->
362 set_bytes_per_datum(indio_dev->buffer, d_size);
363
364 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
365 AD7793_MODE_SEL(AD7793_MODE_CONT);
366 st->conf = (st->conf & ~AD7793_CONF_CHAN(-1)) |
367 AD7793_CONF_CHAN(indio_dev->channels[channel].address);
368
369 ad7793_write_reg(st, AD7793_REG_CONF, sizeof(st->conf), st->conf);
370
371 spi_bus_lock(st->spi->master);
372 __ad7793_write_reg(st, 1, 1, AD7793_REG_MODE,
373 sizeof(st->mode), st->mode);
374
375 st->irq_dis = false;
376 enable_irq(st->spi->irq);
377
378 return 0;
379 }
380
381 static int ad7793_ring_postdisable(struct iio_dev *indio_dev)
382 {
383 struct ad7793_state *st = iio_priv(indio_dev);
384
385 st->mode = (st->mode & ~AD7793_MODE_SEL(-1)) |
386 AD7793_MODE_SEL(AD7793_MODE_IDLE);
387
388 st->done = false;
389 wait_event_interruptible(st->wq_data_avail, st->done);
390
391 if (!st->irq_dis)
392 disable_irq_nosync(st->spi->irq);
393
394 __ad7793_write_reg(st, 1, 0, AD7793_REG_MODE,
395 sizeof(st->mode), st->mode);
396
397 return spi_bus_unlock(st->spi->master);
398 }
399
400 /**
401 * ad7793_trigger_handler() bh of trigger launched polling to ring buffer
402 **/
403
404 static irqreturn_t ad7793_trigger_handler(int irq, void *p)
405 {
406 struct iio_poll_func *pf = p;
407 struct iio_dev *indio_dev = pf->indio_dev;
408 struct iio_buffer *ring = indio_dev->buffer;
409 struct ad7793_state *st = iio_priv(indio_dev);
410 s64 dat64[2];
411 s32 *dat32 = (s32 *)dat64;
412
413 if (ring->scan_count)
414 __ad7793_read_reg(st, 1, 1, AD7793_REG_DATA,
415 dat32,
416 indio_dev->channels[0].scan_type.realbits/8);
417
418 /* Guaranteed to be aligned with 8 byte boundary */
419 if (ring->scan_timestamp)
420 dat64[1] = pf->timestamp;
421
422 ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
423
424 iio_trigger_notify_done(indio_dev->trig);
425 st->irq_dis = false;
426 enable_irq(st->spi->irq);
427
428 return IRQ_HANDLED;
429 }
430
431 static const struct iio_buffer_setup_ops ad7793_ring_setup_ops = {
432 .preenable = &ad7793_ring_preenable,
433 .postenable = &iio_triggered_buffer_postenable,
434 .predisable = &iio_triggered_buffer_predisable,
435 .postdisable = &ad7793_ring_postdisable,
436 };
437
438 static int ad7793_register_ring_funcs_and_init(struct iio_dev *indio_dev)
439 {
440 int ret;
441
442 indio_dev->buffer = iio_sw_rb_allocate(indio_dev);
443 if (!indio_dev->buffer) {
444 ret = -ENOMEM;
445 goto error_ret;
446 }
447 /* Effectively select the ring buffer implementation */
448 indio_dev->buffer->access = &ring_sw_access_funcs;
449 indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
450 &ad7793_trigger_handler,
451 IRQF_ONESHOT,
452 indio_dev,
453 "ad7793_consumer%d",
454 indio_dev->id);
455 if (indio_dev->pollfunc == NULL) {
456 ret = -ENOMEM;
457 goto error_deallocate_sw_rb;
458 }
459
460 /* Ring buffer functions - here trigger setup related */
461 indio_dev->buffer->setup_ops = &ad7793_ring_setup_ops;
462
463 /* Flag that polled ring buffering is possible */
464 indio_dev->modes |= INDIO_BUFFER_TRIGGERED;
465 return 0;
466
467 error_deallocate_sw_rb:
468 iio_sw_rb_free(indio_dev->buffer);
469 error_ret:
470 return ret;
471 }
472
473 static void ad7793_ring_cleanup(struct iio_dev *indio_dev)
474 {
475 iio_dealloc_pollfunc(indio_dev->pollfunc);
476 iio_sw_rb_free(indio_dev->buffer);
477 }
478
479 /**
480 * ad7793_data_rdy_trig_poll() the event handler for the data rdy trig
481 **/
482 static irqreturn_t ad7793_data_rdy_trig_poll(int irq, void *private)
483 {
484 struct ad7793_state *st = iio_priv(private);
485
486 st->done = true;
487 wake_up_interruptible(&st->wq_data_avail);
488 disable_irq_nosync(irq);
489 st->irq_dis = true;
490 iio_trigger_poll(st->trig, iio_get_time_ns());
491
492 return IRQ_HANDLED;
493 }
494
495 static int ad7793_probe_trigger(struct iio_dev *indio_dev)
496 {
497 struct ad7793_state *st = iio_priv(indio_dev);
498 int ret;
499
500 st->trig = iio_allocate_trigger("%s-dev%d",
501 spi_get_device_id(st->spi)->name,
502 indio_dev->id);
503 if (st->trig == NULL) {
504 ret = -ENOMEM;
505 goto error_ret;
506 }
507
508 ret = request_irq(st->spi->irq,
509 ad7793_data_rdy_trig_poll,
510 IRQF_TRIGGER_LOW,
511 spi_get_device_id(st->spi)->name,
512 indio_dev);
513 if (ret)
514 goto error_free_trig;
515
516 disable_irq_nosync(st->spi->irq);
517 st->irq_dis = true;
518 st->trig->dev.parent = &st->spi->dev;
519 st->trig->owner = THIS_MODULE;
520 st->trig->private_data = indio_dev;
521
522 ret = iio_trigger_register(st->trig);
523
524 /* select default trigger */
525 indio_dev->trig = st->trig;
526 if (ret)
527 goto error_free_irq;
528
529 return 0;
530
531 error_free_irq:
532 free_irq(st->spi->irq, indio_dev);
533 error_free_trig:
534 iio_free_trigger(st->trig);
535 error_ret:
536 return ret;
537 }
538
539 static void ad7793_remove_trigger(struct iio_dev *indio_dev)
540 {
541 struct ad7793_state *st = iio_priv(indio_dev);
542
543 iio_trigger_unregister(st->trig);
544 free_irq(st->spi->irq, indio_dev);
545 iio_free_trigger(st->trig);
546 }
547
548 static const u16 sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 33, 19,
549 17, 16, 12, 10, 8, 6, 4};
550
551 static ssize_t ad7793_read_frequency(struct device *dev,
552 struct device_attribute *attr,
553 char *buf)
554 {
555 struct iio_dev *indio_dev = dev_get_drvdata(dev);
556 struct ad7793_state *st = iio_priv(indio_dev);
557
558 return sprintf(buf, "%d\n",
559 sample_freq_avail[AD7793_MODE_RATE(st->mode)]);
560 }
561
562 static ssize_t ad7793_write_frequency(struct device *dev,
563 struct device_attribute *attr,
564 const char *buf,
565 size_t len)
566 {
567 struct iio_dev *indio_dev = dev_get_drvdata(dev);
568 struct ad7793_state *st = iio_priv(indio_dev);
569 long lval;
570 int i, ret;
571
572 mutex_lock(&indio_dev->mlock);
573 if (iio_buffer_enabled(indio_dev)) {
574 mutex_unlock(&indio_dev->mlock);
575 return -EBUSY;
576 }
577 mutex_unlock(&indio_dev->mlock);
578
579 ret = strict_strtol(buf, 10, &lval);
580 if (ret)
581 return ret;
582
583 ret = -EINVAL;
584
585 for (i = 0; i < ARRAY_SIZE(sample_freq_avail); i++)
586 if (lval == sample_freq_avail[i]) {
587 mutex_lock(&indio_dev->mlock);
588 st->mode &= ~AD7793_MODE_RATE(-1);
589 st->mode |= AD7793_MODE_RATE(i);
590 ad7793_write_reg(st, AD7793_REG_MODE,
591 sizeof(st->mode), st->mode);
592 mutex_unlock(&indio_dev->mlock);
593 ret = 0;
594 }
595
596 return ret ? ret : len;
597 }
598
599 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
600 ad7793_read_frequency,
601 ad7793_write_frequency);
602
603 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
604 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
605
606 static ssize_t ad7793_show_scale_available(struct device *dev,
607 struct device_attribute *attr, char *buf)
608 {
609 struct iio_dev *indio_dev = dev_get_drvdata(dev);
610 struct ad7793_state *st = iio_priv(indio_dev);
611 int i, len = 0;
612
613 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
614 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
615 st->scale_avail[i][1]);
616
617 len += sprintf(buf + len, "\n");
618
619 return len;
620 }
621
622 static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available, in-in_scale_available,
623 S_IRUGO, ad7793_show_scale_available, NULL, 0);
624
625 static struct attribute *ad7793_attributes[] = {
626 &iio_dev_attr_sampling_frequency.dev_attr.attr,
627 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
628 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
629 NULL
630 };
631
632 static const struct attribute_group ad7793_attribute_group = {
633 .attrs = ad7793_attributes,
634 };
635
636 static int ad7793_read_raw(struct iio_dev *indio_dev,
637 struct iio_chan_spec const *chan,
638 int *val,
639 int *val2,
640 long m)
641 {
642 struct ad7793_state *st = iio_priv(indio_dev);
643 int ret, smpl = 0;
644 unsigned long long scale_uv;
645 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
646
647 switch (m) {
648 case 0:
649 mutex_lock(&indio_dev->mlock);
650 if (iio_buffer_enabled(indio_dev))
651 ret = ad7793_scan_from_ring(st,
652 chan->scan_index, &smpl);
653 else
654 ret = ad7793_read(st, chan->address,
655 chan->scan_type.realbits / 8, &smpl);
656 mutex_unlock(&indio_dev->mlock);
657
658 if (ret < 0)
659 return ret;
660
661 *val = (smpl >> chan->scan_type.shift) &
662 ((1 << (chan->scan_type.realbits)) - 1);
663
664 if (!unipolar)
665 *val -= (1 << (chan->scan_type.realbits - 1));
666
667 return IIO_VAL_INT;
668
669 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
670 *val = st->scale_avail[(st->conf >> 8) & 0x7][0];
671 *val2 = st->scale_avail[(st->conf >> 8) & 0x7][1];
672
673 return IIO_VAL_INT_PLUS_NANO;
674
675 case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
676 switch (chan->type) {
677 case IIO_VOLTAGE:
678 /* 1170mV / 2^23 * 6 */
679 scale_uv = (1170ULL * 100000000ULL * 6ULL)
680 >> (chan->scan_type.realbits -
681 (unipolar ? 0 : 1));
682 break;
683 case IIO_TEMP:
684 /* Always uses unity gain and internal ref */
685 scale_uv = (2500ULL * 100000000ULL)
686 >> (chan->scan_type.realbits -
687 (unipolar ? 0 : 1));
688 break;
689 default:
690 return -EINVAL;
691 }
692
693 *val2 = do_div(scale_uv, 100000000) * 10;
694 *val = scale_uv;
695
696 return IIO_VAL_INT_PLUS_NANO;
697 }
698 return -EINVAL;
699 }
700
701 static int ad7793_write_raw(struct iio_dev *indio_dev,
702 struct iio_chan_spec const *chan,
703 int val,
704 int val2,
705 long mask)
706 {
707 struct ad7793_state *st = iio_priv(indio_dev);
708 int ret, i;
709 unsigned int tmp;
710
711 mutex_lock(&indio_dev->mlock);
712 if (iio_buffer_enabled(indio_dev)) {
713 mutex_unlock(&indio_dev->mlock);
714 return -EBUSY;
715 }
716
717 switch (mask) {
718 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
719 ret = -EINVAL;
720 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
721 if (val2 == st->scale_avail[i][1]) {
722 tmp = st->conf;
723 st->conf &= ~AD7793_CONF_GAIN(-1);
724 st->conf |= AD7793_CONF_GAIN(i);
725
726 if (tmp != st->conf) {
727 ad7793_write_reg(st, AD7793_REG_CONF,
728 sizeof(st->conf),
729 st->conf);
730 ad7793_calibrate_all(st);
731 }
732 ret = 0;
733 }
734
735 default:
736 ret = -EINVAL;
737 }
738
739 mutex_unlock(&indio_dev->mlock);
740 return ret;
741 }
742
743 static int ad7793_validate_trigger(struct iio_dev *indio_dev,
744 struct iio_trigger *trig)
745 {
746 if (indio_dev->trig != trig)
747 return -EINVAL;
748
749 return 0;
750 }
751
752 static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
753 struct iio_chan_spec const *chan,
754 long mask)
755 {
756 return IIO_VAL_INT_PLUS_NANO;
757 }
758
759 static const struct iio_info ad7793_info = {
760 .read_raw = &ad7793_read_raw,
761 .write_raw = &ad7793_write_raw,
762 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
763 .attrs = &ad7793_attribute_group,
764 .validate_trigger = ad7793_validate_trigger,
765 .driver_module = THIS_MODULE,
766 };
767
768 static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
769 [ID_AD7793] = {
770 .channel[0] = {
771 .type = IIO_VOLTAGE,
772 .differential = 1,
773 .indexed = 1,
774 .channel = 0,
775 .channel2 = 0,
776 .address = AD7793_CH_AIN1P_AIN1M,
777 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
778 .scan_index = 0,
779 .scan_type = IIO_ST('s', 24, 32, 0)
780 },
781 .channel[1] = {
782 .type = IIO_VOLTAGE,
783 .differential = 1,
784 .indexed = 1,
785 .channel = 1,
786 .channel2 = 1,
787 .address = AD7793_CH_AIN2P_AIN2M,
788 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
789 .scan_index = 1,
790 .scan_type = IIO_ST('s', 24, 32, 0)
791 },
792 .channel[2] = {
793 .type = IIO_VOLTAGE,
794 .differential = 1,
795 .indexed = 1,
796 .channel = 2,
797 .channel2 = 2,
798 .address = AD7793_CH_AIN3P_AIN3M,
799 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
800 .scan_index = 2,
801 .scan_type = IIO_ST('s', 24, 32, 0)
802 },
803 .channel[3] = {
804 .type = IIO_VOLTAGE,
805 .differential = 1,
806 .extend_name = "shorted",
807 .indexed = 1,
808 .channel = 2,
809 .channel2 = 2,
810 .address = AD7793_CH_AIN1M_AIN1M,
811 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
812 .scan_index = 2,
813 .scan_type = IIO_ST('s', 24, 32, 0)
814 },
815 .channel[4] = {
816 .type = IIO_TEMP,
817 .indexed = 1,
818 .channel = 0,
819 .address = AD7793_CH_TEMP,
820 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
821 .scan_index = 4,
822 .scan_type = IIO_ST('s', 24, 32, 0),
823 },
824 .channel[5] = {
825 .type = IIO_VOLTAGE,
826 .extend_name = "supply",
827 .indexed = 1,
828 .channel = 4,
829 .address = AD7793_CH_AVDD_MONITOR,
830 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
831 .scan_index = 5,
832 .scan_type = IIO_ST('s', 24, 32, 0),
833 },
834 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
835 },
836 [ID_AD7792] = {
837 .channel[0] = {
838 .type = IIO_VOLTAGE,
839 .differential = 1,
840 .indexed = 1,
841 .channel = 0,
842 .channel2 = 0,
843 .address = AD7793_CH_AIN1P_AIN1M,
844 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
845 .scan_index = 0,
846 .scan_type = IIO_ST('s', 16, 32, 0)
847 },
848 .channel[1] = {
849 .type = IIO_VOLTAGE,
850 .differential = 1,
851 .indexed = 1,
852 .channel = 1,
853 .channel2 = 1,
854 .address = AD7793_CH_AIN2P_AIN2M,
855 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
856 .scan_index = 1,
857 .scan_type = IIO_ST('s', 16, 32, 0)
858 },
859 .channel[2] = {
860 .type = IIO_VOLTAGE,
861 .differential = 1,
862 .indexed = 1,
863 .channel = 2,
864 .channel2 = 2,
865 .address = AD7793_CH_AIN3P_AIN3M,
866 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
867 .scan_index = 2,
868 .scan_type = IIO_ST('s', 16, 32, 0)
869 },
870 .channel[3] = {
871 .type = IIO_VOLTAGE,
872 .differential = 1,
873 .extend_name = "shorted",
874 .indexed = 1,
875 .channel = 2,
876 .channel2 = 2,
877 .address = AD7793_CH_AIN1M_AIN1M,
878 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED),
879 .scan_index = 2,
880 .scan_type = IIO_ST('s', 16, 32, 0)
881 },
882 .channel[4] = {
883 .type = IIO_TEMP,
884 .indexed = 1,
885 .channel = 0,
886 .address = AD7793_CH_TEMP,
887 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
888 .scan_index = 4,
889 .scan_type = IIO_ST('s', 16, 32, 0),
890 },
891 .channel[5] = {
892 .type = IIO_VOLTAGE,
893 .extend_name = "supply",
894 .indexed = 1,
895 .channel = 4,
896 .address = AD7793_CH_AVDD_MONITOR,
897 .info_mask = (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
898 .scan_index = 5,
899 .scan_type = IIO_ST('s', 16, 32, 0),
900 },
901 .channel[6] = IIO_CHAN_SOFT_TIMESTAMP(6),
902 },
903 };
904
905 static int __devinit ad7793_probe(struct spi_device *spi)
906 {
907 struct ad7793_platform_data *pdata = spi->dev.platform_data;
908 struct ad7793_state *st;
909 struct iio_dev *indio_dev;
910 int ret, i, voltage_uv = 0;
911
912 if (!pdata) {
913 dev_err(&spi->dev, "no platform data?\n");
914 return -ENODEV;
915 }
916
917 if (!spi->irq) {
918 dev_err(&spi->dev, "no IRQ?\n");
919 return -ENODEV;
920 }
921
922 indio_dev = iio_allocate_device(sizeof(*st));
923 if (indio_dev == NULL)
924 return -ENOMEM;
925
926 st = iio_priv(indio_dev);
927
928 st->reg = regulator_get(&spi->dev, "vcc");
929 if (!IS_ERR(st->reg)) {
930 ret = regulator_enable(st->reg);
931 if (ret)
932 goto error_put_reg;
933
934 voltage_uv = regulator_get_voltage(st->reg);
935 }
936
937 st->chip_info =
938 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
939
940 st->pdata = pdata;
941
942 if (pdata && pdata->vref_mv)
943 st->int_vref_mv = pdata->vref_mv;
944 else if (voltage_uv)
945 st->int_vref_mv = voltage_uv / 1000;
946 else
947 st->int_vref_mv = 2500; /* Build-in ref */
948
949 spi_set_drvdata(spi, indio_dev);
950 st->spi = spi;
951
952 indio_dev->dev.parent = &spi->dev;
953 indio_dev->name = spi_get_device_id(spi)->name;
954 indio_dev->modes = INDIO_DIRECT_MODE;
955 indio_dev->channels = st->chip_info->channel;
956 indio_dev->available_scan_masks = st->available_scan_masks;
957 indio_dev->num_channels = 7;
958 indio_dev->info = &ad7793_info;
959
960 for (i = 0; i < indio_dev->num_channels; i++) {
961 set_bit(i, &st->available_scan_masks[i]);
962 set_bit(indio_dev->
963 channels[indio_dev->num_channels - 1].scan_index,
964 &st->available_scan_masks[i]);
965 }
966
967 init_waitqueue_head(&st->wq_data_avail);
968
969 ret = ad7793_register_ring_funcs_and_init(indio_dev);
970 if (ret)
971 goto error_disable_reg;
972
973 ret = ad7793_probe_trigger(indio_dev);
974 if (ret)
975 goto error_unreg_ring;
976
977 ret = iio_buffer_register(indio_dev,
978 indio_dev->channels,
979 indio_dev->num_channels);
980 if (ret)
981 goto error_remove_trigger;
982
983 ret = ad7793_setup(st);
984 if (ret)
985 goto error_uninitialize_ring;
986
987 ret = iio_device_register(indio_dev);
988 if (ret)
989 goto error_uninitialize_ring;
990
991 return 0;
992
993 error_uninitialize_ring:
994 iio_buffer_unregister(indio_dev);
995 error_remove_trigger:
996 ad7793_remove_trigger(indio_dev);
997 error_unreg_ring:
998 ad7793_ring_cleanup(indio_dev);
999 error_disable_reg:
1000 if (!IS_ERR(st->reg))
1001 regulator_disable(st->reg);
1002 error_put_reg:
1003 if (!IS_ERR(st->reg))
1004 regulator_put(st->reg);
1005
1006 iio_free_device(indio_dev);
1007
1008 return ret;
1009 }
1010
1011 static int ad7793_remove(struct spi_device *spi)
1012 {
1013 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1014 struct ad7793_state *st = iio_priv(indio_dev);
1015
1016 iio_device_unregister(indio_dev);
1017 iio_buffer_unregister(indio_dev);
1018 ad7793_remove_trigger(indio_dev);
1019 ad7793_ring_cleanup(indio_dev);
1020
1021 if (!IS_ERR(st->reg)) {
1022 regulator_disable(st->reg);
1023 regulator_put(st->reg);
1024 }
1025
1026 iio_free_device(indio_dev);
1027
1028 return 0;
1029 }
1030
1031 static const struct spi_device_id ad7793_id[] = {
1032 {"ad7792", ID_AD7792},
1033 {"ad7793", ID_AD7793},
1034 {}
1035 };
1036
1037 static struct spi_driver ad7793_driver = {
1038 .driver = {
1039 .name = "ad7793",
1040 .bus = &spi_bus_type,
1041 .owner = THIS_MODULE,
1042 },
1043 .probe = ad7793_probe,
1044 .remove = __devexit_p(ad7793_remove),
1045 .id_table = ad7793_id,
1046 };
1047
1048 static int __init ad7793_init(void)
1049 {
1050 return spi_register_driver(&ad7793_driver);
1051 }
1052 module_init(ad7793_init);
1053
1054 static void __exit ad7793_exit(void)
1055 {
1056 spi_unregister_driver(&ad7793_driver);
1057 }
1058 module_exit(ad7793_exit);
1059
1060 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
1061 MODULE_DESCRIPTION("Analog Devices AD7792/3 ADC");
1062 MODULE_LICENSE("GPL v2");
Linux Btrfs Development