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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus
[linux-btrfs-devel.git] / drivers / staging / rtl8192e / r8192E.h
blob137f66b034bb92586e664074eb14cabe630a6c7b
1 /*
2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
5
6 Parts of this driver are based on the GPL part of the
7 official realtek driver
8
9 Parts of this driver are based on the rtl8192 driver skeleton
10 from Patric Schenke & Andres Salomon
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
13
14 We want to tanks the Authors of those projects and the Ndiswrapper
15 project Authors.
16 */
17
18 #ifndef R819xU_H
19 #define R819xU_H
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/types.h>
27 #include <linux/slab.h>
28 #include <linux/netdevice.h>
29 #include <linux/pci.h>
30 #include <linux/etherdevice.h>
31 #include <linux/delay.h>
32 #include <linux/rtnetlink.h> //for rtnl_lock()
33 #include <linux/wireless.h>
34 #include <linux/timer.h>
35 #include <linux/proc_fs.h> // Necessary because we use the proc fs
36 #include <linux/if_arp.h>
37 #include <linux/random.h>
38 #include <linux/interrupt.h>
39 #include <asm/io.h>
40 #include "ieee80211/rtl819x_HT.h"
41 #include "ieee80211/ieee80211.h"
42
43
44
45
46 #define RTL819xE_MODULE_NAME "rtl819xE"
47
48 #define FALSE 0
49 #define TRUE 1
50 #define MAX_KEY_LEN 61
51 #define KEY_BUF_SIZE 5
52
53 #define BIT0 0x00000001
54 #define BIT1 0x00000002
55 #define BIT2 0x00000004
56 #define BIT3 0x00000008
57 #define BIT4 0x00000010
58 #define BIT5 0x00000020
59 #define BIT6 0x00000040
60 #define BIT7 0x00000080
61 #define BIT8 0x00000100
62 #define BIT9 0x00000200
63 #define BIT10 0x00000400
64 #define BIT11 0x00000800
65 #define BIT12 0x00001000
66 #define BIT13 0x00002000
67 #define BIT14 0x00004000
68 #define BIT15 0x00008000
69 #define BIT16 0x00010000
70 #define BIT17 0x00020000
71 #define BIT18 0x00040000
72 #define BIT19 0x00080000
73 #define BIT20 0x00100000
74 #define BIT21 0x00200000
75 #define BIT22 0x00400000
76 #define BIT23 0x00800000
77 #define BIT24 0x01000000
78 #define BIT25 0x02000000
79 #define BIT26 0x04000000
80 #define BIT27 0x08000000
81 #define BIT28 0x10000000
82 #define BIT29 0x20000000
83 #define BIT30 0x40000000
84 #define BIT31 0x80000000
85 // Rx smooth factor
86 #define Rx_Smooth_Factor 20
87 /* 2007/06/04 MH Define sliding window for RSSI history. */
88 #define PHY_RSSI_SLID_WIN_MAX 100
89 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
90
91 #define IC_VersionCut_D 0x3
92 #define IC_VersionCut_E 0x4
93
94 #if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
95 #define DMESG(x,a...) printk(KERN_INFO RTL819xE_MODULE_NAME ": " x "\n", ## a)
96 #else
97 #define DMESG(x,a...)
98 extern u32 rt_global_debug_component;
99 #define RT_TRACE(component, x, args...) \
100 do { if(rt_global_debug_component & component) \
101 printk(KERN_DEBUG RTL819xE_MODULE_NAME ":" x , \
102 ##args);\
103 }while(0);
104
105 #define COMP_TRACE BIT0 // For function call tracing.
106 #define COMP_DBG BIT1 // Only for temporary debug message.
107 #define COMP_INIT BIT2 // during driver initialization / halt / reset.
108
109
110 #define COMP_RECV BIT3 // Reveive part data path.
111 #define COMP_SEND BIT4 // Send part path.
112 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
113 #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
114 #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
115 #define COMP_SWBW BIT8 // For bandwidth switch.
116 #define COMP_SEC BIT9// For Security.
117
118
119 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
120 #define COMP_QOS BIT11 // For QoS.
121
122 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
123 #define COMP_RXDESC BIT13 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
124 #define COMP_PHY BIT14
125 #define COMP_DIG BIT15 // For DIG, 2006.09.25, by rcnjko.
126 #define COMP_TXAGC BIT16 // For Tx power, 060928, by rcnjko.
127 #define COMP_HALDM BIT17 // For HW Dynamic Mechanism, 061010, by rcnjko.
128 #define COMP_POWER_TRACKING BIT18 //FOR 8190 TX POWER TRACKING
129 #define COMP_EVENTS BIT19 // Event handling
130
131 #define COMP_RF BIT20 // For RF.
132
133 /* 11n or 8190 specific code should be put below this line */
134
135
136 #define COMP_FIRMWARE BIT21 //for firmware downloading
137 #define COMP_HT BIT22 // For 802.11n HT related information. by Emily 2006-8-11
138
139 #define COMP_RESET BIT23
140 #define COMP_CMDPKT BIT24
141 #define COMP_SCAN BIT25
142 #define COMP_IPS BIT26
143 #define COMP_DOWN BIT27 // for rm driver module
144 #define COMP_INTR BIT28 // for interrupt
145 #define COMP_ERR BIT31 // for error out, always on
146 #endif
147
148
149 //
150 // Queue Select Value in TxDesc
151 //
152 #define QSLT_BK 0x1
153 #define QSLT_BE 0x0
154 #define QSLT_VI 0x4
155 #define QSLT_VO 0x6
156 #define QSLT_BEACON 0x10
157 #define QSLT_HIGH 0x11
158 #define QSLT_MGNT 0x12
159 #define QSLT_CMD 0x13
160
161 #define DESC90_RATE1M 0x00
162 #define DESC90_RATE2M 0x01
163 #define DESC90_RATE5_5M 0x02
164 #define DESC90_RATE11M 0x03
165 #define DESC90_RATE6M 0x04
166 #define DESC90_RATE9M 0x05
167 #define DESC90_RATE12M 0x06
168 #define DESC90_RATE18M 0x07
169 #define DESC90_RATE24M 0x08
170 #define DESC90_RATE36M 0x09
171 #define DESC90_RATE48M 0x0a
172 #define DESC90_RATE54M 0x0b
173 #define DESC90_RATEMCS0 0x00
174 #define DESC90_RATEMCS1 0x01
175 #define DESC90_RATEMCS2 0x02
176 #define DESC90_RATEMCS3 0x03
177 #define DESC90_RATEMCS4 0x04
178 #define DESC90_RATEMCS5 0x05
179 #define DESC90_RATEMCS6 0x06
180 #define DESC90_RATEMCS7 0x07
181 #define DESC90_RATEMCS8 0x08
182 #define DESC90_RATEMCS9 0x09
183 #define DESC90_RATEMCS10 0x0a
184 #define DESC90_RATEMCS11 0x0b
185 #define DESC90_RATEMCS12 0x0c
186 #define DESC90_RATEMCS13 0x0d
187 #define DESC90_RATEMCS14 0x0e
188 #define DESC90_RATEMCS15 0x0f
189 #define DESC90_RATEMCS32 0x20
190
191 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
192 #define EEPROM_Default_LegacyHTTxPowerDiff 0x4
193 #define IEEE80211_WATCH_DOG_TIME 2000
194
195 typedef u32 RT_RF_CHANGE_SOURCE;
196 #define RF_CHANGE_BY_SW BIT31
197 #define RF_CHANGE_BY_HW BIT30
198 #define RF_CHANGE_BY_PS BIT29
199 #define RF_CHANGE_BY_IPS BIT28
200 #define RF_CHANGE_BY_INIT 0 // Do not change the RFOff reason. Defined by Bruce, 2008-01-17.
201
202 // RF state.
203 typedef enum _RT_RF_POWER_STATE {
204 eRfOn,
205 eRfSleep,
206 eRfOff
207 } RT_RF_POWER_STATE;
208
209 typedef enum _RT_JOIN_ACTION {
210 RT_JOIN_INFRA = 1,
211 RT_JOIN_IBSS = 2,
212 RT_START_IBSS = 3,
213 RT_NO_ACTION = 4,
214 } RT_JOIN_ACTION;
215
216 typedef enum _IPS_CALLBACK_FUNCION {
217 IPS_CALLBACK_NONE = 0,
218 IPS_CALLBACK_MGNT_LINK_REQUEST = 1,
219 IPS_CALLBACK_JOIN_REQUEST = 2,
220 } IPS_CALLBACK_FUNCION;
221
222 typedef struct _RT_POWER_SAVE_CONTROL {
223 /* Inactive Power Save(IPS) : Disable RF when disconnected */
224 bool bInactivePs;
225 bool bIPSModeBackup;
226 bool bSwRfProcessing;
227 RT_RF_POWER_STATE eInactivePowerState;
228 struct work_struct InactivePsWorkItem;
229 struct timer_list InactivePsTimer;
230
231 /* Return point for join action */
232 IPS_CALLBACK_FUNCION ReturnPoint;
233
234 /* Recored Parameters for rescheduled JoinRequest */
235 bool bTmpBssDesc;
236 RT_JOIN_ACTION tmpJoinAction;
237 struct ieee80211_network tmpBssDesc;
238
239 /* Recored Parameters for rescheduled MgntLinkRequest */
240 bool bTmpScanOnly;
241 bool bTmpActiveScan;
242 bool bTmpFilterHiddenAP;
243 bool bTmpUpdateParms;
244 u8 tmpSsidBuf[33];
245 OCTET_STRING tmpSsid2Scan;
246 bool bTmpSsid2Scan;
247 u8 tmpNetworkType;
248 u8 tmpChannelNumber;
249 u16 tmpBcnPeriod;
250 u8 tmpDtimPeriod;
251 u16 tmpmCap;
252 OCTET_STRING tmpSuppRateSet;
253 u8 tmpSuppRateBuf[MAX_NUM_RATES];
254 bool bTmpSuppRate;
255 IbssParms tmpIbpm;
256 bool bTmpIbpm;
257
258 /*
259 * Leisure Power Save:
260 * Disable RF if connected but traffic is not busy
261 */
262 bool bLeisurePs;
263 u32 PowerProfile;
264 u8 LpsIdleCount;
265
266 u32 CurPsLevel;
267 u32 RegRfPsLevel;
268
269 bool bFwCtrlLPS;
270 u8 FWCtrlPSMode;
271
272 bool LinkReqInIPSRFOffPgs;
273 bool BufConnectinfoBefore;
274 } RT_POWER_SAVE_CONTROL, *PRT_POWER_SAVE_CONTROL;
275
276 /* For rtl819x */
277 typedef struct _tx_desc_819x_pci {
278 //DWORD 0
279 u16 PktSize;
280 u8 Offset;
281 u8 Reserved1:3;
282 u8 CmdInit:1;
283 u8 LastSeg:1;
284 u8 FirstSeg:1;
285 u8 LINIP:1;
286 u8 OWN:1;
287
288 //DWORD 1
289 u8 TxFWInfoSize;
290 u8 RATid:3;
291 u8 DISFB:1;
292 u8 USERATE:1;
293 u8 MOREFRAG:1;
294 u8 NoEnc:1;
295 u8 PIFS:1;
296 u8 QueueSelect:5;
297 u8 NoACM:1;
298 u8 Resv:2;
299 u8 SecCAMID:5;
300 u8 SecDescAssign:1;
301 u8 SecType:2;
302
303 //DWORD 2
304 u16 TxBufferSize;
305 u8 PktId:7;
306 u8 Resv1:1;
307 u8 Reserved2;
308
309 //DWORD 3
310 u32 TxBuffAddr;
311
312 //DWORD 4
313 u32 NextDescAddress;
314
315 //DWORD 5,6,7
316 u32 Reserved5;
317 u32 Reserved6;
318 u32 Reserved7;
319 }tx_desc_819x_pci, *ptx_desc_819x_pci;
320
321
322 typedef struct _tx_desc_cmd_819x_pci {
323 //DWORD 0
324 u16 PktSize;
325 u8 Reserved1;
326 u8 CmdType:3;
327 u8 CmdInit:1;
328 u8 LastSeg:1;
329 u8 FirstSeg:1;
330 u8 LINIP:1;
331 u8 OWN:1;
332
333 //DOWRD 1
334 u16 ElementReport;
335 u16 Reserved2;
336
337 //DOWRD 2
338 u16 TxBufferSize;
339 u16 Reserved3;
340
341 //DWORD 3,4,5
342 u32 TxBufferAddr;
343 u32 NextDescAddress;
344 u32 Reserved4;
345 u32 Reserved5;
346 u32 Reserved6;
347 }tx_desc_cmd_819x_pci, *ptx_desc_cmd_819x_pci;
348
349
350 typedef struct _tx_fwinfo_819x_pci {
351 //DOWRD 0
352 u8 TxRate:7;
353 u8 CtsEnable:1;
354 u8 RtsRate:7;
355 u8 RtsEnable:1;
356 u8 TxHT:1;
357 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
358 u8 TxBandwidth:1; // This is used for HT MCS rate only.
359 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
360 u8 STBC:2;
361 u8 AllowAggregation:1;
362 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
363 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
364 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
365 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
366 u8 RtsSTBC:2;
367 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
368
369 //DWORD 1
370 u8 RxMF:2;
371 u8 RxAMD:3;
372 u8 Reserved1:3;
373 u8 Reserved2;
374 u8 Reserved3;
375 u8 Reserved4;
376
377 //u32 Reserved;
378 }tx_fwinfo_819x_pci, *ptx_fwinfo_819x_pci;
379
380 typedef struct _rx_desc_819x_pci{
381 //DOWRD 0
382 u16 Length:14;
383 u16 CRC32:1;
384 u16 ICV:1;
385 u8 RxDrvInfoSize;
386 u8 Shift:2;
387 u8 PHYStatus:1;
388 u8 SWDec:1;
389 u8 LastSeg:1;
390 u8 FirstSeg:1;
391 u8 EOR:1;
392 u8 OWN:1;
393
394 //DWORD 1
395 u32 Reserved2;
396
397 //DWORD 2
398 u32 Reserved3;
399
400 //DWORD 3
401 u32 BufferAddress;
402
403 }rx_desc_819x_pci, *prx_desc_819x_pci;
404
405 typedef struct _rx_fwinfo_819x_pci{
406 //DWORD 0
407 u16 Reserved1:12;
408 u16 PartAggr:1;
409 u16 FirstAGGR:1;
410 u16 Reserved2:2;
411
412 u8 RxRate:7;
413 u8 RxHT:1;
414
415 u8 BW:1;
416 u8 SPLCP:1;
417 u8 Reserved3:2;
418 u8 PAM:1;
419 u8 Mcast:1;
420 u8 Bcast:1;
421 u8 Reserved4:1;
422
423 //DWORD 1
424 u32 TSFL;
425
426 }rx_fwinfo_819x_pci, *prx_fwinfo_819x_pci;
427
428 #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
429 #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
430 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
431 #define ENCRYPTION_MAX_OVERHEAD 128
432 #define MAX_FRAGMENT_COUNT 8
433 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
434
435 #define scrclng 4 // octets for crc32 (FCS, ICV)
436 /* 8190 Loopback Mode definition */
437 typedef enum _rtl819x_loopback{
438 RTL819X_NO_LOOPBACK = 0,
439 RTL819X_MAC_LOOPBACK = 1,
440 RTL819X_DMA_LOOPBACK = 2,
441 RTL819X_CCK_LOOPBACK = 3,
442 }rtl819x_loopback_e;
443
444 /* due to rtl8192 firmware */
445 typedef enum _desc_packet_type_e{
446 DESC_PACKET_TYPE_INIT = 0,
447 DESC_PACKET_TYPE_NORMAL = 1,
448 }desc_packet_type_e;
449
450 typedef enum _firmware_status{
451 FW_STATUS_0_INIT = 0,
452 FW_STATUS_1_MOVE_BOOT_CODE = 1,
453 FW_STATUS_2_MOVE_MAIN_CODE = 2,
454 FW_STATUS_3_TURNON_CPU = 3,
455 FW_STATUS_4_MOVE_DATA_CODE = 4,
456 FW_STATUS_5_READY = 5,
457 }firmware_status_e;
458
459 typedef struct _rt_firmware{
460 firmware_status_e firmware_status;
461 u16 cmdpacket_frag_thresold;
462 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
463 #define MAX_FW_INIT_STEP 3
464 u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
465 u16 firmware_buf_size[MAX_FW_INIT_STEP];
466 }rt_firmware, *prt_firmware;
467
468 #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
469
470 /* Firmware Queue Layout */
471 #define NUM_OF_FIRMWARE_QUEUE 10
472 #define NUM_OF_PAGES_IN_FW 0x100
473 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa
474 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007
475 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024
476 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007
477 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
478 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x2
479 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10
480 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
481 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
482 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd
483 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
484 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
485 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
486 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
487 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
488 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
489 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
490 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
491 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
492
493 #define DCAM 0xAC // Debug CAM Interface
494 #define AESMSK_FC 0xB2 // AES Mask register for frame control (0xB2~0xB3). Added by Annie, 2006-03-06.
495
496
497 #define CAM_CONTENT_COUNT 8
498 #define CFG_VALID BIT15
499 #define EPROM_93c46 0
500 #define EPROM_93c56 1
501
502 #define DEFAULT_FRAG_THRESHOLD 2342U
503 #define MIN_FRAG_THRESHOLD 256U
504 #define DEFAULT_BEACONINTERVAL 0x64U
505
506 #define DEFAULT_RETRY_RTS 7
507 #define DEFAULT_RETRY_DATA 7
508
509 #define PHY_RSSI_SLID_WIN_MAX 100
510
511
512 typedef enum _WIRELESS_MODE {
513 WIRELESS_MODE_UNKNOWN = 0x00,
514 WIRELESS_MODE_A = 0x01,
515 WIRELESS_MODE_B = 0x02,
516 WIRELESS_MODE_G = 0x04,
517 WIRELESS_MODE_AUTO = 0x08,
518 WIRELESS_MODE_N_24G = 0x10,
519 WIRELESS_MODE_N_5G = 0x20
520 } WIRELESS_MODE;
521
522 #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
523
524 typedef struct buffer
525 {
526 struct buffer *next;
527 u32 *buf;
528 dma_addr_t dma;
529
530 } buffer;
531
532 typedef struct _rt_9x_tx_rate_history {
533 u32 cck[4];
534 u32 ofdm[8];
535 // HT_MCS[0][]: BW=0 SG=0
536 // HT_MCS[1][]: BW=1 SG=0
537 // HT_MCS[2][]: BW=0 SG=1
538 // HT_MCS[3][]: BW=1 SG=1
539 u32 ht_mcs[4][16];
540 }rt_tx_rahis_t, *prt_tx_rahis_t;
541
542 typedef struct _RT_SMOOTH_DATA_4RF {
543 char elements[4][100];//array to store values
544 u32 index; //index to current array to store
545 u32 TotalNum; //num of valid elements
546 u32 TotalVal[4]; //sum of valid elements
547 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
548
549 typedef enum _tag_TxCmd_Config_Index{
550 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
551 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
552 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
553 TXCMD_SET_TX_DURATION = 0xFF900003,
554 TXCMD_SET_RX_RSSI = 0xFF900004,
555 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
556 TXCMD_XXXX_CTRL,
557 }DCMD_TXCMD_OP;
558
559 typedef struct Stats
560 {
561 unsigned long rxrdu;
562 unsigned long rxok;
563 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV
564 unsigned long rxoverflow;
565 unsigned long rxint;
566 unsigned long txoverflow;
567 unsigned long txbeokint;
568 unsigned long txbkokint;
569 unsigned long txviokint;
570 unsigned long txvookint;
571 unsigned long txbeaconokint;
572 unsigned long txbeaconerr;
573 unsigned long txmanageokint;
574 unsigned long txcmdpktokint;
575 unsigned long txfeedback;
576 unsigned long txfeedbackok;
577 unsigned long txoktotal;
578 unsigned long txbytesunicast;
579 unsigned long rxbytesunicast;
580
581 unsigned long slide_signal_strength[100];
582 unsigned long slide_evm[100];
583 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
584 unsigned long slide_evm_total; // For recording sliding window's EVM value
585 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
586 u8 rx_rssi_percentage[4];
587 u8 rx_evm_percentage[2];
588 u32 Slide_Beacon_pwdb[100];
589 u32 Slide_Beacon_Total;
590 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
591 } Stats;
592
593
594 // Bandwidth Offset
595 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
596 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
597 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
598
599 typedef struct ChnlAccessSetting {
600 u16 SIFS_Timer;
601 u16 DIFS_Timer;
602 u16 SlotTimeTimer;
603 u16 EIFS_Timer;
604 u16 CWminIndex;
605 u16 CWmaxIndex;
606 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
607
608 typedef struct _BB_REGISTER_DEFINITION{
609 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
610 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
611 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
612 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
613 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
614 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
615 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
616 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
617 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
618 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
619 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
620 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
621 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
622 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
623 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
624 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
625 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
626 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
627
628 typedef struct _rate_adaptive
629 {
630 u8 rate_adaptive_disabled;
631 u8 ratr_state;
632 u16 reserve;
633
634 u32 high_rssi_thresh_for_ra;
635 u32 high2low_rssi_thresh_for_ra;
636 u8 low2high_rssi_thresh_for_ra40M;
637 u32 low_rssi_thresh_for_ra40M;
638 u8 low2high_rssi_thresh_for_ra20M;
639 u32 low_rssi_thresh_for_ra20M;
640 u32 upper_rssi_threshold_ratr;
641 u32 middle_rssi_threshold_ratr;
642 u32 low_rssi_threshold_ratr;
643 u32 low_rssi_threshold_ratr_40M;
644 u32 low_rssi_threshold_ratr_20M;
645 u8 ping_rssi_enable; //cosa add for test
646 u32 ping_rssi_ratr; //cosa add for test
647 u32 ping_rssi_thresh_for_ra;//cosa add for test
648 u32 last_ratr;
649
650 } rate_adaptive, *prate_adaptive;
651 #define TxBBGainTableLength 37
652 #define CCKTxBBGainTableLength 23
653 typedef struct _txbbgain_struct
654 {
655 long txbb_iq_amplifygain;
656 u32 txbbgain_value;
657 } txbbgain_struct, *ptxbbgain_struct;
658
659 typedef struct _ccktxbbgain_struct
660 {
661 //The Value is from a22 to a29 one Byte one time is much Safer
662 u8 ccktxbb_valuearray[8];
663 } ccktxbbgain_struct,*pccktxbbgain_struct;
664
665
666 typedef struct _init_gain
667 {
668 u8 xaagccore1;
669 u8 xbagccore1;
670 u8 xcagccore1;
671 u8 xdagccore1;
672 u8 cca;
673
674 } init_gain, *pinit_gain;
675
676 /* 2007/11/02 MH Define RF mode temporarily for test. */
677 typedef enum tag_Rf_Operatetion_State
678 {
679 RF_STEP_INIT = 0,
680 RF_STEP_NORMAL,
681 RF_STEP_MAX
682 }RF_STEP_E;
683
684 typedef enum _RT_STATUS{
685 RT_STATUS_SUCCESS,
686 RT_STATUS_FAILURE,
687 RT_STATUS_PENDING,
688 RT_STATUS_RESOURCE
689 }RT_STATUS,*PRT_STATUS;
690
691 typedef enum _RT_CUSTOMER_ID
692 {
693 RT_CID_DEFAULT = 0,
694 RT_CID_8187_ALPHA0 = 1,
695 RT_CID_8187_SERCOMM_PS = 2,
696 RT_CID_8187_HW_LED = 3,
697 RT_CID_8187_NETGEAR = 4,
698 RT_CID_WHQL = 5,
699 RT_CID_819x_CAMEO = 6,
700 RT_CID_819x_RUNTOP = 7,
701 RT_CID_819x_Senao = 8,
702 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
703 RT_CID_819x_Netcore = 10,
704 RT_CID_Nettronix = 11,
705 RT_CID_DLINK = 12,
706 RT_CID_PRONET = 13,
707 RT_CID_COREGA = 14,
708 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
709
710 /* LED customization. */
711
712 typedef enum _LED_STRATEGY_8190{
713 SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
714 SW_LED_MODE1, // SW control for PCI Express
715 SW_LED_MODE2, // SW control for Cameo.
716 SW_LED_MODE3, // SW contorl for RunTop.
717 SW_LED_MODE4, // SW control for Netcore
718 SW_LED_MODE5, //added by vivi, for led new mode, DLINK
719 SW_LED_MODE6, //added by vivi, for led new mode, PRONET
720 HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
721 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
722
723 #define CHANNEL_PLAN_LEN 10
724
725 #define sCrcLng 4
726
727 typedef struct _TX_FWINFO_STRUCUTRE{
728 //DOWRD 0
729 u8 TxRate:7;
730 u8 CtsEnable:1;
731 u8 RtsRate:7;
732 u8 RtsEnable:1;
733 u8 TxHT:1;
734 u8 Short:1;
735 u8 TxBandwidth:1;
736 u8 TxSubCarrier:2;
737 u8 STBC:2;
738 u8 AllowAggregation:1;
739 u8 RtsHT:1;
740 u8 RtsShort:1;
741 u8 RtsBandwidth:1;
742 u8 RtsSubcarrier:2;
743 u8 RtsSTBC:2;
744 u8 EnableCPUDur:1;
745
746 //DWORD 1
747 u32 RxMF:2;
748 u32 RxAMD:3;
749 u32 Reserved1:3;
750 u32 TxAGCOffset:4;
751 u32 TxAGCSign:1;
752 u32 Tx_INFO_RSVD:6;
753 u32 PacketID:13;
754 }TX_FWINFO_T;
755
756
757 typedef struct _TX_FWINFO_8190PCI{
758 //DOWRD 0
759 u8 TxRate:7;
760 u8 CtsEnable:1;
761 u8 RtsRate:7;
762 u8 RtsEnable:1;
763 u8 TxHT:1;
764 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
765 u8 TxBandwidth:1; // This is used for HT MCS rate only.
766 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
767 u8 STBC:2;
768 u8 AllowAggregation:1;
769 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
770 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
771 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
772 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
773 u8 RtsSTBC:2;
774 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
775
776 //DWORD 1
777 u32 RxMF:2;
778 u32 RxAMD:3;
779 u32 TxPerPktInfoFeedback:1; // 1: indicate that the transimission info of this packet should be gathered by Firmware and retured by Rx Cmd.
780 u32 Reserved1:2;
781 u32 TxAGCOffset:4; // Only 90 support
782 u32 TxAGCSign:1; // Only 90 support
783 u32 RAW_TXD:1; // MAC will send data in txpktbuffer without any processing,such as CRC check
784 u32 Retry_Limit:4; // CCX Support relative retry limit FW page only support 4 bits now.
785 u32 Reserved2:1;
786 u32 PacketID:13;
787
788 // DW 2
789
790 }TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
791
792 typedef struct _phy_ofdm_rx_status_report_819xpci
793 {
794 u8 trsw_gain_X[4];
795 u8 pwdb_all;
796 u8 cfosho_X[4];
797 u8 cfotail_X[4];
798 u8 rxevm_X[2];
799 u8 rxsnr_X[4];
800 u8 pdsnr_X[2];
801 u8 csi_current_X[2];
802 u8 csi_target_X[2];
803 u8 sigevm;
804 u8 max_ex_pwr;
805 u8 sgi_en;
806 u8 rxsc_sgien_exflg;
807 }phy_sts_ofdm_819xpci_t;
808
809 typedef struct _phy_cck_rx_status_report_819xpci
810 {
811 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
812 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
813 u8 adc_pwdb_X[4];
814 u8 sq_rpt;
815 u8 cck_agc_rpt;
816 }phy_sts_cck_819xpci_t;
817
818 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
819 u8 reserved:4;
820 u8 rxsc:2;
821 u8 sgi_en:1;
822 u8 ex_intf_flag:1;
823 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
824
825 typedef enum _RT_OP_MODE{
826 RT_OP_MODE_AP,
827 RT_OP_MODE_INFRASTRUCTURE,
828 RT_OP_MODE_IBSS,
829 RT_OP_MODE_NO_LINK,
830 }RT_OP_MODE, *PRT_OP_MODE;
831
832
833 /* 2007/11/02 MH Define RF mode temporarily for test. */
834 typedef enum tag_Rf_OpType
835 {
836 RF_OP_By_SW_3wire = 0,
837 RF_OP_By_FW,
838 RF_OP_MAX
839 }RF_OpType_E;
840
841 typedef enum _RESET_TYPE {
842 RESET_TYPE_NORESET = 0x00,
843 RESET_TYPE_NORMAL = 0x01,
844 RESET_TYPE_SILENT = 0x02
845 } RESET_TYPE;
846
847 typedef struct _tx_ring{
848 u32 * desc;
849 u8 nStuckCount;
850 struct _tx_ring * next;
851 }__attribute__ ((packed)) tx_ring, * ptx_ring;
852
853 struct rtl8192_tx_ring {
854 tx_desc_819x_pci *desc;
855 dma_addr_t dma;
856 unsigned int idx;
857 unsigned int entries;
858 struct sk_buff_head queue;
859 };
860
861 #define NIC_SEND_HANG_THRESHOLD_NORMAL 4
862 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE 8
863 #define MAX_TX_QUEUE 9 // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
864
865 #define MAX_RX_COUNT 64
866 #define MAX_TX_QUEUE_COUNT 9
867
868 typedef struct r8192_priv
869 {
870 struct pci_dev *pdev;
871 u8 *mem_start;
872
873 /* maintain info from eeprom */
874 short epromtype;
875 u16 eeprom_vid;
876 u16 eeprom_did;
877 u8 eeprom_CustomerID;
878 u16 eeprom_ChannelPlan;
879 RT_CUSTOMER_ID CustomerID;
880 u8 IC_Cut;
881 int irq;
882 struct ieee80211_device *ieee80211;
883 #ifdef ENABLE_LPS
884 bool ps_force;
885 bool force_lps;
886 bool bdisable_nic;
887 #endif
888 bool being_init_adapter;
889 u8 Rf_Mode;
890 u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
891 spinlock_t irq_th_lock;
892 spinlock_t rf_ps_lock;
893 struct mutex mutex;
894
895 short chan;
896 short sens;
897 /* RX stuff */
898 rx_desc_819x_pci *rx_ring;
899 dma_addr_t rx_ring_dma;
900 unsigned int rx_idx;
901 struct sk_buff *rx_buf[MAX_RX_COUNT];
902 int rxringcount;
903 u16 rxbuffersize;
904
905 /* TX stuff */
906 struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
907 int txringcount;
908
909 struct tasklet_struct irq_rx_tasklet;
910 struct tasklet_struct irq_tx_tasklet;
911 struct tasklet_struct irq_prepare_beacon_tasklet;
912
913 short up;
914 short crcmon; //if 1 allow bad crc frame reception in monitor mode
915 struct semaphore wx_sem;
916 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
917 u8 rf_type; /* 0 means 1T2R, 1 means 2T4R */
918
919 short (*rf_set_sens)(struct net_device *dev, short sens);
920 u8 (*rf_set_chan)(struct ieee80211_device *ieee80211, u8 ch);
921 short promisc;
922 /* stats */
923 struct Stats stats;
924 struct iw_statistics wstats;
925 struct proc_dir_entry *dir_dev;
926 struct ieee80211_rx_stats previous_stats;
927
928 /* RX stuff */
929 struct sk_buff_head skb_queue;
930 struct work_struct qos_activate;
931
932 //2 Tx Related variables
933 u16 ShortRetryLimit;
934 u16 LongRetryLimit;
935
936 u32 LastRxDescTSFHigh;
937 u32 LastRxDescTSFLow;
938
939
940 //2 Rx Related variables
941 u32 ReceiveConfig;
942
943 u8 retry_data;
944 u8 retry_rts;
945
946 struct work_struct reset_wq;
947 u8 rx_chk_cnt;
948
949 //for rtl819xPci
950 // Data Rate Config. Added by Annie, 2006-04-13.
951 u16 basic_rate;
952 u8 short_preamble;
953 u8 slot_time;
954 u16 SifsTime;
955 /* WirelessMode*/
956 u8 RegWirelessMode;
957 /*Firmware*/
958 prt_firmware pFirmware;
959 rtl819x_loopback_e LoopbackMode;
960 bool AutoloadFailFlag;
961 u16 EEPROMAntPwDiff; // Antenna gain offset from B/C/D to A
962 u8 EEPROMThermalMeter;
963 u8 EEPROMCrystalCap;
964 u8 EEPROMTxPowerLevelCCK[14];// CCK channel 1~14
965 // The following definition is for eeprom 93c56
966 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
967 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
968 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
969 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
970 u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
971 u8 EEPROMLegacyHTTxPowerDiff; // Legacy to HT rate power diff
972 bool bTXPowerDataReadFromEEPORM;
973 /*channel plan*/
974 u16 RegChannelPlan; // Channel Plan specifed by user, 15: following setting of EEPROM, 0-14: default channel plan index specified by user.
975 u16 ChannelPlan;
976 /*PS related*/
977 // Rf off action for power save
978 u8 bHwRfOffAction; //0:No action, 1:By GPIO, 2:By Disable
979 /*PHY related*/
980 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
981 // Read/write are allow for following hardware information variables
982 u32 MCSTxPowerLevelOriginalOffset[6];
983 u32 CCKTxPowerLevelOriginalOffset;
984 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
985 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
986 u8 TxPowerLevelCCK_C[14];
987 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
988 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
989 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
990 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
991 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
992 u8 AntennaTxPwDiff[3]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
993 u8 CrystalCap; // CrystalCap.
994 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
995 //05/27/2008 cck power enlarge
996 u8 CckPwEnl;
997 u16 TSSI_13dBm;
998 u32 Pwr_Track;
999 u8 CCKPresentAttentuation_20Mdefault;
1000 u8 CCKPresentAttentuation_40Mdefault;
1001 char CCKPresentAttentuation_difference;
1002 char CCKPresentAttentuation;
1003 // Use to calculate PWBD.
1004 RT_RF_POWER_STATE eRFPowerState;
1005 RT_RF_CHANGE_SOURCE RfOffReason;
1006 RT_POWER_SAVE_CONTROL PowerSaveControl;
1007 u8 bCckHighPower;
1008 long undecorated_smoothed_pwdb;
1009 long undecorated_smoothed_cck_adc_pwdb[4];
1010 //for set channel
1011 u8 SwChnlInProgress;
1012 u8 SwChnlStage;
1013 u8 SwChnlStep;
1014 u8 SetBWModeInProgress;
1015 HT_CHANNEL_WIDTH CurrentChannelBW;
1016
1017 // 8190 40MHz mode
1018 //
1019 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1020 // Joseph test for shorten RF configuration time.
1021 // We save RF reg0 in this variable to reduce RF reading.
1022 //
1023 u32 RfReg0Value[4];
1024 u8 NumTotalRFPath;
1025 bool brfpath_rxenable[4];
1026 //+by amy 080507
1027 struct timer_list watch_dog_timer;
1028 u8 watchdog_last_time;
1029 u8 watchdog_check_reset_cnt;
1030
1031 //+by amy 080515 for dynamic mechenism
1032 //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1033 bool bDynamicTxHighPower; // Tx high power state
1034 bool bDynamicTxLowPower; // Tx low power state
1035 bool bLastDTPFlag_High;
1036 bool bLastDTPFlag_Low;
1037
1038 /* OFDM RSSI. For high power or not */
1039 u8 phy_check_reg824;
1040 u32 phy_reg824_bit9;
1041
1042 //Add by amy for Rate Adaptive
1043 rate_adaptive rate_adaptive;
1044 //Add by amy for TX power tracking
1045 //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1046 const txbbgain_struct * txbbgain_table;
1047 u8 txpower_count;//For 6 sec do tracking again
1048 bool btxpower_trackingInit;
1049 u8 OFDM_index;
1050 u8 CCK_index;
1051 u8 Record_CCK_20Mindex;
1052 u8 Record_CCK_40Mindex;
1053 //2007/09/10 Mars Add CCK TX Power Tracking
1054 const ccktxbbgain_struct *cck_txbbgain_table;
1055 const ccktxbbgain_struct *cck_txbbgain_ch14_table;
1056 u8 rfa_txpowertrackingindex;
1057 u8 rfa_txpowertrackingindex_real;
1058 u8 rfa_txpowertracking_default;
1059 u8 rfc_txpowertrackingindex;
1060 u8 rfc_txpowertrackingindex_real;
1061 u8 rfc_txpowertracking_default;
1062 bool btxpower_tracking;
1063 bool bcck_in_ch14;
1064
1065 //For Backup Initial Gain
1066 init_gain initgain_backup;
1067 u8 DefaultInitialGain[4];
1068 // For EDCA Turbo mode, Added by amy 080515.
1069 bool bis_any_nonbepkts;
1070 bool bcurrent_turbo_EDCA;
1071
1072 bool bis_cur_rdlstate;
1073 struct timer_list fsync_timer;
1074 u32 rate_record;
1075 u32 rateCountDiffRecord;
1076 u32 ContiuneDiffCount;
1077 bool bswitch_fsync;
1078
1079 u8 framesync;
1080 u32 framesyncC34;
1081 u8 framesyncMonitor;
1082
1083 //by amy for gpio
1084 bool bHwRadioOff;
1085 //by amy for ps
1086 RT_OP_MODE OpMode;
1087 //by amy for reset_count
1088 u32 reset_count;
1089
1090 //by amy for silent reset
1091 RESET_TYPE ResetProgress;
1092 bool bForcedSilentReset;
1093 bool bDisableNormalResetCheck;
1094 u16 TxCounter;
1095 u16 RxCounter;
1096 int IrpPendingCount;
1097 bool bResetInProgress;
1098 bool force_reset;
1099 u8 InitialGainOperateType;
1100
1101 //define work item by amy 080526
1102 struct delayed_work update_beacon_wq;
1103 struct delayed_work watch_dog_wq;
1104 struct delayed_work txpower_tracking_wq;
1105 struct delayed_work rfpath_check_wq;
1106 struct delayed_work gpio_change_rf_wq;
1107 struct delayed_work initialgain_operate_wq;
1108 struct workqueue_struct *priv_wq;
1109 }r8192_priv;
1110
1111 bool init_firmware(struct r8192_priv *priv);
1112 u32 read_cam(struct r8192_priv *priv, u8 addr);
1113 void write_cam(struct r8192_priv *priv, u8 addr, u32 data);
1114 u8 read_nic_byte(struct r8192_priv *priv, int x);
1115 u32 read_nic_dword(struct r8192_priv *priv, int x);
1116 u16 read_nic_word(struct r8192_priv *priv, int x) ;
1117 void write_nic_byte(struct r8192_priv *priv, int x,u8 y);
1118 void write_nic_word(struct r8192_priv *priv, int x,u16 y);
1119 void write_nic_dword(struct r8192_priv *priv, int x,u32 y);
1120
1121 int rtl8192_down(struct net_device *dev);
1122 int rtl8192_up(struct net_device *dev);
1123 void rtl8192_commit(struct r8192_priv *priv);
1124 void write_phy(struct net_device *dev, u8 adr, u8 data);
1125 void CamResetAllEntry(struct r8192_priv *priv);
1126 void EnableHWSecurityConfig8192(struct r8192_priv *priv);
1127 void setKey(struct r8192_priv *priv, u8 EntryNo, u8 KeyIndex, u16 KeyType,
1128 const u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1129 void firmware_init_param(struct r8192_priv *priv);
1130 RT_STATUS cmpk_message_handle_tx(struct r8192_priv *priv, u8 *codevirtualaddress, u32 packettype, u32 buffer_len);
1131
1132 #ifdef ENABLE_IPS
1133 void IPSEnter(struct r8192_priv *priv);
1134 void IPSLeave(struct r8192_priv *priv);
1135 void IPSLeave_wq(struct work_struct *work);
1136 void ieee80211_ips_leave_wq(struct ieee80211_device *ieee80211);
1137 void ieee80211_ips_leave(struct ieee80211_device *ieee80211);
1138 #endif
1139 #ifdef ENABLE_LPS
1140 void LeisurePSEnter(struct ieee80211_device *ieee80211);
1141 void LeisurePSLeave(struct ieee80211_device *ieee80211);
1142 #endif
1143
1144 bool NicIFEnableNIC(struct r8192_priv *priv);
1145 bool NicIFDisableNIC(struct r8192_priv *priv);
1146
1147 void PHY_SetRtl8192eRfOff(struct r8192_priv *priv);
1148 #endif
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