| blob | 81fe0be51c42efb990dcb84e06333a923b6e6e75 |
1 /*
2 Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
21 /*
22 Module: rt73usb
23 Abstract: Data structures and registers for the rt73usb module.
24 Supported chipsets: rt2571W & rt2671.
25 */
27 #ifndef RT73USB_H
28 #define RT73USB_H
30 /*
31 * RF chip defines.
32 */
33 #define RF5226 0x0001
34 #define RF2528 0x0002
35 #define RF5225 0x0003
36 #define RF2527 0x0004
38 /*
39 * Signal information.
40 * Defaul offset is required for RSSI <-> dBm conversion.
41 */
42 #define DEFAULT_RSSI_OFFSET 120
44 /*
45 * Register layout information.
46 */
47 #define CSR_REG_BASE 0x3000
48 #define CSR_REG_SIZE 0x04b0
49 #define EEPROM_BASE 0x0000
50 #define EEPROM_SIZE 0x0100
51 #define BBP_BASE 0x0000
52 #define BBP_SIZE 0x0080
53 #define RF_BASE 0x0004
54 #define RF_SIZE 0x0010
56 /*
57 * Number of TX queues.
58 */
59 #define NUM_TX_QUEUES 4
61 /*
62 * USB registers.
63 */
65 /*
66 * MCU_LEDCS: LED control for MCU Mailbox.
67 */
68 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
69 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
70 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
71 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
72 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
73 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
74 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
75 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
76 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
77 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
78 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
79 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
81 /*
82 * 8051 firmware image.
83 */
85 #define FIRMWARE_IMAGE_BASE 0x0800
87 /*
88 * Security key table memory.
89 * 16 entries 32-byte for shared key table
90 * 64 entries 32-byte for pairwise key table
91 * 64 entries 8-byte for pairwise ta key table
92 */
93 #define SHARED_KEY_TABLE_BASE 0x1000
94 #define PAIRWISE_KEY_TABLE_BASE 0x1200
95 #define PAIRWISE_TA_TABLE_BASE 0x1a00
97 #define SHARED_KEY_ENTRY(__idx) \
98 ( SHARED_KEY_TABLE_BASE + \
99 ((__idx) * sizeof(struct hw_key_entry)) )
100 #define PAIRWISE_KEY_ENTRY(__idx) \
101 ( PAIRWISE_KEY_TABLE_BASE + \
102 ((__idx) * sizeof(struct hw_key_entry)) )
103 #define PAIRWISE_TA_ENTRY(__idx) \
104 ( PAIRWISE_TA_TABLE_BASE + \
105 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
115 u8 cipher;
116 u8 reserved;
119 /*
120 * Since NULL frame won't be that long (256 byte),
121 * We steal 16 tail bytes to save debugging settings.
122 */
123 #define HW_DEBUG_SETTING_BASE 0x2bf0
125 /*
126 * On-chip BEACON frame space.
127 */
128 #define HW_BEACON_BASE0 0x2400
129 #define HW_BEACON_BASE1 0x2500
130 #define HW_BEACON_BASE2 0x2600
131 #define HW_BEACON_BASE3 0x2700
133 #define HW_BEACON_OFFSET(__index) \
134 ( HW_BEACON_BASE0 + (__index * 0x0100) )
136 /*
137 * MAC Control/Status Registers(CSR).
138 * Some values are set in TU, whereas 1 TU == 1024 us.
139 */
141 /*
142 * MAC_CSR0: ASIC revision number.
143 */
144 #define MAC_CSR0 0x3000
146 /*
147 * MAC_CSR1: System control register.
148 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
149 * BBP_RESET: Hardware reset BBP.
150 * HOST_READY: Host is ready after initialization, 1: ready.
151 */
152 #define MAC_CSR1 0x3004
153 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
154 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
155 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
157 /*
158 * MAC_CSR2: STA MAC register 0.
159 */
160 #define MAC_CSR2 0x3008
161 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
162 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
163 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
164 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
166 /*
167 * MAC_CSR3: STA MAC register 1.
168 * UNICAST_TO_ME_MASK:
169 * Used to mask off bits from byte 5 of the MAC address
170 * to determine the UNICAST_TO_ME bit for RX frames.
171 * The full mask is complemented by BSS_ID_MASK:
172 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
173 */
174 #define MAC_CSR3 0x300c
175 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
176 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
177 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
179 /*
180 * MAC_CSR4: BSSID register 0.
181 */
182 #define MAC_CSR4 0x3010
183 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
184 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
185 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
186 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
188 /*
189 * MAC_CSR5: BSSID register 1.
190 * BSS_ID_MASK:
191 * This mask is used to mask off bits 0 and 1 of byte 5 of the
192 * BSSID. This will make sure that those bits will be ignored
193 * when determining the MY_BSS of RX frames.
194 * 0: 1-BSSID mode (BSS index = 0)
195 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
196 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
197 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
198 */
199 #define MAC_CSR5 0x3014
200 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
201 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
202 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
204 /*
205 * MAC_CSR6: Maximum frame length register.
206 */
207 #define MAC_CSR6 0x3018
208 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
210 /*
211 * MAC_CSR7: Reserved
212 */
213 #define MAC_CSR7 0x301c
215 /*
216 * MAC_CSR8: SIFS/EIFS register.
217 * All units are in US.
218 */
219 #define MAC_CSR8 0x3020
220 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
221 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
222 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
224 /*
225 * MAC_CSR9: Back-Off control register.
226 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
227 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
228 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
229 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
230 */
231 #define MAC_CSR9 0x3024
232 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
233 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
234 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
235 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
237 /*
238 * MAC_CSR10: Power state configuration.
239 */
240 #define MAC_CSR10 0x3028
242 /*
243 * MAC_CSR11: Power saving transition time register.
244 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
245 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
246 * WAKEUP_LATENCY: In unit of TU.
247 */
248 #define MAC_CSR11 0x302c
249 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
250 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
251 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
252 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
254 /*
255 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
256 * CURRENT_STATE: 0:sleep, 1:awake.
257 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
258 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
259 */
260 #define MAC_CSR12 0x3030
261 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
262 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
263 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
264 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
266 /*
267 * MAC_CSR13: GPIO.
268 */
269 #define MAC_CSR13 0x3034
270 #define MAC_CSR13_BIT0 FIELD32(0x00000001)
271 #define MAC_CSR13_BIT1 FIELD32(0x00000002)
272 #define MAC_CSR13_BIT2 FIELD32(0x00000004)
273 #define MAC_CSR13_BIT3 FIELD32(0x00000008)
274 #define MAC_CSR13_BIT4 FIELD32(0x00000010)
275 #define MAC_CSR13_BIT5 FIELD32(0x00000020)
276 #define MAC_CSR13_BIT6 FIELD32(0x00000040)
277 #define MAC_CSR13_BIT7 FIELD32(0x00000080)
278 #define MAC_CSR13_BIT8 FIELD32(0x00000100)
279 #define MAC_CSR13_BIT9 FIELD32(0x00000200)
280 #define MAC_CSR13_BIT10 FIELD32(0x00000400)
281 #define MAC_CSR13_BIT11 FIELD32(0x00000800)
282 #define MAC_CSR13_BIT12 FIELD32(0x00001000)
284 /*
285 * MAC_CSR14: LED control register.
286 * ON_PERIOD: On period, default 70ms.
287 * OFF_PERIOD: Off period, default 30ms.
288 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
289 * SW_LED: s/w LED, 1: ON, 0: OFF.
290 * HW_LED_POLARITY: 0: active low, 1: active high.
291 */
292 #define MAC_CSR14 0x3038
293 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
294 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
295 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
296 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
297 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
298 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
300 /*
301 * MAC_CSR15: NAV control.
302 */
303 #define MAC_CSR15 0x303c
305 /*
306 * TXRX control registers.
307 * Some values are set in TU, whereas 1 TU == 1024 us.
308 */
310 /*
311 * TXRX_CSR0: TX/RX configuration register.
312 * TSF_OFFSET: Default is 24.
313 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
314 * DISABLE_RX: Disable Rx engine.
315 * DROP_CRC: Drop CRC error.
316 * DROP_PHYSICAL: Drop physical error.
317 * DROP_CONTROL: Drop control frame.
318 * DROP_NOT_TO_ME: Drop not to me unicast frame.
319 * DROP_TO_DS: Drop fram ToDs bit is true.
320 * DROP_VERSION_ERROR: Drop version error frame.
321 * DROP_MULTICAST: Drop multicast frames.
322 * DROP_BORADCAST: Drop broadcast frames.
323 * ROP_ACK_CTS: Drop received ACK and CTS.
324 */
325 #define TXRX_CSR0 0x3040
326 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
327 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
328 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
329 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
330 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
331 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
332 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
333 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
334 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
335 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
336 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
337 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
338 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
339 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
341 /*
342 * TXRX_CSR1
343 */
344 #define TXRX_CSR1 0x3044
345 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
346 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
347 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
348 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
349 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
350 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
351 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
352 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
354 /*
355 * TXRX_CSR2
356 */
357 #define TXRX_CSR2 0x3048
358 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
359 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
360 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
361 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
362 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
363 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
364 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
365 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
367 /*
368 * TXRX_CSR3
369 */
370 #define TXRX_CSR3 0x304c
371 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
372 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
373 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
374 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
375 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
376 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
377 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
378 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
380 /*
381 * TXRX_CSR4: Auto-Responder/Tx-retry register.
382 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
383 * OFDM_TX_RATE_DOWN: 1:enable.
384 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
385 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
386 */
387 #define TXRX_CSR4 0x3050
388 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
389 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
390 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
391 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
392 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
393 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
394 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
395 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
396 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
397 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
399 /*
400 * TXRX_CSR5
401 */
402 #define TXRX_CSR5 0x3054
404 /*
405 * TXRX_CSR6: ACK/CTS payload consumed time
406 */
407 #define TXRX_CSR6 0x3058
409 /*
410 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
411 */
412 #define TXRX_CSR7 0x305c
413 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
414 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
415 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
416 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
418 /*
419 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
420 */
421 #define TXRX_CSR8 0x3060
422 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
423 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
424 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
425 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
427 /*
428 * TXRX_CSR9: Synchronization control register.
429 * BEACON_INTERVAL: In unit of 1/16 TU.
430 * TSF_TICKING: Enable TSF auto counting.
431 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
432 * BEACON_GEN: Enable beacon generator.
433 */
434 #define TXRX_CSR9 0x3064
435 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
436 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
437 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
438 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
439 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
440 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
442 /*
443 * TXRX_CSR10: BEACON alignment.
444 */
445 #define TXRX_CSR10 0x3068
447 /*
448 * TXRX_CSR11: AES mask.
449 */
450 #define TXRX_CSR11 0x306c
452 /*
453 * TXRX_CSR12: TSF low 32.
454 */
455 #define TXRX_CSR12 0x3070
456 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
458 /*
459 * TXRX_CSR13: TSF high 32.
460 */
461 #define TXRX_CSR13 0x3074
462 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
464 /*
465 * TXRX_CSR14: TBTT timer.
466 */
467 #define TXRX_CSR14 0x3078
469 /*
470 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
471 */
472 #define TXRX_CSR15 0x307c
474 /*
475 * PHY control registers.
476 * Some values are set in TU, whereas 1 TU == 1024 us.
477 */
479 /*
480 * PHY_CSR0: RF/PS control.
481 */
482 #define PHY_CSR0 0x3080
483 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
484 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
486 /*
487 * PHY_CSR1
488 */
489 #define PHY_CSR1 0x3084
490 #define PHY_CSR1_RF_RPI FIELD32(0x00010000)
492 /*
493 * PHY_CSR2: Pre-TX BBP control.
494 */
495 #define PHY_CSR2 0x3088
497 /*
498 * PHY_CSR3: BBP serial control register.
499 * VALUE: Register value to program into BBP.
500 * REG_NUM: Selected BBP register.
501 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
502 * BUSY: 1: ASIC is busy execute BBP programming.
503 */
504 #define PHY_CSR3 0x308c
505 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
506 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
507 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
508 #define PHY_CSR3_BUSY FIELD32(0x00010000)
510 /*
511 * PHY_CSR4: RF serial control register
512 * VALUE: Register value (include register id) serial out to RF/IF chip.
513 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
514 * IF_SELECT: 1: select IF to program, 0: select RF to program.
515 * PLL_LD: RF PLL_LD status.
516 * BUSY: 1: ASIC is busy execute RF programming.
517 */
518 #define PHY_CSR4 0x3090
519 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
520 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
521 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
522 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
523 #define PHY_CSR4_BUSY FIELD32(0x80000000)
525 /*
526 * PHY_CSR5: RX to TX signal switch timing control.
527 */
528 #define PHY_CSR5 0x3094
529 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
531 /*
532 * PHY_CSR6: TX to RX signal timing control.
533 */
534 #define PHY_CSR6 0x3098
535 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
537 /*
538 * PHY_CSR7: TX DAC switching timing control.
539 */
540 #define PHY_CSR7 0x309c
542 /*
543 * Security control register.
544 */
546 /*
547 * SEC_CSR0: Shared key table control.
548 */
549 #define SEC_CSR0 0x30a0
550 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
551 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
552 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
553 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
554 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
555 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
556 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
557 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
558 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
559 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
560 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
561 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
562 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
563 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
564 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
565 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
567 /*
568 * SEC_CSR1: Shared key table security mode register.
569 */
570 #define SEC_CSR1 0x30a4
571 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
572 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
573 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
574 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
575 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
576 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
577 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
578 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
580 /*
581 * Pairwise key table valid bitmap registers.
582 * SEC_CSR2: pairwise key table valid bitmap 0.
583 * SEC_CSR3: pairwise key table valid bitmap 1.
584 */
585 #define SEC_CSR2 0x30a8
586 #define SEC_CSR3 0x30ac
588 /*
589 * SEC_CSR4: Pairwise key table lookup control.
590 */
591 #define SEC_CSR4 0x30b0
592 #define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
593 #define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
594 #define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
595 #define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
597 /*
598 * SEC_CSR5: shared key table security mode register.
599 */
600 #define SEC_CSR5 0x30b4
601 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
602 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
603 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
604 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
605 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
606 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
607 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
608 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
610 /*
611 * STA control registers.
612 */
614 /*
615 * STA_CSR0: RX PLCP error count & RX FCS error count.
616 */
617 #define STA_CSR0 0x30c0
618 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
619 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
621 /*
622 * STA_CSR1: RX False CCA count & RX LONG frame count.
623 */
624 #define STA_CSR1 0x30c4
625 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
626 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
628 /*
629 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
630 */
631 #define STA_CSR2 0x30c8
632 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
633 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
635 /*
636 * STA_CSR3: TX Beacon count.
637 */
638 #define STA_CSR3 0x30cc
639 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
641 /*
642 * STA_CSR4: TX Retry count.
643 */
644 #define STA_CSR4 0x30d0
645 #define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
646 #define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
648 /*
649 * STA_CSR5: TX Retry count.
650 */
651 #define STA_CSR5 0x30d4
652 #define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
653 #define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
655 /*
656 * QOS control registers.
657 */
659 /*
660 * QOS_CSR1: TXOP holder MAC address register.
661 */
662 #define QOS_CSR1 0x30e4
663 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
664 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
666 /*
667 * QOS_CSR2: TXOP holder timeout register.
668 */
669 #define QOS_CSR2 0x30e8
671 /*
672 * RX QOS-CFPOLL MAC address register.
673 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
674 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
675 */
676 #define QOS_CSR3 0x30ec
677 #define QOS_CSR4 0x30f0
679 /*
680 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
681 */
682 #define QOS_CSR5 0x30f4
684 /*
685 * WMM Scheduler Register
686 */
688 /*
689 * AIFSN_CSR: AIFSN for each EDCA AC.
690 * AIFSN0: For AC_BK.
691 * AIFSN1: For AC_BE.
692 * AIFSN2: For AC_VI.
693 * AIFSN3: For AC_VO.
694 */
695 #define AIFSN_CSR 0x0400
696 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
697 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
698 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
699 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
701 /*
702 * CWMIN_CSR: CWmin for each EDCA AC.
703 * CWMIN0: For AC_BK.
704 * CWMIN1: For AC_BE.
705 * CWMIN2: For AC_VI.
706 * CWMIN3: For AC_VO.
707 */
708 #define CWMIN_CSR 0x0404
709 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
710 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
711 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
712 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
714 /*
715 * CWMAX_CSR: CWmax for each EDCA AC.
716 * CWMAX0: For AC_BK.
717 * CWMAX1: For AC_BE.
718 * CWMAX2: For AC_VI.
719 * CWMAX3: For AC_VO.
720 */
721 #define CWMAX_CSR 0x0408
722 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
723 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
724 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
725 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
727 /*
728 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
729 * AC0_TX_OP: For AC_BK, in unit of 32us.
730 * AC1_TX_OP: For AC_BE, in unit of 32us.
731 */
732 #define AC_TXOP_CSR0 0x040c
733 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
734 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
736 /*
737 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
738 * AC2_TX_OP: For AC_VI, in unit of 32us.
739 * AC3_TX_OP: For AC_VO, in unit of 32us.
740 */
741 #define AC_TXOP_CSR1 0x0410
742 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
743 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
745 /*
746 * BBP registers.
747 * The wordsize of the BBP is 8 bits.
748 */
750 /*
751 * R2
752 */
753 #define BBP_R2_BG_MODE FIELD8(0x20)
755 /*
756 * R3
757 */
758 #define BBP_R3_SMART_MODE FIELD8(0x01)
760 /*
761 * R4: RX antenna control
762 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
763 */
765 /*
766 * ANTENNA_CONTROL semantics (guessed):
767 * 0x1: Software controlled antenna switching (fixed or SW diversity)
768 * 0x2: Hardware diversity.
769 */
770 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
771 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
773 /*
774 * R77
775 */
776 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
778 /*
779 * RF registers
780 */
782 /*
783 * RF 3
784 */
785 #define RF3_TXPOWER FIELD32(0x00003e00)
787 /*
788 * RF 4
789 */
790 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
792 /*
793 * EEPROM content.
794 * The wordsize of the EEPROM is 16 bits.
795 */
797 /*
798 * HW MAC address.
799 */
800 #define EEPROM_MAC_ADDR_0 0x0002
801 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
802 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
803 #define EEPROM_MAC_ADDR1 0x0003
804 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
805 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
806 #define EEPROM_MAC_ADDR_2 0x0004
807 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
808 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
810 /*
811 * EEPROM antenna.
812 * ANTENNA_NUM: Number of antennas.
813 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
814 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
815 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
816 * DYN_TXAGC: Dynamic TX AGC control.
817 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
818 * RF_TYPE: Rf_type of this adapter.
819 */
820 #define EEPROM_ANTENNA 0x0010
821 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
822 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
823 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
824 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
825 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
826 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
827 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
829 /*
830 * EEPROM NIC config.
831 * EXTERNAL_LNA: External LNA.
832 */
833 #define EEPROM_NIC 0x0011
834 #define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)
836 /*
837 * EEPROM geography.
838 * GEO_A: Default geographical setting for 5GHz band
839 * GEO: Default geographical setting.
840 */
841 #define EEPROM_GEOGRAPHY 0x0012
842 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
843 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
845 /*
846 * EEPROM BBP.
847 */
848 #define EEPROM_BBP_START 0x0013
849 #define EEPROM_BBP_SIZE 16
850 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
851 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
853 /*
854 * EEPROM TXPOWER 802.11G
855 */
856 #define EEPROM_TXPOWER_G_START 0x0023
857 #define EEPROM_TXPOWER_G_SIZE 7
858 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
859 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
861 /*
862 * EEPROM Frequency
863 */
864 #define EEPROM_FREQ 0x002f
865 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
866 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
867 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
869 /*
870 * EEPROM LED.
871 * POLARITY_RDY_G: Polarity RDY_G setting.
872 * POLARITY_RDY_A: Polarity RDY_A setting.
873 * POLARITY_ACT: Polarity ACT setting.
874 * POLARITY_GPIO_0: Polarity GPIO0 setting.
875 * POLARITY_GPIO_1: Polarity GPIO1 setting.
876 * POLARITY_GPIO_2: Polarity GPIO2 setting.
877 * POLARITY_GPIO_3: Polarity GPIO3 setting.
878 * POLARITY_GPIO_4: Polarity GPIO4 setting.
879 * LED_MODE: Led mode.
880 */
881 #define EEPROM_LED 0x0030
882 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
883 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
884 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
885 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
886 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
887 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
888 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
889 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
890 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
892 /*
893 * EEPROM TXPOWER 802.11A
894 */
895 #define EEPROM_TXPOWER_A_START 0x0031
896 #define EEPROM_TXPOWER_A_SIZE 12
897 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
898 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
900 /*
901 * EEPROM RSSI offset 802.11BG
902 */
903 #define EEPROM_RSSI_OFFSET_BG 0x004d
904 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
905 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
907 /*
908 * EEPROM RSSI offset 802.11A
909 */
910 #define EEPROM_RSSI_OFFSET_A 0x004e
911 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
912 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
914 /*
915 * DMA descriptor defines.
916 */
917 #define TXD_DESC_SIZE ( 6 * sizeof(__le32) )
918 #define TXINFO_SIZE ( 6 * sizeof(__le32) )
919 #define RXD_DESC_SIZE ( 6 * sizeof(__le32) )
921 /*
922 * TX descriptor format for TX, PRIO and Beacon Ring.
923 */
925 /*
926 * Word0
927 * BURST: Next frame belongs to same "burst" event.
928 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
929 * KEY_TABLE: Use per-client pairwise KEY table.
930 * KEY_INDEX:
931 * Key index (0~31) to the pairwise KEY table.
932 * 0~3 to shared KEY table 0 (BSS0).
933 * 4~7 to shared KEY table 1 (BSS1).
934 * 8~11 to shared KEY table 2 (BSS2).
935 * 12~15 to shared KEY table 3 (BSS3).
936 * BURST2: For backward compatibility, set to same value as BURST.
937 */
938 #define TXD_W0_BURST FIELD32(0x00000001)
939 #define TXD_W0_VALID FIELD32(0x00000002)
940 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
941 #define TXD_W0_ACK FIELD32(0x00000008)
942 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
943 #define TXD_W0_OFDM FIELD32(0x00000020)
944 #define TXD_W0_IFS FIELD32(0x00000040)
945 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
946 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
947 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
948 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
949 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
950 #define TXD_W0_BURST2 FIELD32(0x10000000)
951 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
953 /*
954 * Word1
955 * HOST_Q_ID: EDCA/HCCA queue ID.
956 * HW_SEQUENCE: MAC overwrites the frame sequence number.
957 * BUFFER_COUNT: Number of buffers in this TXD.
958 */
959 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
960 #define TXD_W1_AIFSN FIELD32(0x000000f0)
961 #define TXD_W1_CWMIN FIELD32(0x00000f00)
962 #define TXD_W1_CWMAX FIELD32(0x0000f000)
963 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
964 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
965 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
967 /*
968 * Word2: PLCP information
969 */
970 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
971 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
972 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
973 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
975 /*
976 * Word3
977 */
978 #define TXD_W3_IV FIELD32(0xffffffff)
980 /*
981 * Word4
982 */
983 #define TXD_W4_EIV FIELD32(0xffffffff)
985 /*
986 * Word5
987 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
988 * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
989 * WAITING_DMA_DONE_INT: TXD been filled with data
990 * and waiting for TxDoneISR housekeeping.
991 */
992 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
993 #define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
994 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
995 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
997 /*
998 * RX descriptor format for RX Ring.
999 */
1001 /*
1002 * Word0
1003 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1004 * KEY_INDEX: Decryption key actually used.
1005 */
1006 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1007 #define RXD_W0_DROP FIELD32(0x00000002)
1008 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1009 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1010 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1011 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1012 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1013 #define RXD_W0_OFDM FIELD32(0x00000080)
1014 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1015 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1016 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1017 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1019 /*
1020 * WORD1
1021 * SIGNAL: RX raw data rate reported by BBP.
1022 * RSSI: RSSI reported by BBP.
1023 */
1024 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1025 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1026 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1027 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1029 /*
1030 * Word2
1031 * IV: Received IV of originally encrypted.
1032 */
1033 #define RXD_W2_IV FIELD32(0xffffffff)
1035 /*
1036 * Word3
1037 * EIV: Received EIV of originally encrypted.
1038 */
1039 #define RXD_W3_EIV FIELD32(0xffffffff)
1041 /*
1042 * Word4
1043 * ICV: Received ICV of originally encrypted.
1044 * NOTE: This is a guess, the official definition is "reserved"
1045 */
1046 #define RXD_W4_ICV FIELD32(0xffffffff)
1048 /*
1049 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1050 * and passed to the HOST driver.
1051 * The following fields are for DMA block and HOST usage only.
1052 * Can't be touched by ASIC MAC block.
1053 */
1055 /*
1056 * Word5
1057 */
1058 #define RXD_W5_RESERVED FIELD32(0xffffffff)
1060 /*
1061 * Macros for converting txpower from EEPROM to mac80211 value
1062 * and from mac80211 value to register value.
1063 */
1064 #define MIN_TXPOWER 0
1065 #define MAX_TXPOWER 31
1066 #define DEFAULT_TXPOWER 24
1068 #define TXPOWER_FROM_DEV(__txpower) \
1069 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1071 #define TXPOWER_TO_DEV(__txpower) \
1072 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)