drivers/net/mlx4/profile.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   4  * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #include "mlx4.h"
  36 #include "fw.h"
  37
  38 enum {
  39         MLX4_RES_QP,
  40         MLX4_RES_RDMARC,
  41         MLX4_RES_ALTC,
  42         MLX4_RES_AUXC,
  43         MLX4_RES_SRQ,
  44         MLX4_RES_CQ,
  45         MLX4_RES_EQ,
  46         MLX4_RES_DMPT,
  47         MLX4_RES_CMPT,
  48         MLX4_RES_MTT,
  49         MLX4_RES_MCG,
  50         MLX4_RES_NUM
  51 };
  52
  53 static const char *res_name[] = {
  54         [MLX4_RES_QP]           = "QP",
  55         [MLX4_RES_RDMARC]       = "RDMARC",
  56         [MLX4_RES_ALTC]         = "ALTC",
  57         [MLX4_RES_AUXC]         = "AUXC",
  58         [MLX4_RES_SRQ]          = "SRQ",
  59         [MLX4_RES_CQ]           = "CQ",
  60         [MLX4_RES_EQ]           = "EQ",
  61         [MLX4_RES_DMPT]         = "DMPT",
  62         [MLX4_RES_CMPT]         = "CMPT",
  63         [MLX4_RES_MTT]          = "MTT",
  64         [MLX4_RES_MCG]          = "MCG",
  65 };
  66
  67 u64 mlx4_make_profile(struct mlx4_dev *dev,
  68                       struct mlx4_profile *request,
  69                       struct mlx4_dev_cap *dev_cap,
  70                       struct mlx4_init_hca_param *init_hca)
  71 {
  72         struct mlx4_priv *priv = mlx4_priv(dev);
  73         struct mlx4_resource {
  74                 u64 size;
  75                 u64 start;
  76                 int type;
  77                 int num;
  78                 int log_num;
  79         };
  80
  81         u64 total_size = 0;
  82         struct mlx4_resource *profile;
  83         struct mlx4_resource tmp;
  84         int i, j;
  85
  86         profile = kzalloc(MLX4_RES_NUM * sizeof *profile, GFP_KERNEL);
  87         if (!profile)
  88                 return -ENOMEM;
  89
  90         profile[MLX4_RES_QP].size     = dev_cap->qpc_entry_sz;
  91         profile[MLX4_RES_RDMARC].size = dev_cap->rdmarc_entry_sz;
  92         profile[MLX4_RES_ALTC].size   = dev_cap->altc_entry_sz;
  93         profile[MLX4_RES_AUXC].size   = dev_cap->aux_entry_sz;
  94         profile[MLX4_RES_SRQ].size    = dev_cap->srq_entry_sz;
  95         profile[MLX4_RES_CQ].size     = dev_cap->cqc_entry_sz;
  96         profile[MLX4_RES_EQ].size     = dev_cap->eqc_entry_sz;
  97         profile[MLX4_RES_DMPT].size   = dev_cap->dmpt_entry_sz;
  98         profile[MLX4_RES_CMPT].size   = dev_cap->cmpt_entry_sz;
  99         profile[MLX4_RES_MTT].size    = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
 100         profile[MLX4_RES_MCG].size    = MLX4_MGM_ENTRY_SIZE;
 101
 102         profile[MLX4_RES_QP].num      = request->num_qp;
 103         profile[MLX4_RES_RDMARC].num  = request->num_qp * request->rdmarc_per_qp;
 104         profile[MLX4_RES_ALTC].num    = request->num_qp;
 105         profile[MLX4_RES_AUXC].num    = request->num_qp;
 106         profile[MLX4_RES_SRQ].num     = request->num_srq;
 107         profile[MLX4_RES_CQ].num      = request->num_cq;
 108         profile[MLX4_RES_EQ].num      = min_t(unsigned, dev_cap->max_eqs,
 109                                               dev_cap->reserved_eqs +
 110                                               num_possible_cpus() + 1);
 111         profile[MLX4_RES_DMPT].num    = request->num_mpt;
 112         profile[MLX4_RES_CMPT].num    = MLX4_NUM_CMPTS;
 113         profile[MLX4_RES_MTT].num     = request->num_mtt;
 114         profile[MLX4_RES_MCG].num     = request->num_mcg;
 115
 116         for (i = 0; i < MLX4_RES_NUM; ++i) {
 117                 profile[i].type     = i;
 118                 profile[i].num      = roundup_pow_of_two(profile[i].num);
 119                 profile[i].log_num  = ilog2(profile[i].num);
 120                 profile[i].size    *= profile[i].num;
 121                 profile[i].size     = max(profile[i].size, (u64) PAGE_SIZE);
 122         }
 123
 124         /*
 125          * Sort the resources in decreasing order of size.  Since they
 126          * all have sizes that are powers of 2, we'll be able to keep
 127          * resources aligned to their size and pack them without gaps
 128          * using the sorted order.
 129          */
 130         for (i = MLX4_RES_NUM; i > 0; --i)
 131                 for (j = 1; j < i; ++j) {
 132                         if (profile[j].size > profile[j - 1].size) {
 133                                 tmp            = profile[j];
 134                                 profile[j]     = profile[j - 1];
 135                                 profile[j - 1] = tmp;
 136                         }
 137                 }
 138
 139         for (i = 0; i < MLX4_RES_NUM; ++i) {
 140                 if (profile[i].size) {
 141                         profile[i].start = total_size;
 142                         total_size      += profile[i].size;
 143                 }
 144
 145                 if (total_size > dev_cap->max_icm_sz) {
 146                         mlx4_err(dev, "Profile requires 0x%llx bytes; "
 147                                   "won't fit in 0x%llx bytes of context memory.\n",
 148                                   (unsigned long long) total_size,
 149                                   (unsigned long long) dev_cap->max_icm_sz);
 150                         kfree(profile);
 151                         return -ENOMEM;
 152                 }
 153
 154                 if (profile[i].size)
 155                         mlx4_dbg(dev, "  profile[%2d] (%6s): 2^%02d entries @ 0x%10llx, "
 156                                   "size 0x%10llx\n",
 157                                  i, res_name[profile[i].type], profile[i].log_num,
 158                                  (unsigned long long) profile[i].start,
 159                                  (unsigned long long) profile[i].size);
 160         }
 161
 162         mlx4_dbg(dev, "HCA context memory: reserving %d KB\n",
 163                  (int) (total_size >> 10));
 164
 165         for (i = 0; i < MLX4_RES_NUM; ++i) {
 166                 switch (profile[i].type) {
 167                 case MLX4_RES_QP:
 168                         dev->caps.num_qps     = profile[i].num;
 169                         init_hca->qpc_base    = profile[i].start;
 170                         init_hca->log_num_qps = profile[i].log_num;
 171                         break;
 172                 case MLX4_RES_RDMARC:
 173                         for (priv->qp_table.rdmarc_shift = 0;
 174                              request->num_qp << priv->qp_table.rdmarc_shift < profile[i].num;
 175                              ++priv->qp_table.rdmarc_shift)
 176                                 ; /* nothing */
 177                         dev->caps.max_qp_dest_rdma = 1 << priv->qp_table.rdmarc_shift;
 178                         priv->qp_table.rdmarc_base   = (u32) profile[i].start;
 179                         init_hca->rdmarc_base        = profile[i].start;
 180                         init_hca->log_rd_per_qp      = priv->qp_table.rdmarc_shift;
 181                         break;
 182                 case MLX4_RES_ALTC:
 183                         init_hca->altc_base = profile[i].start;
 184                         break;
 185                 case MLX4_RES_AUXC:
 186                         init_hca->auxc_base = profile[i].start;
 187                         break;
 188                 case MLX4_RES_SRQ:
 189                         dev->caps.num_srqs     = profile[i].num;
 190                         init_hca->srqc_base    = profile[i].start;
 191                         init_hca->log_num_srqs = profile[i].log_num;
 192                         break;
 193                 case MLX4_RES_CQ:
 194                         dev->caps.num_cqs     = profile[i].num;
 195                         init_hca->cqc_base    = profile[i].start;
 196                         init_hca->log_num_cqs = profile[i].log_num;
 197                         break;
 198                 case MLX4_RES_EQ:
 199                         dev->caps.num_eqs     = profile[i].num;
 200                         init_hca->eqc_base    = profile[i].start;
 201                         init_hca->log_num_eqs = profile[i].log_num;
 202                         break;
 203                 case MLX4_RES_DMPT:
 204                         dev->caps.num_mpts      = profile[i].num;
 205                         priv->mr_table.mpt_base = profile[i].start;
 206                         init_hca->dmpt_base     = profile[i].start;
 207                         init_hca->log_mpt_sz    = profile[i].log_num;
 208                         break;
 209                 case MLX4_RES_CMPT:
 210                         init_hca->cmpt_base      = profile[i].start;
 211                         break;
 212                 case MLX4_RES_MTT:
 213                         dev->caps.num_mtt_segs   = profile[i].num;
 214                         priv->mr_table.mtt_base  = profile[i].start;
 215                         init_hca->mtt_base       = profile[i].start;
 216                         break;
 217                 case MLX4_RES_MCG:
 218                         dev->caps.num_mgms        = profile[i].num >> 1;
 219                         dev->caps.num_amgms       = profile[i].num >> 1;
 220                         init_hca->mc_base         = profile[i].start;
 221                         init_hca->log_mc_entry_sz = ilog2(MLX4_MGM_ENTRY_SIZE);
 222                         init_hca->log_mc_table_sz = profile[i].log_num;
 223                         init_hca->log_mc_hash_sz  = profile[i].log_num - 1;
 224                         break;
 225                 default:
 226                         break;
 227                 }
 228         }
 229
 230         /*
 231          * PDs don't take any HCA memory, but we assign them as part
 232          * of the HCA profile anyway.
 233          */
 234         dev->caps.num_pds = MLX4_NUM_PDS;
 235
 236         kfree(profile);
 237         return total_size;
 238 }