arch/blackfin/mach-bf518/include/mach/defBF514.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf518/defBF514.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Rev:
  10  *
  11  * Modified:
  12  *
  13  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2, or (at your option)
  18  * any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; see the file COPYING.
  27  * If not, write to the Free Software Foundation,
  28  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  29  */
  30
  31 #ifndef _DEF_BF514_H
  32 #define _DEF_BF514_H
  33
  34 /* Include all Core registers and bit definitions */
  35 #include <asm/def_LPBlackfin.h>
  36
  37 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
  38
  39 /* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
  40 #include "defBF51x_base.h"
  41
  42 /* The following are the #defines needed by ADSP-BF514 that are not in the common header */
  43
  44 /* SDH Registers */
  45
  46 #define SDH_PWR_CTL                    0xFFC03900 /* SDH Power Control */
  47 #define SDH_CLK_CTL                    0xFFC03904 /* SDH Clock Control */
  48 #define SDH_ARGUMENT                   0xFFC03908 /* SDH Argument */
  49 #define SDH_COMMAND                    0xFFC0390C /* SDH Command */
  50 #define SDH_RESP_CMD                   0xFFC03910 /* SDH Response Command */
  51 #define SDH_RESPONSE0                  0xFFC03914 /* SDH Response0 */
  52 #define SDH_RESPONSE1                  0xFFC03918 /* SDH Response1 */
  53 #define SDH_RESPONSE2                  0xFFC0391C /* SDH Response2 */
  54 #define SDH_RESPONSE3                  0xFFC03920 /* SDH Response3 */
  55 #define SDH_DATA_TIMER                 0xFFC03924 /* SDH Data Timer */
  56 #define SDH_DATA_LGTH                  0xFFC03928 /* SDH Data Length */
  57 #define SDH_DATA_CTL                   0xFFC0392C /* SDH Data Control */
  58 #define SDH_DATA_CNT                   0xFFC03930 /* SDH Data Counter */
  59 #define SDH_STATUS                     0xFFC03934 /* SDH Status */
  60 #define SDH_STATUS_CLR                 0xFFC03938 /* SDH Status Clear */
  61 #define SDH_MASK0                      0xFFC0393C /* SDH Interrupt0 Mask */
  62 #define SDH_MASK1                      0xFFC03940 /* SDH Interrupt1 Mask */
  63 #define SDH_FIFO_CNT                   0xFFC03948 /* SDH FIFO Counter */
  64 #define SDH_FIFO                       0xFFC03980 /* SDH Data FIFO */
  65 #define SDH_E_STATUS                   0xFFC039C0 /* SDH Exception Status */
  66 #define SDH_E_MASK                     0xFFC039C4 /* SDH Exception Mask */
  67 #define SDH_CFG                        0xFFC039C8 /* SDH Configuration */
  68 #define SDH_RD_WAIT_EN                 0xFFC039CC /* SDH Read Wait Enable */
  69 #define SDH_PID0                       0xFFC039D0 /* SDH Peripheral Identification0 */
  70 #define SDH_PID1                       0xFFC039D4 /* SDH Peripheral Identification1 */
  71 #define SDH_PID2                       0xFFC039D8 /* SDH Peripheral Identification2 */
  72 #define SDH_PID3                       0xFFC039DC /* SDH Peripheral Identification3 */
  73 #define SDH_PID4                       0xFFC039E0 /* SDH Peripheral Identification4 */
  74 #define SDH_PID5                       0xFFC039E4 /* SDH Peripheral Identification5 */
  75 #define SDH_PID6                       0xFFC039E8 /* SDH Peripheral Identification6 */
  76 #define SDH_PID7                       0xFFC039EC /* SDH Peripheral Identification7 */
  77
  78 /* Removable Storage Interface Registers */
  79
  80 #define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
  81 #define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
  82 #define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
  83 #define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
  84 #define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
  85 #define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
  86 #define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
  87 #define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
  88 #define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
  89 #define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
  90 #define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
  91 #define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
  92 #define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
  93 #define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
  94 #define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
  95 #define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
  96 #define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
  97 #define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
  98 #define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
  99 #define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
 100 #define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
 101 #define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
 102 #define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
 103 #define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
 104 #define RSI_PID0                       0xFFC03FE0 /* RSI Peripheral ID Register 0 */
 105 #define RSI_PID1                       0xFFC03FE4 /* RSI Peripheral ID Register 1 */
 106 #define RSI_PID2                       0xFFC03FE8 /* RSI Peripheral ID Register 2 */
 107 #define RSI_PID3                       0xFFC03FEC /* RSI Peripheral ID Register 3 */
 108 #define RSI_PID4                       0xFFC03FF0 /* RSI Peripheral ID Register 4 */
 109 #define RSI_PID5                       0xFFC03FF4 /* RSI Peripheral ID Register 5 */
 110 #define RSI_PID6                       0xFFC03FF8 /* RSI Peripheral ID Register 6 */
 111 #define RSI_PID7                       0xFFC03FFC /* RSI Peripheral ID Register 7 */
 112
 113 /* ********************************************************** */
 114 /*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
 115 /*     and MULTI BIT READ MACROS                              */
 116 /* ********************************************************** */
 117
 118 /* Bit masks for SDH_COMMAND */
 119
 120 #define                   CMD_IDX  0x3f       /* Command Index */
 121 #define                   CMD_RSP  0x40       /* Response */
 122 #define                 CMD_L_RSP  0x80       /* Long Response */
 123 #define                 CMD_INT_E  0x100      /* Command Interrupt */
 124 #define                CMD_PEND_E  0x200      /* Command Pending */
 125 #define                     CMD_E  0x400      /* Command Enable */
 126
 127 /* Bit masks for SDH_PWR_CTL */
 128
 129 #define                    PWR_ON  0x3        /* Power On */
 130 #if 0
 131 #define                       TBD  0x3c       /* TBD */
 132 #endif
 133 #define                 SD_CMD_OD  0x40       /* Open Drain Output */
 134 #define                   ROD_CTL  0x80       /* Rod Control */
 135
 136 /* Bit masks for SDH_CLK_CTL */
 137
 138 #define                    CLKDIV  0xff       /* MC_CLK Divisor */
 139 #define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
 140 #define                  PWR_SV_E  0x200      /* Power Save Enable */
 141 #define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
 142 #define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
 143
 144 /* Bit masks for SDH_RESP_CMD */
 145
 146 #define                  RESP_CMD  0x3f       /* Response Command */
 147
 148 /* Bit masks for SDH_DATA_CTL */
 149
 150 #define                     DTX_E  0x1        /* Data Transfer Enable */
 151 #define                   DTX_DIR  0x2        /* Data Transfer Direction */
 152 #define                  DTX_MODE  0x4        /* Data Transfer Mode */
 153 #define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
 154 #define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
 155
 156 /* Bit masks for SDH_STATUS */
 157
 158 #define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
 159 #define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
 160 #define               CMD_TIME_OUT  0x4        /* CMD Time Out */
 161 #define               DAT_TIME_OUT  0x8        /* Data Time Out */
 162 #define               TX_UNDERRUN  0x10       /* Transmit Underrun */
 163 #define                RX_OVERRUN  0x20       /* Receive Overrun */
 164 #define              CMD_RESP_END  0x40       /* CMD Response End */
 165 #define                  CMD_SENT  0x80       /* CMD Sent */
 166 #define                   DAT_END  0x100      /* Data End */
 167 #define             START_BIT_ERR  0x200      /* Start Bit Error */
 168 #define               DAT_BLK_END  0x400      /* Data Block End */
 169 #define                   CMD_ACT  0x800      /* CMD Active */
 170 #define                    TX_ACT  0x1000     /* Transmit Active */
 171 #define                    RX_ACT  0x2000     /* Receive Active */
 172 #define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
 173 #define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
 174 #define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
 175 #define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
 176 #define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
 177 #define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
 178 #define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
 179 #define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
 180
 181 /* Bit masks for SDH_STATUS_CLR */
 182
 183 #define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
 184 #define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
 185 #define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
 186 #define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
 187 #define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
 188 #define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
 189 #define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
 190 #define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
 191 #define              DAT_END_STAT  0x100      /* Data End Status */
 192 #define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
 193 #define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
 194
 195 /* Bit masks for SDH_MASK0 */
 196
 197 #define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
 198 #define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
 199 #define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
 200 #define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
 201 #define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
 202 #define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
 203 #define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
 204 #define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
 205 #define              DAT_END_MASK  0x100      /* Data End Mask */
 206 #define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
 207 #define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
 208 #define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
 209 #define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
 210 #define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
 211 #define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
 212 #define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
 213 #define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
 214 #define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
 215 #define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
 216 #define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
 217 #define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
 218 #define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
 219
 220 /* Bit masks for SDH_FIFO_CNT */
 221
 222 #define                FIFO_COUNT  0x7fff     /* FIFO Count */
 223
 224 /* Bit masks for SDH_E_STATUS */
 225
 226 #define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
 227 #define               SD_CARD_DET  0x10       /* SD Card Detect */
 228
 229 /* Bit masks for SDH_E_MASK */
 230
 231 #define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
 232 #define                   SCD_MSK  0x40       /* Mask Card Detect */
 233
 234 /* Bit masks for SDH_CFG */
 235
 236 #define                   CLKS_EN  0x1        /* Clocks Enable */
 237 #define                      SD4E  0x4        /* SDIO 4-Bit Enable */
 238 #define                       MWE  0x8        /* Moving Window Enable */
 239 #define                    SD_RST  0x10       /* SDMMC Reset */
 240 #define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
 241 #define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
 242 #define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
 243
 244 /* Bit masks for SDH_RD_WAIT_EN */
 245
 246 #define                       RWR  0x1        /* Read Wait Request */
 247
 248 #endif /* _DEF_BF514_H */