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PSP-03.00.00.03
[linux-ginger.git] / arch / arm / plat-omap / mcbsp.c
blob776a92a3c09e08d0deea1f9317f567f1bfaa19ea
1 /*
2 * linux/arch/arm/plat-omap/mcbsp.c
3 *
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Multichannel mode not supported.
13 */
14
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
25 #include <linux/io.h>
26
27 #include <plat/dma.h>
28 #include <plat/mcbsp.h>
29
30 struct omap_mcbsp **mcbsp_ptr;
31 int omap_mcbsp_count;
32
33 void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
34 {
35 if (cpu_class_is_omap1() || cpu_is_omap2420())
36 __raw_writew((u16)val, io_base + reg);
37 else
38 __raw_writel(val, io_base + reg);
39 }
40
41 int omap_mcbsp_read(void __iomem *io_base, u16 reg)
42 {
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(io_base + reg);
45 else
46 return __raw_readl(io_base + reg);
47 }
48
49 #define OMAP_MCBSP_READ(base, reg) \
50 omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
51 #define OMAP_MCBSP_WRITE(base, reg, val) \
52 omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
53
54 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
56
57 static void omap_mcbsp_dump_reg(u8 id)
58 {
59 struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
60
61 dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
62 dev_dbg(mcbsp->dev, "DRR2: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
64 dev_dbg(mcbsp->dev, "DRR1: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
66 dev_dbg(mcbsp->dev, "DXR2: 0x%04x\n",
67 OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
68 dev_dbg(mcbsp->dev, "DXR1: 0x%04x\n",
69 OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
70 dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
71 OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
72 dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
73 OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
74 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n",
75 OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
76 dev_dbg(mcbsp->dev, "RCR1: 0x%04x\n",
77 OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
78 dev_dbg(mcbsp->dev, "XCR2: 0x%04x\n",
79 OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
80 dev_dbg(mcbsp->dev, "XCR1: 0x%04x\n",
81 OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
82 dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
83 OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
84 dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
85 OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
86 dev_dbg(mcbsp->dev, "PCR0: 0x%04x\n",
87 OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
88 dev_dbg(mcbsp->dev, "***********************\n");
89 }
90
91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
92 {
93 struct omap_mcbsp *mcbsp_tx = dev_id;
94 u16 irqst_spcr2;
95
96 irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
97 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
98
99 if (irqst_spcr2 & XSYNC_ERR) {
100 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
101 irqst_spcr2);
102 /* Writing zero to XSYNC_ERR clears the IRQ */
103 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
104 irqst_spcr2 & ~(XSYNC_ERR));
105 } else {
106 complete(&mcbsp_tx->tx_irq_completion);
107 }
108
109 return IRQ_HANDLED;
110 }
111
112 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
113 {
114 struct omap_mcbsp *mcbsp_rx = dev_id;
115 u16 irqst_spcr1;
116
117 irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
118 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
119
120 if (irqst_spcr1 & RSYNC_ERR) {
121 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
122 irqst_spcr1);
123 /* Writing zero to RSYNC_ERR clears the IRQ */
124 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
125 irqst_spcr1 & ~(RSYNC_ERR));
126 } else {
127 complete(&mcbsp_rx->tx_irq_completion);
128 }
129
130 return IRQ_HANDLED;
131 }
132
133 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
134 {
135 struct omap_mcbsp *mcbsp_dma_tx = data;
136
137 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
138 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
139
140 /* We can free the channels */
141 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
142 mcbsp_dma_tx->dma_tx_lch = -1;
143
144 complete(&mcbsp_dma_tx->tx_dma_completion);
145 }
146
147 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
148 {
149 struct omap_mcbsp *mcbsp_dma_rx = data;
150
151 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
152 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
153
154 /* We can free the channels */
155 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
156 mcbsp_dma_rx->dma_rx_lch = -1;
157
158 complete(&mcbsp_dma_rx->rx_dma_completion);
159 }
160
161 /*
162 * omap_mcbsp_config simply write a config to the
163 * appropriate McBSP.
164 * You either call this function or set the McBSP registers
165 * by yourself before calling omap_mcbsp_start().
166 */
167 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
168 {
169 struct omap_mcbsp *mcbsp;
170 void __iomem *io_base;
171
172 if (!omap_mcbsp_check_valid_id(id)) {
173 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
174 return;
175 }
176 mcbsp = id_to_mcbsp_ptr(id);
177
178 io_base = mcbsp->io_base;
179 dev_dbg(mcbsp->dev, "Configuring McBSP%d phys_base: 0x%08lx\n",
180 mcbsp->id, mcbsp->phys_base);
181
182 /* We write the given config */
183 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
184 OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
185 OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
186 OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
187 OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
188 OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
189 OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
190 OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
191 OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
192 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
193 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
194 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
195 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
196 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
197 }
198 }
199 EXPORT_SYMBOL(omap_mcbsp_config);
200
201 #ifdef CONFIG_ARCH_OMAP34XX
202 /*
203 * omap_mcbsp_set_tx_threshold configures how to deal
204 * with transmit threshold. the threshold value and handler can be
205 * configure in here.
206 */
207 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
208 {
209 struct omap_mcbsp *mcbsp;
210 void __iomem *io_base;
211
212 if (!cpu_is_omap34xx())
213 return;
214
215 if (!omap_mcbsp_check_valid_id(id)) {
216 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
217 return;
218 }
219 mcbsp = id_to_mcbsp_ptr(id);
220 io_base = mcbsp->io_base;
221
222 OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
223 }
224 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
225
226 /*
227 * omap_mcbsp_set_rx_threshold configures how to deal
228 * with receive threshold. the threshold value and handler can be
229 * configure in here.
230 */
231 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
232 {
233 struct omap_mcbsp *mcbsp;
234 void __iomem *io_base;
235
236 if (!cpu_is_omap34xx())
237 return;
238
239 if (!omap_mcbsp_check_valid_id(id)) {
240 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
241 return;
242 }
243 mcbsp = id_to_mcbsp_ptr(id);
244 io_base = mcbsp->io_base;
245
246 OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
247 }
248 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
249
250 /*
251 * omap_mcbsp_get_max_tx_thres just return the current configured
252 * maximum threshold for transmission
253 */
254 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
255 {
256 struct omap_mcbsp *mcbsp;
257
258 if (!omap_mcbsp_check_valid_id(id)) {
259 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
260 return -ENODEV;
261 }
262 mcbsp = id_to_mcbsp_ptr(id);
263
264 return mcbsp->max_tx_thres;
265 }
266 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
267
268 /*
269 * omap_mcbsp_get_max_rx_thres just return the current configured
270 * maximum threshold for reception
271 */
272 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
273 {
274 struct omap_mcbsp *mcbsp;
275
276 if (!omap_mcbsp_check_valid_id(id)) {
277 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
278 return -ENODEV;
279 }
280 mcbsp = id_to_mcbsp_ptr(id);
281
282 return mcbsp->max_rx_thres;
283 }
284 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
285
286 /*
287 * omap_mcbsp_get_dma_op_mode just return the current configured
288 * operating mode for the mcbsp channel
289 */
290 int omap_mcbsp_get_dma_op_mode(unsigned int id)
291 {
292 struct omap_mcbsp *mcbsp;
293 int dma_op_mode;
294
295 if (!omap_mcbsp_check_valid_id(id)) {
296 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
297 return -ENODEV;
298 }
299 mcbsp = id_to_mcbsp_ptr(id);
300
301 spin_lock_irq(&mcbsp->lock);
302 dma_op_mode = mcbsp->dma_op_mode;
303 spin_unlock_irq(&mcbsp->lock);
304
305 return dma_op_mode;
306 }
307 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
308
309 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
310 {
311 /*
312 * Enable wakup behavior, smart idle and all wakeups
313 * REVISIT: some wakeups may be unnecessary
314 */
315 if (cpu_is_omap34xx()) {
316 u16 syscon;
317
318 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
319 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
320
321 spin_lock_irq(&mcbsp->lock);
322 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
323 syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
324 CLOCKACTIVITY(0x02));
325 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
326 XRDYEN | RRDYEN);
327 } else {
328 syscon |= SIDLEMODE(0x01);
329 }
330 spin_unlock_irq(&mcbsp->lock);
331
332 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
333 }
334 }
335
336 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
337 {
338 /*
339 * Disable wakup behavior, smart idle and all wakeups
340 */
341 if (cpu_is_omap34xx()) {
342 u16 syscon;
343
344 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
345 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
346 /*
347 * HW bug workaround - If no_idle mode is taken, we need to
348 * go to smart_idle before going to always_idle, or the
349 * device will not hit retention anymore.
350 */
351 syscon |= SIDLEMODE(0x02);
352 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
353
354 syscon &= ~(SIDLEMODE(0x03));
355 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
356
357 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
358 }
359 }
360 #else
361 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
362 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
363 #endif
364
365 /*
366 * We can choose between IRQ based or polled IO.
367 * This needs to be called before omap_mcbsp_request().
368 */
369 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
370 {
371 struct omap_mcbsp *mcbsp;
372
373 if (!omap_mcbsp_check_valid_id(id)) {
374 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
375 return -ENODEV;
376 }
377 mcbsp = id_to_mcbsp_ptr(id);
378
379 spin_lock(&mcbsp->lock);
380
381 if (!mcbsp->free) {
382 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
383 mcbsp->id);
384 spin_unlock(&mcbsp->lock);
385 return -EINVAL;
386 }
387
388 mcbsp->io_type = io_type;
389
390 spin_unlock(&mcbsp->lock);
391
392 return 0;
393 }
394 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
395
396 int omap_mcbsp_request(unsigned int id)
397 {
398 struct omap_mcbsp *mcbsp;
399 int err;
400
401 if (!omap_mcbsp_check_valid_id(id)) {
402 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
403 return -ENODEV;
404 }
405 mcbsp = id_to_mcbsp_ptr(id);
406
407 spin_lock(&mcbsp->lock);
408 if (!mcbsp->free) {
409 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
410 mcbsp->id);
411 spin_unlock(&mcbsp->lock);
412 return -EBUSY;
413 }
414
415 mcbsp->free = 0;
416 spin_unlock(&mcbsp->lock);
417
418 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
419 mcbsp->pdata->ops->request(id);
420
421 clk_enable(mcbsp->iclk);
422 clk_enable(mcbsp->fclk);
423
424 /* Do procedure specific to omap34xx arch, if applicable */
425 omap34xx_mcbsp_request(mcbsp);
426
427 /*
428 * Make sure that transmitter, receiver and sample-rate generator are
429 * not running before activating IRQs.
430 */
431 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
432 OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
433
434 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
435 /* We need to get IRQs here */
436 init_completion(&mcbsp->tx_irq_completion);
437 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
438 0, "McBSP", (void *)mcbsp);
439 if (err != 0) {
440 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
441 "for McBSP%d\n", mcbsp->tx_irq,
442 mcbsp->id);
443 return err;
444 }
445
446 init_completion(&mcbsp->rx_irq_completion);
447 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
448 0, "McBSP", (void *)mcbsp);
449 if (err != 0) {
450 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
451 "for McBSP%d\n", mcbsp->rx_irq,
452 mcbsp->id);
453 free_irq(mcbsp->tx_irq, (void *)mcbsp);
454 return err;
455 }
456 }
457
458 return 0;
459 }
460 EXPORT_SYMBOL(omap_mcbsp_request);
461
462 void omap_mcbsp_disable_clks(unsigned int id)
463 {
464 struct omap_mcbsp *mcbsp;
465
466 if (!omap_mcbsp_check_valid_id(id)) {
467 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
468 return;
469 }
470 mcbsp = id_to_mcbsp_ptr(id);
471 clk_disable(mcbsp->fclk);
472 clk_disable(mcbsp->iclk);
473 }
474 EXPORT_SYMBOL(omap_mcbsp_disable_clks);
475
476
477 void omap_mcbsp_enable_clks(unsigned int id)
478 {
479 struct omap_mcbsp *mcbsp;
480
481 if (!omap_mcbsp_check_valid_id(id)) {
482 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
483 return;
484 }
485 mcbsp = id_to_mcbsp_ptr(id);
486 clk_enable(mcbsp->iclk);
487 clk_enable(mcbsp->fclk);
488 }
489 EXPORT_SYMBOL(omap_mcbsp_enable_clks);
490
491 void omap_mcbsp_free(unsigned int id)
492 {
493 struct omap_mcbsp *mcbsp;
494
495 if (!omap_mcbsp_check_valid_id(id)) {
496 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
497 return;
498 }
499 mcbsp = id_to_mcbsp_ptr(id);
500
501 if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
502 mcbsp->pdata->ops->free(id);
503
504 /* Do procedure specific to omap34xx arch, if applicable */
505 omap34xx_mcbsp_free(mcbsp);
506
507 clk_disable(mcbsp->fclk);
508 clk_disable(mcbsp->iclk);
509
510 if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
511 /* Free IRQs */
512 free_irq(mcbsp->rx_irq, (void *)mcbsp);
513 free_irq(mcbsp->tx_irq, (void *)mcbsp);
514 }
515
516 spin_lock(&mcbsp->lock);
517 if (mcbsp->free) {
518 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
519 mcbsp->id);
520 spin_unlock(&mcbsp->lock);
521 return;
522 }
523
524 mcbsp->free = 1;
525 spin_unlock(&mcbsp->lock);
526 }
527 EXPORT_SYMBOL(omap_mcbsp_free);
528
529 /*
530 * Here we start the McBSP, by enabling transmitter, receiver or both.
531 * If no transmitter or receiver is active prior calling, then sample-rate
532 * generator and frame sync are started.
533 */
534 void omap_mcbsp_start(unsigned int id, int tx, int rx)
535 {
536 struct omap_mcbsp *mcbsp;
537 void __iomem *io_base;
538 int idle;
539 u16 w;
540
541 if (!omap_mcbsp_check_valid_id(id)) {
542 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
543 return;
544 }
545 mcbsp = id_to_mcbsp_ptr(id);
546 io_base = mcbsp->io_base;
547
548 mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
549 mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
550
551 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
552 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
553
554 if (idle) {
555 /* Start the sample generator */
556 w = OMAP_MCBSP_READ(io_base, SPCR2);
557 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
558 }
559
560 /* Enable transmitter and receiver */
561 tx &= 1;
562 w = OMAP_MCBSP_READ(io_base, SPCR2);
563 OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx);
564
565 rx &= 1;
566 w = OMAP_MCBSP_READ(io_base, SPCR1);
567 OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx);
568
569 /*
570 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
571 * REVISIT: 100us may give enough time for two CLKSRG, however
572 * due to some unknown PM related, clock gating etc. reason it
573 * is now at 500us.
574 */
575 udelay(500);
576
577 if (idle) {
578 /* Start frame sync */
579 w = OMAP_MCBSP_READ(io_base, SPCR2);
580 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
581 }
582
583 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
584 /* Release the transmitter and receiver */
585 w = OMAP_MCBSP_READ(io_base, XCCR);
586 w &= ~(tx ? XDISABLE : 0);
587 OMAP_MCBSP_WRITE(io_base, XCCR, w);
588 w = OMAP_MCBSP_READ(io_base, RCCR);
589 w &= ~(rx ? RDISABLE : 0);
590 OMAP_MCBSP_WRITE(io_base, RCCR, w);
591 }
592
593 /* Dump McBSP Regs */
594 omap_mcbsp_dump_reg(id);
595 }
596 EXPORT_SYMBOL(omap_mcbsp_start);
597
598 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
599 {
600 struct omap_mcbsp *mcbsp;
601 void __iomem *io_base;
602 int idle;
603 u16 w;
604
605 if (!omap_mcbsp_check_valid_id(id)) {
606 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
607 return;
608 }
609
610 mcbsp = id_to_mcbsp_ptr(id);
611 io_base = mcbsp->io_base;
612
613 /* Reset transmitter */
614 tx &= 1;
615 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
616 w = OMAP_MCBSP_READ(io_base, XCCR);
617 w |= (tx ? XDISABLE : 0);
618 OMAP_MCBSP_WRITE(io_base, XCCR, w);
619 }
620 w = OMAP_MCBSP_READ(io_base, SPCR2);
621 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx);
622
623 /* Reset receiver */
624 rx &= 1;
625 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
626 w = OMAP_MCBSP_READ(io_base, RCCR);
627 w |= (rx ? RDISABLE : 0);
628 OMAP_MCBSP_WRITE(io_base, RCCR, w);
629 }
630 w = OMAP_MCBSP_READ(io_base, SPCR1);
631 OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx);
632
633 idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
634 OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
635
636 if (idle) {
637 /* Reset the sample rate generator */
638 w = OMAP_MCBSP_READ(io_base, SPCR2);
639 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
640 }
641 }
642 EXPORT_SYMBOL(omap_mcbsp_stop);
643
644 /* polled mcbsp i/o operations */
645 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
646 {
647 struct omap_mcbsp *mcbsp;
648 void __iomem *base;
649
650 if (!omap_mcbsp_check_valid_id(id)) {
651 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
652 return -ENODEV;
653 }
654
655 mcbsp = id_to_mcbsp_ptr(id);
656 base = mcbsp->io_base;
657
658 writew(buf, base + OMAP_MCBSP_REG_DXR1);
659 /* if frame sync error - clear the error */
660 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
661 /* clear error */
662 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
663 base + OMAP_MCBSP_REG_SPCR2);
664 /* resend */
665 return -1;
666 } else {
667 /* wait for transmit confirmation */
668 int attemps = 0;
669 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
670 if (attemps++ > 1000) {
671 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
672 (~XRST),
673 base + OMAP_MCBSP_REG_SPCR2);
674 udelay(10);
675 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
676 (XRST),
677 base + OMAP_MCBSP_REG_SPCR2);
678 udelay(10);
679 dev_err(mcbsp->dev, "Could not write to"
680 " McBSP%d Register\n", mcbsp->id);
681 return -2;
682 }
683 }
684 }
685
686 return 0;
687 }
688 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
689
690 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
691 {
692 struct omap_mcbsp *mcbsp;
693 void __iomem *base;
694
695 if (!omap_mcbsp_check_valid_id(id)) {
696 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
697 return -ENODEV;
698 }
699 mcbsp = id_to_mcbsp_ptr(id);
700
701 base = mcbsp->io_base;
702 /* if frame sync error - clear the error */
703 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
704 /* clear error */
705 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
706 base + OMAP_MCBSP_REG_SPCR1);
707 /* resend */
708 return -1;
709 } else {
710 /* wait for recieve confirmation */
711 int attemps = 0;
712 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
713 if (attemps++ > 1000) {
714 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
715 (~RRST),
716 base + OMAP_MCBSP_REG_SPCR1);
717 udelay(10);
718 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
719 (RRST),
720 base + OMAP_MCBSP_REG_SPCR1);
721 udelay(10);
722 dev_err(mcbsp->dev, "Could not read from"
723 " McBSP%d Register\n", mcbsp->id);
724 return -2;
725 }
726 }
727 }
728 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
729
730 return 0;
731 }
732 EXPORT_SYMBOL(omap_mcbsp_pollread);
733
734 /*
735 * IRQ based word transmission.
736 */
737 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
738 {
739 struct omap_mcbsp *mcbsp;
740 void __iomem *io_base;
741 omap_mcbsp_word_length word_length;
742
743 if (!omap_mcbsp_check_valid_id(id)) {
744 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
745 return;
746 }
747
748 mcbsp = id_to_mcbsp_ptr(id);
749 io_base = mcbsp->io_base;
750 word_length = mcbsp->tx_word_length;
751
752 wait_for_completion(&mcbsp->tx_irq_completion);
753
754 if (word_length > OMAP_MCBSP_WORD_16)
755 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
756 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
757 }
758 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
759
760 u32 omap_mcbsp_recv_word(unsigned int id)
761 {
762 struct omap_mcbsp *mcbsp;
763 void __iomem *io_base;
764 u16 word_lsb, word_msb = 0;
765 omap_mcbsp_word_length word_length;
766
767 if (!omap_mcbsp_check_valid_id(id)) {
768 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
769 return -ENODEV;
770 }
771 mcbsp = id_to_mcbsp_ptr(id);
772
773 word_length = mcbsp->rx_word_length;
774 io_base = mcbsp->io_base;
775
776 wait_for_completion(&mcbsp->rx_irq_completion);
777
778 if (word_length > OMAP_MCBSP_WORD_16)
779 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
780 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
781
782 return (word_lsb | (word_msb << 16));
783 }
784 EXPORT_SYMBOL(omap_mcbsp_recv_word);
785
786 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
787 {
788 struct omap_mcbsp *mcbsp;
789 void __iomem *io_base;
790 omap_mcbsp_word_length tx_word_length;
791 omap_mcbsp_word_length rx_word_length;
792 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
793
794 if (!omap_mcbsp_check_valid_id(id)) {
795 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
796 return -ENODEV;
797 }
798 mcbsp = id_to_mcbsp_ptr(id);
799 io_base = mcbsp->io_base;
800 tx_word_length = mcbsp->tx_word_length;
801 rx_word_length = mcbsp->rx_word_length;
802
803 if (tx_word_length != rx_word_length)
804 return -EINVAL;
805
806 /* First we wait for the transmitter to be ready */
807 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
808 while (!(spcr2 & XRDY)) {
809 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
810 if (attempts++ > 1000) {
811 /* We must reset the transmitter */
812 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
813 udelay(10);
814 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
815 udelay(10);
816 dev_err(mcbsp->dev, "McBSP%d transmitter not "
817 "ready\n", mcbsp->id);
818 return -EAGAIN;
819 }
820 }
821
822 /* Now we can push the data */
823 if (tx_word_length > OMAP_MCBSP_WORD_16)
824 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
825 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
826
827 /* We wait for the receiver to be ready */
828 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
829 while (!(spcr1 & RRDY)) {
830 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
831 if (attempts++ > 1000) {
832 /* We must reset the receiver */
833 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
834 udelay(10);
835 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
836 udelay(10);
837 dev_err(mcbsp->dev, "McBSP%d receiver not "
838 "ready\n", mcbsp->id);
839 return -EAGAIN;
840 }
841 }
842
843 /* Receiver is ready, let's read the dummy data */
844 if (rx_word_length > OMAP_MCBSP_WORD_16)
845 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
846 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
847
848 return 0;
849 }
850 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
851
852 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
853 {
854 struct omap_mcbsp *mcbsp;
855 u32 clock_word = 0;
856 void __iomem *io_base;
857 omap_mcbsp_word_length tx_word_length;
858 omap_mcbsp_word_length rx_word_length;
859 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
860
861 if (!omap_mcbsp_check_valid_id(id)) {
862 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
863 return -ENODEV;
864 }
865
866 mcbsp = id_to_mcbsp_ptr(id);
867 io_base = mcbsp->io_base;
868
869 tx_word_length = mcbsp->tx_word_length;
870 rx_word_length = mcbsp->rx_word_length;
871
872 if (tx_word_length != rx_word_length)
873 return -EINVAL;
874
875 /* First we wait for the transmitter to be ready */
876 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
877 while (!(spcr2 & XRDY)) {
878 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
879 if (attempts++ > 1000) {
880 /* We must reset the transmitter */
881 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
882 udelay(10);
883 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
884 udelay(10);
885 dev_err(mcbsp->dev, "McBSP%d transmitter not "
886 "ready\n", mcbsp->id);
887 return -EAGAIN;
888 }
889 }
890
891 /* We first need to enable the bus clock */
892 if (tx_word_length > OMAP_MCBSP_WORD_16)
893 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
894 OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
895
896 /* We wait for the receiver to be ready */
897 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
898 while (!(spcr1 & RRDY)) {
899 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
900 if (attempts++ > 1000) {
901 /* We must reset the receiver */
902 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
903 udelay(10);
904 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
905 udelay(10);
906 dev_err(mcbsp->dev, "McBSP%d receiver not "
907 "ready\n", mcbsp->id);
908 return -EAGAIN;
909 }
910 }
911
912 /* Receiver is ready, there is something for us */
913 if (rx_word_length > OMAP_MCBSP_WORD_16)
914 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
915 word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
916
917 word[0] = (word_lsb | (word_msb << 16));
918
919 return 0;
920 }
921 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
922
923 /*
924 * Simple DMA based buffer rx/tx routines.
925 * Nothing fancy, just a single buffer tx/rx through DMA.
926 * The DMA resources are released once the transfer is done.
927 * For anything fancier, you should use your own customized DMA
928 * routines and callbacks.
929 */
930 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
931 unsigned int length)
932 {
933 struct omap_mcbsp *mcbsp;
934 int dma_tx_ch;
935 int src_port = 0;
936 int dest_port = 0;
937 int sync_dev = 0;
938
939 if (!omap_mcbsp_check_valid_id(id)) {
940 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
941 return -ENODEV;
942 }
943 mcbsp = id_to_mcbsp_ptr(id);
944
945 if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
946 omap_mcbsp_tx_dma_callback,
947 mcbsp,
948 &dma_tx_ch)) {
949 dev_err(mcbsp->dev, " Unable to request DMA channel for "
950 "McBSP%d TX. Trying IRQ based TX\n",
951 mcbsp->id);
952 return -EAGAIN;
953 }
954 mcbsp->dma_tx_lch = dma_tx_ch;
955
956 dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
957 dma_tx_ch);
958
959 init_completion(&mcbsp->tx_dma_completion);
960
961 if (cpu_class_is_omap1()) {
962 src_port = OMAP_DMA_PORT_TIPB;
963 dest_port = OMAP_DMA_PORT_EMIFF;
964 }
965 if (cpu_class_is_omap2())
966 sync_dev = mcbsp->dma_tx_sync;
967
968 omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
969 OMAP_DMA_DATA_TYPE_S16,
970 length >> 1, 1,
971 OMAP_DMA_SYNC_ELEMENT,
972 sync_dev, 0);
973
974 omap_set_dma_dest_params(mcbsp->dma_tx_lch,
975 src_port,
976 OMAP_DMA_AMODE_CONSTANT,
977 mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
978 0, 0);
979
980 omap_set_dma_src_params(mcbsp->dma_tx_lch,
981 dest_port,
982 OMAP_DMA_AMODE_POST_INC,
983 buffer,
984 0, 0);
985
986 omap_start_dma(mcbsp->dma_tx_lch);
987 wait_for_completion(&mcbsp->tx_dma_completion);
988
989 return 0;
990 }
991 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
992
993 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
994 unsigned int length)
995 {
996 struct omap_mcbsp *mcbsp;
997 int dma_rx_ch;
998 int src_port = 0;
999 int dest_port = 0;
1000 int sync_dev = 0;
1001
1002 if (!omap_mcbsp_check_valid_id(id)) {
1003 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1004 return -ENODEV;
1005 }
1006 mcbsp = id_to_mcbsp_ptr(id);
1007
1008 if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1009 omap_mcbsp_rx_dma_callback,
1010 mcbsp,
1011 &dma_rx_ch)) {
1012 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1013 "McBSP%d RX. Trying IRQ based RX\n",
1014 mcbsp->id);
1015 return -EAGAIN;
1016 }
1017 mcbsp->dma_rx_lch = dma_rx_ch;
1018
1019 dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1020 dma_rx_ch);
1021
1022 init_completion(&mcbsp->rx_dma_completion);
1023
1024 if (cpu_class_is_omap1()) {
1025 src_port = OMAP_DMA_PORT_TIPB;
1026 dest_port = OMAP_DMA_PORT_EMIFF;
1027 }
1028 if (cpu_class_is_omap2())
1029 sync_dev = mcbsp->dma_rx_sync;
1030
1031 omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1032 OMAP_DMA_DATA_TYPE_S16,
1033 length >> 1, 1,
1034 OMAP_DMA_SYNC_ELEMENT,
1035 sync_dev, 0);
1036
1037 omap_set_dma_src_params(mcbsp->dma_rx_lch,
1038 src_port,
1039 OMAP_DMA_AMODE_CONSTANT,
1040 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1041 0, 0);
1042
1043 omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1044 dest_port,
1045 OMAP_DMA_AMODE_POST_INC,
1046 buffer,
1047 0, 0);
1048
1049 omap_start_dma(mcbsp->dma_rx_lch);
1050 wait_for_completion(&mcbsp->rx_dma_completion);
1051
1052 return 0;
1053 }
1054 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1055
1056 /*
1057 * SPI wrapper.
1058 * Since SPI setup is much simpler than the generic McBSP one,
1059 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1060 * Once this is done, you can call omap_mcbsp_start().
1061 */
1062 void omap_mcbsp_set_spi_mode(unsigned int id,
1063 const struct omap_mcbsp_spi_cfg *spi_cfg)
1064 {
1065 struct omap_mcbsp *mcbsp;
1066 struct omap_mcbsp_reg_cfg mcbsp_cfg;
1067
1068 if (!omap_mcbsp_check_valid_id(id)) {
1069 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1070 return;
1071 }
1072 mcbsp = id_to_mcbsp_ptr(id);
1073
1074 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1075
1076 /* SPI has only one frame */
1077 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1078 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1079
1080 /* Clock stop mode */
1081 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1082 mcbsp_cfg.spcr1 |= (1 << 12);
1083 else
1084 mcbsp_cfg.spcr1 |= (3 << 11);
1085
1086 /* Set clock parities */
1087 if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1088 mcbsp_cfg.pcr0 |= CLKRP;
1089 else
1090 mcbsp_cfg.pcr0 &= ~CLKRP;
1091
1092 if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1093 mcbsp_cfg.pcr0 &= ~CLKXP;
1094 else
1095 mcbsp_cfg.pcr0 |= CLKXP;
1096
1097 /* Set SCLKME to 0 and CLKSM to 1 */
1098 mcbsp_cfg.pcr0 &= ~SCLKME;
1099 mcbsp_cfg.srgr2 |= CLKSM;
1100
1101 /* Set FSXP */
1102 if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1103 mcbsp_cfg.pcr0 &= ~FSXP;
1104 else
1105 mcbsp_cfg.pcr0 |= FSXP;
1106
1107 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1108 mcbsp_cfg.pcr0 |= CLKXM;
1109 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1110 mcbsp_cfg.pcr0 |= FSXM;
1111 mcbsp_cfg.srgr2 &= ~FSGM;
1112 mcbsp_cfg.xcr2 |= XDATDLY(1);
1113 mcbsp_cfg.rcr2 |= RDATDLY(1);
1114 } else {
1115 mcbsp_cfg.pcr0 &= ~CLKXM;
1116 mcbsp_cfg.srgr1 |= CLKGDV(1);
1117 mcbsp_cfg.pcr0 &= ~FSXM;
1118 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1119 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1120 }
1121
1122 mcbsp_cfg.xcr2 &= ~XPHASE;
1123 mcbsp_cfg.rcr2 &= ~RPHASE;
1124
1125 omap_mcbsp_config(id, &mcbsp_cfg);
1126 }
1127 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1128
1129 #ifdef CONFIG_ARCH_OMAP34XX
1130 #define max_thres(m) (mcbsp->pdata->buffer_size)
1131 #define valid_threshold(m, val) ((val) <= max_thres(m))
1132 #define THRESHOLD_PROP_BUILDER(prop) \
1133 static ssize_t prop##_show(struct device *dev, \
1134 struct device_attribute *attr, char *buf) \
1135 { \
1136 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1137 \
1138 return sprintf(buf, "%u\n", mcbsp->prop); \
1139 } \
1140 \
1141 static ssize_t prop##_store(struct device *dev, \
1142 struct device_attribute *attr, \
1143 const char *buf, size_t size) \
1144 { \
1145 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
1146 unsigned long val; \
1147 int status; \
1148 \
1149 status = strict_strtoul(buf, 0, &val); \
1150 if (status) \
1151 return status; \
1152 \
1153 if (!valid_threshold(mcbsp, val)) \
1154 return -EDOM; \
1155 \
1156 mcbsp->prop = val; \
1157 return size; \
1158 } \
1159 \
1160 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1161
1162 THRESHOLD_PROP_BUILDER(max_tx_thres);
1163 THRESHOLD_PROP_BUILDER(max_rx_thres);
1164
1165 static const char *dma_op_modes[] = {
1166 "element", "threshold", "frame",
1167 };
1168
1169 static ssize_t dma_op_mode_show(struct device *dev,
1170 struct device_attribute *attr, char *buf)
1171 {
1172 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1173 int dma_op_mode, i = 0;
1174 ssize_t len = 0;
1175 const char * const *s;
1176
1177 spin_lock_irq(&mcbsp->lock);
1178 dma_op_mode = mcbsp->dma_op_mode;
1179 spin_unlock_irq(&mcbsp->lock);
1180
1181 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1182 if (dma_op_mode == i)
1183 len += sprintf(buf + len, "[%s] ", *s);
1184 else
1185 len += sprintf(buf + len, "%s ", *s);
1186 }
1187 len += sprintf(buf + len, "\n");
1188
1189 return len;
1190 }
1191
1192 static ssize_t dma_op_mode_store(struct device *dev,
1193 struct device_attribute *attr,
1194 const char *buf, size_t size)
1195 {
1196 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1197 const char * const *s;
1198 int i = 0;
1199
1200 for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1201 if (sysfs_streq(buf, *s))
1202 break;
1203
1204 if (i == ARRAY_SIZE(dma_op_modes))
1205 return -EINVAL;
1206
1207 spin_lock_irq(&mcbsp->lock);
1208 if (!mcbsp->free) {
1209 size = -EBUSY;
1210 goto unlock;
1211 }
1212 mcbsp->dma_op_mode = i;
1213
1214 unlock:
1215 spin_unlock_irq(&mcbsp->lock);
1216
1217 return size;
1218 }
1219
1220 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1221
1222 static const struct attribute *additional_attrs[] = {
1223 &dev_attr_max_tx_thres.attr,
1224 &dev_attr_max_rx_thres.attr,
1225 &dev_attr_dma_op_mode.attr,
1226 NULL,
1227 };
1228
1229 static const struct attribute_group additional_attr_group = {
1230 .attrs = (struct attribute **)additional_attrs,
1231 };
1232
1233 static inline int __devinit omap_additional_add(struct device *dev)
1234 {
1235 return sysfs_create_group(&dev->kobj, &additional_attr_group);
1236 }
1237
1238 static inline void __devexit omap_additional_remove(struct device *dev)
1239 {
1240 sysfs_remove_group(&dev->kobj, &additional_attr_group);
1241 }
1242
1243 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1244 {
1245 mcbsp->dma_op_mode = MCBSP_DMA_MODE_THRESHOLD;
1246 if (cpu_is_omap34xx()) {
1247 mcbsp->max_tx_thres = max_thres(mcbsp);
1248 mcbsp->max_rx_thres = max_thres(mcbsp);
1249 /*
1250 * REVISIT: Set dmap_op_mode to THRESHOLD as default
1251 * for mcbsp2 instances.
1252 */
1253 if (omap_additional_add(mcbsp->dev))
1254 dev_warn(mcbsp->dev,
1255 "Unable to create additional controls\n");
1256 } else {
1257 mcbsp->max_tx_thres = -EINVAL;
1258 mcbsp->max_rx_thres = -EINVAL;
1259 }
1260 }
1261
1262 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1263 {
1264 if (cpu_is_omap34xx())
1265 omap_additional_remove(mcbsp->dev);
1266 }
1267 #else
1268 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1269 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1270 #endif /* CONFIG_ARCH_OMAP34XX */
1271
1272 /*
1273 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1274 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1275 */
1276 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1277 {
1278 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1279 struct omap_mcbsp *mcbsp;
1280 int id = pdev->id - 1;
1281 int ret = 0;
1282
1283 if (!pdata) {
1284 dev_err(&pdev->dev, "McBSP device initialized without"
1285 "platform data\n");
1286 ret = -EINVAL;
1287 goto exit;
1288 }
1289
1290 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1291
1292 if (id >= omap_mcbsp_count) {
1293 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1294 ret = -EINVAL;
1295 goto exit;
1296 }
1297
1298 mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1299 if (!mcbsp) {
1300 ret = -ENOMEM;
1301 goto exit;
1302 }
1303
1304 spin_lock_init(&mcbsp->lock);
1305 mcbsp->id = id + 1;
1306 mcbsp->free = 1;
1307 mcbsp->dma_tx_lch = -1;
1308 mcbsp->dma_rx_lch = -1;
1309
1310 mcbsp->phys_base = pdata->phys_base;
1311 mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1312 if (!mcbsp->io_base) {
1313 ret = -ENOMEM;
1314 goto err_ioremap;
1315 }
1316
1317 /* Default I/O is IRQ based */
1318 mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1319 mcbsp->tx_irq = pdata->tx_irq;
1320 mcbsp->rx_irq = pdata->rx_irq;
1321 mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1322 mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1323
1324 mcbsp->iclk = clk_get(&pdev->dev, "ick");
1325 if (IS_ERR(mcbsp->iclk)) {
1326 ret = PTR_ERR(mcbsp->iclk);
1327 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1328 goto err_iclk;
1329 }
1330
1331 mcbsp->fclk = clk_get(&pdev->dev, "fck");
1332 if (IS_ERR(mcbsp->fclk)) {
1333 ret = PTR_ERR(mcbsp->fclk);
1334 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1335 goto err_fclk;
1336 }
1337
1338 mcbsp->pdata = pdata;
1339 mcbsp->dev = &pdev->dev;
1340 mcbsp_ptr[id] = mcbsp;
1341 platform_set_drvdata(pdev, mcbsp);
1342
1343 /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1344 omap34xx_device_init(mcbsp);
1345
1346 return 0;
1347
1348 err_fclk:
1349 clk_put(mcbsp->iclk);
1350 err_iclk:
1351 iounmap(mcbsp->io_base);
1352 err_ioremap:
1353 kfree(mcbsp);
1354 exit:
1355 return ret;
1356 }
1357
1358 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1359 {
1360 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1361
1362 platform_set_drvdata(pdev, NULL);
1363 if (mcbsp) {
1364
1365 if (mcbsp->pdata && mcbsp->pdata->ops &&
1366 mcbsp->pdata->ops->free)
1367 mcbsp->pdata->ops->free(mcbsp->id);
1368
1369 omap34xx_device_exit(mcbsp);
1370
1371 clk_disable(mcbsp->fclk);
1372 clk_disable(mcbsp->iclk);
1373 clk_put(mcbsp->fclk);
1374 clk_put(mcbsp->iclk);
1375
1376 iounmap(mcbsp->io_base);
1377
1378 mcbsp->fclk = NULL;
1379 mcbsp->iclk = NULL;
1380 mcbsp->free = 0;
1381 mcbsp->dev = NULL;
1382 }
1383
1384 return 0;
1385 }
1386
1387 static struct platform_driver omap_mcbsp_driver = {
1388 .probe = omap_mcbsp_probe,
1389 .remove = __devexit_p(omap_mcbsp_remove),
1390 .driver = {
1391 .name = "omap-mcbsp",
1392 },
1393 };
1394
1395 int __init omap_mcbsp_init(void)
1396 {
1397 /* Register the McBSP driver */
1398 return platform_driver_register(&omap_mcbsp_driver);
1399 }
Linux for Ginger Game Console