| blob | 29993f62b30a2c47abfb7c24a3ab5677c9142dc5 |
1 /*
2 * Device Tree Generator version: 1.1
3 *
4 * (C) Copyright 2007-2008 Xilinx, Inc.
5 * (C) Copyright 2007-2009 Michal Simek
6 *
7 * Michal SIMEK <monstr@monstr.eu>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 *
24 * CAUTION: This file is automatically generated by libgen.
25 * Version: Xilinx EDK 10.1.03 EDK_K_SP3.6
26 *
27 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
28 */
30 /dts-v1/;
31 / {
32 #address-cells = <1>;
33 #size-cells = <1>;
34 compatible = "xlnx,microblaze";
35 model = "testing";
36 DDR2_SDRAM: memory@90000000 {
37 device_type = "memory";
38 reg = < 0x90000000 0x10000000 >;
39 } ;
40 chosen {
41 bootargs = "console=ttyUL0,115200 highres=on";
42 linux,stdout-path = "/plb@0/serial@84000000";
43 } ;
44 cpus {
45 #address-cells = <1>;
46 #cpus = <0x1>;
47 #size-cells = <0>;
48 microblaze_0: cpu@0 {
49 clock-frequency = <125000000>;
50 compatible = "xlnx,microblaze-7.10.d";
51 d-cache-baseaddr = <0x90000000>;
52 d-cache-highaddr = <0x9fffffff>;
53 d-cache-line-size = <0x10>;
54 d-cache-size = <0x2000>;
55 device_type = "cpu";
56 i-cache-baseaddr = <0x90000000>;
57 i-cache-highaddr = <0x9fffffff>;
58 i-cache-line-size = <0x10>;
59 i-cache-size = <0x2000>;
60 model = "microblaze,7.10.d";
61 reg = <0>;
62 timebase-frequency = <125000000>;
63 xlnx,addr-tag-bits = <0xf>;
64 xlnx,allow-dcache-wr = <0x1>;
65 xlnx,allow-icache-wr = <0x1>;
66 xlnx,area-optimized = <0x0>;
67 xlnx,cache-byte-size = <0x2000>;
68 xlnx,d-lmb = <0x1>;
69 xlnx,d-opb = <0x0>;
70 xlnx,d-plb = <0x1>;
71 xlnx,data-size = <0x20>;
72 xlnx,dcache-addr-tag = <0xf>;
73 xlnx,dcache-always-used = <0x1>;
74 xlnx,dcache-byte-size = <0x2000>;
75 xlnx,dcache-line-len = <0x4>;
76 xlnx,dcache-use-fsl = <0x1>;
77 xlnx,debug-enabled = <0x1>;
78 xlnx,div-zero-exception = <0x1>;
79 xlnx,dopb-bus-exception = <0x0>;
80 xlnx,dynamic-bus-sizing = <0x1>;
81 xlnx,edge-is-positive = <0x1>;
82 xlnx,family = "virtex5";
83 xlnx,fpu-exception = <0x1>;
84 xlnx,fsl-data-size = <0x20>;
85 xlnx,fsl-exception = <0x0>;
86 xlnx,fsl-links = <0x0>;
87 xlnx,i-lmb = <0x1>;
88 xlnx,i-opb = <0x0>;
89 xlnx,i-plb = <0x1>;
90 xlnx,icache-always-used = <0x1>;
91 xlnx,icache-line-len = <0x4>;
92 xlnx,icache-use-fsl = <0x1>;
93 xlnx,ill-opcode-exception = <0x1>;
94 xlnx,instance = "microblaze_0";
95 xlnx,interconnect = <0x1>;
96 xlnx,interrupt-is-edge = <0x0>;
97 xlnx,iopb-bus-exception = <0x0>;
98 xlnx,mmu-dtlb-size = <0x4>;
99 xlnx,mmu-itlb-size = <0x2>;
100 xlnx,mmu-tlb-access = <0x3>;
101 xlnx,mmu-zones = <0x10>;
102 xlnx,number-of-pc-brk = <0x1>;
103 xlnx,number-of-rd-addr-brk = <0x0>;
104 xlnx,number-of-wr-addr-brk = <0x0>;
105 xlnx,opcode-0x0-illegal = <0x1>;
106 xlnx,pvr = <0x2>;
107 xlnx,pvr-user1 = <0x0>;
108 xlnx,pvr-user2 = <0x0>;
109 xlnx,reset-msr = <0x0>;
110 xlnx,sco = <0x0>;
111 xlnx,unaligned-exceptions = <0x1>;
112 xlnx,use-barrel = <0x1>;
113 xlnx,use-dcache = <0x1>;
114 xlnx,use-div = <0x1>;
115 xlnx,use-ext-brk = <0x1>;
116 xlnx,use-ext-nm-brk = <0x1>;
117 xlnx,use-extended-fsl-instr = <0x0>;
118 xlnx,use-fpu = <0x2>;
119 xlnx,use-hw-mul = <0x2>;
120 xlnx,use-icache = <0x1>;
121 xlnx,use-interrupt = <0x1>;
122 xlnx,use-mmu = <0x3>;
123 xlnx,use-msr-instr = <0x1>;
124 xlnx,use-pcmp-instr = <0x1>;
125 } ;
126 } ;
127 mb_plb: plb@0 {
128 #address-cells = <1>;
129 #size-cells = <1>;
130 compatible = "xlnx,plb-v46-1.03.a", "simple-bus";
131 ranges ;
132 FLASH: flash@a0000000 {
133 bank-width = <2>;
134 compatible = "xlnx,xps-mch-emc-2.00.a", "cfi-flash";
135 reg = < 0xa0000000 0x2000000 >;
136 xlnx,family = "virtex5";
137 xlnx,include-datawidth-matching-0 = <0x1>;
138 xlnx,include-datawidth-matching-1 = <0x0>;
139 xlnx,include-datawidth-matching-2 = <0x0>;
140 xlnx,include-datawidth-matching-3 = <0x0>;
141 xlnx,include-negedge-ioregs = <0x0>;
142 xlnx,include-plb-ipif = <0x1>;
143 xlnx,include-wrbuf = <0x1>;
144 xlnx,max-mem-width = <0x10>;
145 xlnx,mch-native-dwidth = <0x20>;
146 xlnx,mch-plb-clk-period-ps = <0x1f40>;
147 xlnx,mch-splb-awidth = <0x20>;
148 xlnx,mch0-accessbuf-depth = <0x10>;
149 xlnx,mch0-protocol = <0x0>;
150 xlnx,mch0-rddatabuf-depth = <0x10>;
151 xlnx,mch1-accessbuf-depth = <0x10>;
152 xlnx,mch1-protocol = <0x0>;
153 xlnx,mch1-rddatabuf-depth = <0x10>;
154 xlnx,mch2-accessbuf-depth = <0x10>;
155 xlnx,mch2-protocol = <0x0>;
156 xlnx,mch2-rddatabuf-depth = <0x10>;
157 xlnx,mch3-accessbuf-depth = <0x10>;
158 xlnx,mch3-protocol = <0x0>;
159 xlnx,mch3-rddatabuf-depth = <0x10>;
160 xlnx,mem0-width = <0x10>;
161 xlnx,mem1-width = <0x20>;
162 xlnx,mem2-width = <0x20>;
163 xlnx,mem3-width = <0x20>;
164 xlnx,num-banks-mem = <0x1>;
165 xlnx,num-channels = <0x0>;
166 xlnx,priority-mode = <0x0>;
167 xlnx,synch-mem-0 = <0x0>;
168 xlnx,synch-mem-1 = <0x0>;
169 xlnx,synch-mem-2 = <0x0>;
170 xlnx,synch-mem-3 = <0x0>;
171 xlnx,synch-pipedelay-0 = <0x2>;
172 xlnx,synch-pipedelay-1 = <0x2>;
173 xlnx,synch-pipedelay-2 = <0x2>;
174 xlnx,synch-pipedelay-3 = <0x2>;
175 xlnx,tavdv-ps-mem-0 = <0x1adb0>;
176 xlnx,tavdv-ps-mem-1 = <0x3a98>;
177 xlnx,tavdv-ps-mem-2 = <0x3a98>;
178 xlnx,tavdv-ps-mem-3 = <0x3a98>;
179 xlnx,tcedv-ps-mem-0 = <0x1adb0>;
180 xlnx,tcedv-ps-mem-1 = <0x3a98>;
181 xlnx,tcedv-ps-mem-2 = <0x3a98>;
182 xlnx,tcedv-ps-mem-3 = <0x3a98>;
183 xlnx,thzce-ps-mem-0 = <0x88b8>;
184 xlnx,thzce-ps-mem-1 = <0x1b58>;
185 xlnx,thzce-ps-mem-2 = <0x1b58>;
186 xlnx,thzce-ps-mem-3 = <0x1b58>;
187 xlnx,thzoe-ps-mem-0 = <0x1b58>;
188 xlnx,thzoe-ps-mem-1 = <0x1b58>;
189 xlnx,thzoe-ps-mem-2 = <0x1b58>;
190 xlnx,thzoe-ps-mem-3 = <0x1b58>;
191 xlnx,tlzwe-ps-mem-0 = <0x88b8>;
192 xlnx,tlzwe-ps-mem-1 = <0x0>;
193 xlnx,tlzwe-ps-mem-2 = <0x0>;
194 xlnx,tlzwe-ps-mem-3 = <0x0>;
195 xlnx,twc-ps-mem-0 = <0x2af8>;
196 xlnx,twc-ps-mem-1 = <0x3a98>;
197 xlnx,twc-ps-mem-2 = <0x3a98>;
198 xlnx,twc-ps-mem-3 = <0x3a98>;
199 xlnx,twp-ps-mem-0 = <0x11170>;
200 xlnx,twp-ps-mem-1 = <0x2ee0>;
201 xlnx,twp-ps-mem-2 = <0x2ee0>;
202 xlnx,twp-ps-mem-3 = <0x2ee0>;
203 xlnx,xcl0-linesize = <0x4>;
204 xlnx,xcl0-writexfer = <0x1>;
205 xlnx,xcl1-linesize = <0x4>;
206 xlnx,xcl1-writexfer = <0x1>;
207 xlnx,xcl2-linesize = <0x4>;
208 xlnx,xcl2-writexfer = <0x1>;
209 xlnx,xcl3-linesize = <0x4>;
210 xlnx,xcl3-writexfer = <0x1>;
211 } ;
212 Hard_Ethernet_MAC: xps-ll-temac@81c00000 {
213 #address-cells = <1>;
214 #size-cells = <1>;
215 compatible = "xlnx,compound";
216 ethernet@81c00000 {
217 compatible = "xlnx,xps-ll-temac-1.01.b";
218 device_type = "network";
219 interrupt-parent = <&xps_intc_0>;
220 interrupts = < 5 2 >;
221 llink-connected = <&PIM3>;
222 local-mac-address = [ 02 00 00 00 00 00 ];
223 reg = < 0x81c00000 0x40 >;
224 xlnx,bus2core-clk-ratio = <0x1>;
225 xlnx,phy-type = <0x1>;
226 xlnx,phyaddr = <0x1>;
227 xlnx,rxcsum = <0x0>;
228 xlnx,rxfifo = <0x1000>;
229 xlnx,temac-type = <0x0>;
230 xlnx,txcsum = <0x0>;
231 xlnx,txfifo = <0x1000>;
232 } ;
233 } ;
234 IIC_EEPROM: i2c@81600000 {
235 compatible = "xlnx,xps-iic-2.00.a";
236 interrupt-parent = <&xps_intc_0>;
237 interrupts = < 6 2 >;
238 reg = < 0x81600000 0x10000 >;
239 xlnx,clk-freq = <0x7735940>;
240 xlnx,family = "virtex5";
241 xlnx,gpo-width = <0x1>;
242 xlnx,iic-freq = <0x186a0>;
243 xlnx,scl-inertial-delay = <0x0>;
244 xlnx,sda-inertial-delay = <0x0>;
245 xlnx,ten-bit-adr = <0x0>;
246 } ;
247 LEDs_8Bit: gpio@81400000 {
248 compatible = "xlnx,xps-gpio-1.00.a";
249 interrupt-parent = <&xps_intc_0>;
250 interrupts = < 7 2 >;
251 reg = < 0x81400000 0x10000 >;
252 xlnx,all-inputs = <0x0>;
253 xlnx,all-inputs-2 = <0x0>;
254 xlnx,dout-default = <0x0>;
255 xlnx,dout-default-2 = <0x0>;
256 xlnx,family = "virtex5";
257 xlnx,gpio-width = <0x8>;
258 xlnx,interrupt-present = <0x1>;
259 xlnx,is-bidir = <0x1>;
260 xlnx,is-bidir-2 = <0x1>;
261 xlnx,is-dual = <0x0>;
262 xlnx,tri-default = <0xffffffff>;
263 xlnx,tri-default-2 = <0xffffffff>;
264 } ;
265 RS232_Uart_1: serial@84000000 {
266 clock-frequency = <125000000>;
267 compatible = "xlnx,xps-uartlite-1.00.a";
268 current-speed = <115200>;
269 device_type = "serial";
270 interrupt-parent = <&xps_intc_0>;
271 interrupts = < 8 0 >;
272 port-number = <0>;
273 reg = < 0x84000000 0x10000 >;
274 xlnx,baudrate = <0x1c200>;
275 xlnx,data-bits = <0x8>;
276 xlnx,family = "virtex5";
277 xlnx,odd-parity = <0x0>;
278 xlnx,use-parity = <0x0>;
279 } ;
280 SysACE_CompactFlash: sysace@83600000 {
281 compatible = "xlnx,xps-sysace-1.00.a";
282 interrupt-parent = <&xps_intc_0>;
283 interrupts = < 4 2 >;
284 reg = < 0x83600000 0x10000 >;
285 xlnx,family = "virtex5";
286 xlnx,mem-width = <0x10>;
287 } ;
288 debug_module: debug@84400000 {
289 compatible = "xlnx,mdm-1.00.d";
290 reg = < 0x84400000 0x10000 >;
291 xlnx,family = "virtex5";
292 xlnx,interconnect = <0x1>;
293 xlnx,jtag-chain = <0x2>;
294 xlnx,mb-dbg-ports = <0x1>;
295 xlnx,uart-width = <0x8>;
296 xlnx,use-uart = <0x1>;
297 xlnx,write-fsl-ports = <0x0>;
298 } ;
299 mpmc@90000000 {
300 #address-cells = <1>;
301 #size-cells = <1>;
302 compatible = "xlnx,mpmc-4.02.a";
303 PIM3: sdma@84600180 {
304 compatible = "xlnx,ll-dma-1.00.a";
305 interrupt-parent = <&xps_intc_0>;
306 interrupts = < 2 2 1 2 >;
307 reg = < 0x84600180 0x80 >;
308 } ;
309 } ;
310 xps_intc_0: interrupt-controller@81800000 {
311 #interrupt-cells = <0x2>;
312 compatible = "xlnx,xps-intc-1.00.a";
313 interrupt-controller ;
314 reg = < 0x81800000 0x10000 >;
315 xlnx,kind-of-intr = <0x100>;
316 xlnx,num-intr-inputs = <0x9>;
317 } ;
318 xps_timer_1: timer@83c00000 {
319 compatible = "xlnx,xps-timer-1.00.a";
320 interrupt-parent = <&xps_intc_0>;
321 interrupts = < 3 2 >;
322 reg = < 0x83c00000 0x10000 >;
323 xlnx,count-width = <0x20>;
324 xlnx,family = "virtex5";
325 xlnx,gen0-assert = <0x1>;
326 xlnx,gen1-assert = <0x1>;
327 xlnx,one-timer-only = <0x0>;
328 xlnx,trig0-assert = <0x1>;
329 xlnx,trig1-assert = <0x1>;
330 } ;
331 } ;
332 } ;