Full support for Ginger Console
[linux-ginger.git] / arch / sh / kernel / cpu / sh4a / setup-sh7723.c
blob4caa5a7ca86edf0ead7964255a2361955e507c1f
1 /*
2 * SH7723 Setup
4 * Copyright (C) 2008 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/mm.h>
14 #include <linux/serial_sci.h>
15 #include <linux/uio_driver.h>
16 #include <linux/usb/r8a66597.h>
17 #include <linux/sh_timer.h>
18 #include <linux/io.h>
19 #include <asm/clock.h>
20 #include <asm/mmzone.h>
21 #include <cpu/sh7723.h>
23 static struct uio_info vpu_platform_data = {
24 .name = "VPU5",
25 .version = "0",
26 .irq = 60,
29 static struct resource vpu_resources[] = {
30 [0] = {
31 .name = "VPU",
32 .start = 0xfe900000,
33 .end = 0xfe902807,
34 .flags = IORESOURCE_MEM,
36 [1] = {
37 /* place holder for contiguous memory */
41 static struct platform_device vpu_device = {
42 .name = "uio_pdrv_genirq",
43 .id = 0,
44 .dev = {
45 .platform_data = &vpu_platform_data,
47 .resource = vpu_resources,
48 .num_resources = ARRAY_SIZE(vpu_resources),
49 .archdata = {
50 .hwblk_id = HWBLK_VPU,
54 static struct uio_info veu0_platform_data = {
55 .name = "VEU2H",
56 .version = "0",
57 .irq = 54,
60 static struct resource veu0_resources[] = {
61 [0] = {
62 .name = "VEU2H0",
63 .start = 0xfe920000,
64 .end = 0xfe92027b,
65 .flags = IORESOURCE_MEM,
67 [1] = {
68 /* place holder for contiguous memory */
72 static struct platform_device veu0_device = {
73 .name = "uio_pdrv_genirq",
74 .id = 1,
75 .dev = {
76 .platform_data = &veu0_platform_data,
78 .resource = veu0_resources,
79 .num_resources = ARRAY_SIZE(veu0_resources),
80 .archdata = {
81 .hwblk_id = HWBLK_VEU2H0,
85 static struct uio_info veu1_platform_data = {
86 .name = "VEU2H",
87 .version = "0",
88 .irq = 27,
91 static struct resource veu1_resources[] = {
92 [0] = {
93 .name = "VEU2H1",
94 .start = 0xfe924000,
95 .end = 0xfe92427b,
96 .flags = IORESOURCE_MEM,
98 [1] = {
99 /* place holder for contiguous memory */
103 static struct platform_device veu1_device = {
104 .name = "uio_pdrv_genirq",
105 .id = 2,
106 .dev = {
107 .platform_data = &veu1_platform_data,
109 .resource = veu1_resources,
110 .num_resources = ARRAY_SIZE(veu1_resources),
111 .archdata = {
112 .hwblk_id = HWBLK_VEU2H1,
116 static struct sh_timer_config cmt_platform_data = {
117 .name = "CMT",
118 .channel_offset = 0x60,
119 .timer_bit = 5,
120 .clk = "cmt0",
121 .clockevent_rating = 125,
122 .clocksource_rating = 125,
125 static struct resource cmt_resources[] = {
126 [0] = {
127 .name = "CMT",
128 .start = 0x044a0060,
129 .end = 0x044a006b,
130 .flags = IORESOURCE_MEM,
132 [1] = {
133 .start = 104,
134 .flags = IORESOURCE_IRQ,
138 static struct platform_device cmt_device = {
139 .name = "sh_cmt",
140 .id = 0,
141 .dev = {
142 .platform_data = &cmt_platform_data,
144 .resource = cmt_resources,
145 .num_resources = ARRAY_SIZE(cmt_resources),
146 .archdata = {
147 .hwblk_id = HWBLK_CMT,
151 static struct sh_timer_config tmu0_platform_data = {
152 .name = "TMU0",
153 .channel_offset = 0x04,
154 .timer_bit = 0,
155 .clk = "tmu0",
156 .clockevent_rating = 200,
159 static struct resource tmu0_resources[] = {
160 [0] = {
161 .name = "TMU0",
162 .start = 0xffd80008,
163 .end = 0xffd80013,
164 .flags = IORESOURCE_MEM,
166 [1] = {
167 .start = 16,
168 .flags = IORESOURCE_IRQ,
172 static struct platform_device tmu0_device = {
173 .name = "sh_tmu",
174 .id = 0,
175 .dev = {
176 .platform_data = &tmu0_platform_data,
178 .resource = tmu0_resources,
179 .num_resources = ARRAY_SIZE(tmu0_resources),
180 .archdata = {
181 .hwblk_id = HWBLK_TMU0,
185 static struct sh_timer_config tmu1_platform_data = {
186 .name = "TMU1",
187 .channel_offset = 0x10,
188 .timer_bit = 1,
189 .clk = "tmu0",
190 .clocksource_rating = 200,
193 static struct resource tmu1_resources[] = {
194 [0] = {
195 .name = "TMU1",
196 .start = 0xffd80014,
197 .end = 0xffd8001f,
198 .flags = IORESOURCE_MEM,
200 [1] = {
201 .start = 17,
202 .flags = IORESOURCE_IRQ,
206 static struct platform_device tmu1_device = {
207 .name = "sh_tmu",
208 .id = 1,
209 .dev = {
210 .platform_data = &tmu1_platform_data,
212 .resource = tmu1_resources,
213 .num_resources = ARRAY_SIZE(tmu1_resources),
214 .archdata = {
215 .hwblk_id = HWBLK_TMU0,
219 static struct sh_timer_config tmu2_platform_data = {
220 .name = "TMU2",
221 .channel_offset = 0x1c,
222 .timer_bit = 2,
223 .clk = "tmu0",
226 static struct resource tmu2_resources[] = {
227 [0] = {
228 .name = "TMU2",
229 .start = 0xffd80020,
230 .end = 0xffd8002b,
231 .flags = IORESOURCE_MEM,
233 [1] = {
234 .start = 18,
235 .flags = IORESOURCE_IRQ,
239 static struct platform_device tmu2_device = {
240 .name = "sh_tmu",
241 .id = 2,
242 .dev = {
243 .platform_data = &tmu2_platform_data,
245 .resource = tmu2_resources,
246 .num_resources = ARRAY_SIZE(tmu2_resources),
247 .archdata = {
248 .hwblk_id = HWBLK_TMU0,
252 static struct sh_timer_config tmu3_platform_data = {
253 .name = "TMU3",
254 .channel_offset = 0x04,
255 .timer_bit = 0,
256 .clk = "tmu1",
259 static struct resource tmu3_resources[] = {
260 [0] = {
261 .name = "TMU3",
262 .start = 0xffd90008,
263 .end = 0xffd90013,
264 .flags = IORESOURCE_MEM,
266 [1] = {
267 .start = 57,
268 .flags = IORESOURCE_IRQ,
272 static struct platform_device tmu3_device = {
273 .name = "sh_tmu",
274 .id = 3,
275 .dev = {
276 .platform_data = &tmu3_platform_data,
278 .resource = tmu3_resources,
279 .num_resources = ARRAY_SIZE(tmu3_resources),
280 .archdata = {
281 .hwblk_id = HWBLK_TMU1,
285 static struct sh_timer_config tmu4_platform_data = {
286 .name = "TMU4",
287 .channel_offset = 0x10,
288 .timer_bit = 1,
289 .clk = "tmu1",
292 static struct resource tmu4_resources[] = {
293 [0] = {
294 .name = "TMU4",
295 .start = 0xffd90014,
296 .end = 0xffd9001f,
297 .flags = IORESOURCE_MEM,
299 [1] = {
300 .start = 58,
301 .flags = IORESOURCE_IRQ,
305 static struct platform_device tmu4_device = {
306 .name = "sh_tmu",
307 .id = 4,
308 .dev = {
309 .platform_data = &tmu4_platform_data,
311 .resource = tmu4_resources,
312 .num_resources = ARRAY_SIZE(tmu4_resources),
313 .archdata = {
314 .hwblk_id = HWBLK_TMU1,
318 static struct sh_timer_config tmu5_platform_data = {
319 .name = "TMU5",
320 .channel_offset = 0x1c,
321 .timer_bit = 2,
322 .clk = "tmu1",
325 static struct resource tmu5_resources[] = {
326 [0] = {
327 .name = "TMU5",
328 .start = 0xffd90020,
329 .end = 0xffd9002b,
330 .flags = IORESOURCE_MEM,
332 [1] = {
333 .start = 57,
334 .flags = IORESOURCE_IRQ,
338 static struct platform_device tmu5_device = {
339 .name = "sh_tmu",
340 .id = 5,
341 .dev = {
342 .platform_data = &tmu5_platform_data,
344 .resource = tmu5_resources,
345 .num_resources = ARRAY_SIZE(tmu5_resources),
346 .archdata = {
347 .hwblk_id = HWBLK_TMU1,
351 static struct plat_sci_port sci_platform_data[] = {
353 .mapbase = 0xffe00000,
354 .flags = UPF_BOOT_AUTOCONF,
355 .type = PORT_SCIF,
356 .irqs = { 80, 80, 80, 80 },
357 .clk = "scif0",
359 .mapbase = 0xffe10000,
360 .flags = UPF_BOOT_AUTOCONF,
361 .type = PORT_SCIF,
362 .irqs = { 81, 81, 81, 81 },
363 .clk = "scif1",
365 .mapbase = 0xffe20000,
366 .flags = UPF_BOOT_AUTOCONF,
367 .type = PORT_SCIF,
368 .irqs = { 82, 82, 82, 82 },
369 .clk = "scif2",
371 .mapbase = 0xa4e30000,
372 .flags = UPF_BOOT_AUTOCONF,
373 .type = PORT_SCIFA,
374 .irqs = { 56, 56, 56, 56 },
375 .clk = "scif3",
377 .mapbase = 0xa4e40000,
378 .flags = UPF_BOOT_AUTOCONF,
379 .type = PORT_SCIFA,
380 .irqs = { 88, 88, 88, 88 },
381 .clk = "scif4",
383 .mapbase = 0xa4e50000,
384 .flags = UPF_BOOT_AUTOCONF,
385 .type = PORT_SCIFA,
386 .irqs = { 109, 109, 109, 109 },
387 .clk = "scif5",
388 }, {
389 .flags = 0,
393 static struct platform_device sci_device = {
394 .name = "sh-sci",
395 .id = -1,
396 .dev = {
397 .platform_data = sci_platform_data,
401 static struct resource rtc_resources[] = {
402 [0] = {
403 .start = 0xa465fec0,
404 .end = 0xa465fec0 + 0x58 - 1,
405 .flags = IORESOURCE_IO,
407 [1] = {
408 /* Period IRQ */
409 .start = 69,
410 .flags = IORESOURCE_IRQ,
412 [2] = {
413 /* Carry IRQ */
414 .start = 70,
415 .flags = IORESOURCE_IRQ,
417 [3] = {
418 /* Alarm IRQ */
419 .start = 68,
420 .flags = IORESOURCE_IRQ,
424 static struct platform_device rtc_device = {
425 .name = "sh-rtc",
426 .id = -1,
427 .num_resources = ARRAY_SIZE(rtc_resources),
428 .resource = rtc_resources,
429 .archdata = {
430 .hwblk_id = HWBLK_RTC,
434 static struct r8a66597_platdata r8a66597_data = {
435 .on_chip = 1,
438 static struct resource sh7723_usb_host_resources[] = {
439 [0] = {
440 .start = 0xa4d80000,
441 .end = 0xa4d800ff,
442 .flags = IORESOURCE_MEM,
444 [1] = {
445 .start = 65,
446 .end = 65,
447 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
451 static struct platform_device sh7723_usb_host_device = {
452 .name = "r8a66597_hcd",
453 .id = 0,
454 .dev = {
455 .dma_mask = NULL, /* not use dma */
456 .coherent_dma_mask = 0xffffffff,
457 .platform_data = &r8a66597_data,
459 .num_resources = ARRAY_SIZE(sh7723_usb_host_resources),
460 .resource = sh7723_usb_host_resources,
461 .archdata = {
462 .hwblk_id = HWBLK_USB,
466 static struct resource iic_resources[] = {
467 [0] = {
468 .name = "IIC",
469 .start = 0x04470000,
470 .end = 0x04470017,
471 .flags = IORESOURCE_MEM,
473 [1] = {
474 .start = 96,
475 .end = 99,
476 .flags = IORESOURCE_IRQ,
480 static struct platform_device iic_device = {
481 .name = "i2c-sh_mobile",
482 .id = 0, /* "i2c0" clock */
483 .num_resources = ARRAY_SIZE(iic_resources),
484 .resource = iic_resources,
485 .archdata = {
486 .hwblk_id = HWBLK_IIC,
490 static struct platform_device *sh7723_devices[] __initdata = {
491 &cmt_device,
492 &tmu0_device,
493 &tmu1_device,
494 &tmu2_device,
495 &tmu3_device,
496 &tmu4_device,
497 &tmu5_device,
498 &sci_device,
499 &rtc_device,
500 &iic_device,
501 &sh7723_usb_host_device,
502 &vpu_device,
503 &veu0_device,
504 &veu1_device,
507 static int __init sh7723_devices_setup(void)
509 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
510 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
511 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
513 return platform_add_devices(sh7723_devices,
514 ARRAY_SIZE(sh7723_devices));
516 arch_initcall(sh7723_devices_setup);
518 static struct platform_device *sh7723_early_devices[] __initdata = {
519 &cmt_device,
520 &tmu0_device,
521 &tmu1_device,
522 &tmu2_device,
523 &tmu3_device,
524 &tmu4_device,
525 &tmu5_device,
528 void __init plat_early_device_setup(void)
530 early_platform_add_devices(sh7723_early_devices,
531 ARRAY_SIZE(sh7723_early_devices));
534 #define RAMCR_CACHE_L2FC 0x0002
535 #define RAMCR_CACHE_L2E 0x0001
536 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
537 void __uses_jump_to_uncached l2_cache_init(void)
539 /* Enable L2 cache */
540 ctrl_outl(L2_CACHE_ENABLE, RAMCR);
543 enum {
544 UNUSED=0,
546 /* interrupt sources */
547 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
548 HUDI,
549 DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3,
550 _2DG_TRI,_2DG_INI,_2DG_CEI,
551 DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3,
552 VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI,
553 SCIFA_SCIFA0,
554 VPU_VPUI,
555 TPU_TPUI,
556 ADC_ADI,
557 USB_USI0,
558 RTC_ATI,RTC_PRI,RTC_CUI,
559 DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR,
560 DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR,
561 KEYSC_KEYI,
562 SCIF_SCIF0,SCIF_SCIF1,SCIF_SCIF2,
563 MSIOF_MSIOFI0,MSIOF_MSIOFI1,
564 SCIFA_SCIFA1,
565 FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I,
566 I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI,
567 SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2,
568 CMT_CMTI,
569 TSIF_TSIFI,
570 SIU_SIUI,
571 SCIFA_SCIFA2,
572 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
573 IRDA_IRDAI,
574 ATAPI_ATAPII,
575 SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2,
576 VEU2H1_VEU2HI,
577 LCDC_LCDCI,
578 TMU1_TUNI0,TMU1_TUNI1,TMU1_TUNI2,
580 /* interrupt groups */
581 DMAC1A, DMAC0A, VIO, DMAC0B, FLCTL, I2C, _2DG,
582 SDHI1, RTC, DMAC1B, SDHI0,
585 static struct intc_vect vectors[] __initdata = {
586 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
587 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
588 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
589 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
591 INTC_VECT(DMAC1A_DEI0,0x700),
592 INTC_VECT(DMAC1A_DEI1,0x720),
593 INTC_VECT(DMAC1A_DEI2,0x740),
594 INTC_VECT(DMAC1A_DEI3,0x760),
596 INTC_VECT(_2DG_TRI, 0x780),
597 INTC_VECT(_2DG_INI, 0x7A0),
598 INTC_VECT(_2DG_CEI, 0x7C0),
600 INTC_VECT(DMAC0A_DEI0,0x800),
601 INTC_VECT(DMAC0A_DEI1,0x820),
602 INTC_VECT(DMAC0A_DEI2,0x840),
603 INTC_VECT(DMAC0A_DEI3,0x860),
605 INTC_VECT(VIO_CEUI,0x880),
606 INTC_VECT(VIO_BEUI,0x8A0),
607 INTC_VECT(VIO_VEU2HI,0x8C0),
608 INTC_VECT(VIO_VOUI,0x8E0),
610 INTC_VECT(SCIFA_SCIFA0,0x900),
611 INTC_VECT(VPU_VPUI,0x980),
612 INTC_VECT(TPU_TPUI,0x9A0),
613 INTC_VECT(ADC_ADI,0x9E0),
614 INTC_VECT(USB_USI0,0xA20),
616 INTC_VECT(RTC_ATI,0xA80),
617 INTC_VECT(RTC_PRI,0xAA0),
618 INTC_VECT(RTC_CUI,0xAC0),
620 INTC_VECT(DMAC1B_DEI4,0xB00),
621 INTC_VECT(DMAC1B_DEI5,0xB20),
622 INTC_VECT(DMAC1B_DADERR,0xB40),
624 INTC_VECT(DMAC0B_DEI4,0xB80),
625 INTC_VECT(DMAC0B_DEI5,0xBA0),
626 INTC_VECT(DMAC0B_DADERR,0xBC0),
628 INTC_VECT(KEYSC_KEYI,0xBE0),
629 INTC_VECT(SCIF_SCIF0,0xC00),
630 INTC_VECT(SCIF_SCIF1,0xC20),
631 INTC_VECT(SCIF_SCIF2,0xC40),
632 INTC_VECT(MSIOF_MSIOFI0,0xC80),
633 INTC_VECT(MSIOF_MSIOFI1,0xCA0),
634 INTC_VECT(SCIFA_SCIFA1,0xD00),
636 INTC_VECT(FLCTL_FLSTEI,0xD80),
637 INTC_VECT(FLCTL_FLTENDI,0xDA0),
638 INTC_VECT(FLCTL_FLTREQ0I,0xDC0),
639 INTC_VECT(FLCTL_FLTREQ1I,0xDE0),
641 INTC_VECT(I2C_ALI,0xE00),
642 INTC_VECT(I2C_TACKI,0xE20),
643 INTC_VECT(I2C_WAITI,0xE40),
644 INTC_VECT(I2C_DTEI,0xE60),
646 INTC_VECT(SDHI0_SDHII0,0xE80),
647 INTC_VECT(SDHI0_SDHII1,0xEA0),
648 INTC_VECT(SDHI0_SDHII2,0xEC0),
650 INTC_VECT(CMT_CMTI,0xF00),
651 INTC_VECT(TSIF_TSIFI,0xF20),
652 INTC_VECT(SIU_SIUI,0xF80),
653 INTC_VECT(SCIFA_SCIFA2,0xFA0),
655 INTC_VECT(TMU0_TUNI0,0x400),
656 INTC_VECT(TMU0_TUNI1,0x420),
657 INTC_VECT(TMU0_TUNI2,0x440),
659 INTC_VECT(IRDA_IRDAI,0x480),
660 INTC_VECT(ATAPI_ATAPII,0x4A0),
662 INTC_VECT(SDHI1_SDHII0,0x4E0),
663 INTC_VECT(SDHI1_SDHII1,0x500),
664 INTC_VECT(SDHI1_SDHII2,0x520),
666 INTC_VECT(VEU2H1_VEU2HI,0x560),
667 INTC_VECT(LCDC_LCDCI,0x580),
669 INTC_VECT(TMU1_TUNI0,0x920),
670 INTC_VECT(TMU1_TUNI1,0x940),
671 INTC_VECT(TMU1_TUNI2,0x960),
675 static struct intc_group groups[] __initdata = {
676 INTC_GROUP(DMAC1A,DMAC1A_DEI0,DMAC1A_DEI1,DMAC1A_DEI2,DMAC1A_DEI3),
677 INTC_GROUP(DMAC0A,DMAC0A_DEI0,DMAC0A_DEI1,DMAC0A_DEI2,DMAC0A_DEI3),
678 INTC_GROUP(VIO, VIO_CEUI,VIO_BEUI,VIO_VEU2HI,VIO_VOUI),
679 INTC_GROUP(DMAC0B, DMAC0B_DEI4,DMAC0B_DEI5,DMAC0B_DADERR),
680 INTC_GROUP(FLCTL,FLCTL_FLSTEI,FLCTL_FLTENDI,FLCTL_FLTREQ0I,FLCTL_FLTREQ1I),
681 INTC_GROUP(I2C,I2C_ALI,I2C_TACKI,I2C_WAITI,I2C_DTEI),
682 INTC_GROUP(_2DG, _2DG_TRI,_2DG_INI,_2DG_CEI),
683 INTC_GROUP(SDHI1, SDHI1_SDHII0,SDHI1_SDHII1,SDHI1_SDHII2),
684 INTC_GROUP(RTC, RTC_ATI,RTC_PRI,RTC_CUI),
685 INTC_GROUP(DMAC1B, DMAC1B_DEI4,DMAC1B_DEI5,DMAC1B_DADERR),
686 INTC_GROUP(SDHI0,SDHI0_SDHII0,SDHI0_SDHII1,SDHI0_SDHII2),
689 static struct intc_mask_reg mask_registers[] __initdata = {
690 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
691 { 0, TMU1_TUNI2,TMU1_TUNI1,TMU1_TUNI0,0,SDHI1_SDHII2,SDHI1_SDHII1,SDHI1_SDHII0} },
692 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
693 { VIO_VOUI, VIO_VEU2HI,VIO_BEUI,VIO_CEUI,DMAC0A_DEI3,DMAC0A_DEI2,DMAC0A_DEI1,DMAC0A_DEI0 } },
694 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
695 { 0, 0, 0, VPU_VPUI,0,0,0,SCIFA_SCIFA0 } },
696 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
697 { DMAC1A_DEI3,DMAC1A_DEI2,DMAC1A_DEI1,DMAC1A_DEI0,0,0,0,IRDA_IRDAI } },
698 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
699 { 0,TMU0_TUNI2,TMU0_TUNI1,TMU0_TUNI0,VEU2H1_VEU2HI,0,0,LCDC_LCDCI } },
700 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
701 { KEYSC_KEYI,DMAC0B_DADERR,DMAC0B_DEI5,DMAC0B_DEI4,0,SCIF_SCIF2,SCIF_SCIF1,SCIF_SCIF0 } },
702 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
703 { 0,0,0,SCIFA_SCIFA1,ADC_ADI,0,MSIOF_MSIOFI1,MSIOF_MSIOFI0 } },
704 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
705 { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
706 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
707 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
708 { 0,SDHI0_SDHII2,SDHI0_SDHII1,SDHI0_SDHII0,0,0,SCIFA_SCIFA2,SIU_SIUI } },
709 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
710 { 0, 0, 0, CMT_CMTI, 0, 0, USB_USI0,0 } },
711 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
712 { 0, DMAC1B_DADERR,DMAC1B_DEI5,DMAC1B_DEI4,0,RTC_ATI,RTC_PRI,RTC_CUI } },
713 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
714 { 0,_2DG_CEI,_2DG_INI,_2DG_TRI,0,TPU_TPUI,0,TSIF_TSIFI } },
715 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
716 { 0,0,0,0,0,0,0,ATAPI_ATAPII } },
717 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
718 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
721 static struct intc_prio_reg prio_registers[] __initdata = {
722 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2, IRDA_IRDAI } },
723 { 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2H1_VEU2HI, LCDC_LCDCI, DMAC1A, 0} },
724 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 0} },
725 { 0xa408000c, 0, 16, 4, /* IPRD */ { } },
726 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA_SCIFA0, VPU_VPUI } },
727 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC_KEYI, DMAC0B, USB_USI0, CMT_CMTI } },
728 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,0 } },
729 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0,MSIOF_MSIOFI1, FLCTL, I2C } },
730 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA_SCIFA1,0,TSIF_TSIFI,_2DG } },
731 { 0xa4080024, 0, 16, 4, /* IPRJ */ { ADC_ADI,0,SIU_SIUI,SDHI1 } },
732 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC,DMAC1B,0,SDHI0 } },
733 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA_SCIFA2,0,TPU_TPUI,ATAPI_ATAPII } },
734 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
735 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
738 static struct intc_sense_reg sense_registers[] __initdata = {
739 { 0xa414001c, 16, 2, /* ICR1 */
740 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
743 static struct intc_mask_reg ack_registers[] __initdata = {
744 { 0xa4140024, 0, 8, /* INTREQ00 */
745 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
748 static DECLARE_INTC_DESC_ACK(intc_desc, "sh7723", vectors, groups,
749 mask_registers, prio_registers, sense_registers,
750 ack_registers);
752 void __init plat_irq_setup(void)
754 register_intc_controller(&intc_desc);