Full support for Ginger Console
[linux-ginger.git] / arch / sh / kernel / cpu / sh4a / setup-sh7763.c
blob4659fff6b842057defff64a65b506714170d3c99
1 /*
2 * SH7763 Setup
4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2007 Yoshihiro Shimoda
6 * Copyright (C) 2008, 2009 Nobuhiro Iwamatsu
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
12 #include <linux/platform_device.h>
13 #include <linux/init.h>
14 #include <linux/serial.h>
15 #include <linux/sh_timer.h>
16 #include <linux/io.h>
17 #include <linux/serial_sci.h>
19 static struct resource rtc_resources[] = {
20 [0] = {
21 .start = 0xffe80000,
22 .end = 0xffe80000 + 0x58 - 1,
23 .flags = IORESOURCE_IO,
25 [1] = {
26 /* Shared Period/Carry/Alarm IRQ */
27 .start = 20,
28 .flags = IORESOURCE_IRQ,
32 static struct platform_device rtc_device = {
33 .name = "sh-rtc",
34 .id = -1,
35 .num_resources = ARRAY_SIZE(rtc_resources),
36 .resource = rtc_resources,
39 static struct plat_sci_port sci_platform_data[] = {
41 .mapbase = 0xffe00000,
42 .flags = UPF_BOOT_AUTOCONF,
43 .type = PORT_SCIF,
44 .irqs = { 40, 40, 40, 40 },
45 }, {
46 .mapbase = 0xffe08000,
47 .flags = UPF_BOOT_AUTOCONF,
48 .type = PORT_SCIF,
49 .irqs = { 76, 76, 76, 76 },
50 }, {
51 .mapbase = 0xffe10000,
52 .flags = UPF_BOOT_AUTOCONF,
53 .type = PORT_SCIF,
54 .irqs = { 104, 104, 104, 104 },
55 }, {
56 .flags = 0,
60 static struct platform_device sci_device = {
61 .name = "sh-sci",
62 .id = -1,
63 .dev = {
64 .platform_data = sci_platform_data,
68 static struct resource usb_ohci_resources[] = {
69 [0] = {
70 .start = 0xffec8000,
71 .end = 0xffec80ff,
72 .flags = IORESOURCE_MEM,
74 [1] = {
75 .start = 83,
76 .end = 83,
77 .flags = IORESOURCE_IRQ,
81 static u64 usb_ohci_dma_mask = 0xffffffffUL;
82 static struct platform_device usb_ohci_device = {
83 .name = "sh_ohci",
84 .id = -1,
85 .dev = {
86 .dma_mask = &usb_ohci_dma_mask,
87 .coherent_dma_mask = 0xffffffff,
89 .num_resources = ARRAY_SIZE(usb_ohci_resources),
90 .resource = usb_ohci_resources,
93 static struct resource usbf_resources[] = {
94 [0] = {
95 .start = 0xffec0000,
96 .end = 0xffec00ff,
97 .flags = IORESOURCE_MEM,
99 [1] = {
100 .start = 84,
101 .end = 84,
102 .flags = IORESOURCE_IRQ,
106 static struct platform_device usbf_device = {
107 .name = "sh_udc",
108 .id = -1,
109 .dev = {
110 .dma_mask = NULL,
111 .coherent_dma_mask = 0xffffffff,
113 .num_resources = ARRAY_SIZE(usbf_resources),
114 .resource = usbf_resources,
117 static struct sh_timer_config tmu0_platform_data = {
118 .name = "TMU0",
119 .channel_offset = 0x04,
120 .timer_bit = 0,
121 .clk = "peripheral_clk",
122 .clockevent_rating = 200,
125 static struct resource tmu0_resources[] = {
126 [0] = {
127 .name = "TMU0",
128 .start = 0xffd80008,
129 .end = 0xffd80013,
130 .flags = IORESOURCE_MEM,
132 [1] = {
133 .start = 28,
134 .flags = IORESOURCE_IRQ,
138 static struct platform_device tmu0_device = {
139 .name = "sh_tmu",
140 .id = 0,
141 .dev = {
142 .platform_data = &tmu0_platform_data,
144 .resource = tmu0_resources,
145 .num_resources = ARRAY_SIZE(tmu0_resources),
148 static struct sh_timer_config tmu1_platform_data = {
149 .name = "TMU1",
150 .channel_offset = 0x10,
151 .timer_bit = 1,
152 .clk = "peripheral_clk",
153 .clocksource_rating = 200,
156 static struct resource tmu1_resources[] = {
157 [0] = {
158 .name = "TMU1",
159 .start = 0xffd80014,
160 .end = 0xffd8001f,
161 .flags = IORESOURCE_MEM,
163 [1] = {
164 .start = 29,
165 .flags = IORESOURCE_IRQ,
169 static struct platform_device tmu1_device = {
170 .name = "sh_tmu",
171 .id = 1,
172 .dev = {
173 .platform_data = &tmu1_platform_data,
175 .resource = tmu1_resources,
176 .num_resources = ARRAY_SIZE(tmu1_resources),
179 static struct sh_timer_config tmu2_platform_data = {
180 .name = "TMU2",
181 .channel_offset = 0x1c,
182 .timer_bit = 2,
183 .clk = "peripheral_clk",
186 static struct resource tmu2_resources[] = {
187 [0] = {
188 .name = "TMU2",
189 .start = 0xffd80020,
190 .end = 0xffd8002f,
191 .flags = IORESOURCE_MEM,
193 [1] = {
194 .start = 30,
195 .flags = IORESOURCE_IRQ,
199 static struct platform_device tmu2_device = {
200 .name = "sh_tmu",
201 .id = 2,
202 .dev = {
203 .platform_data = &tmu2_platform_data,
205 .resource = tmu2_resources,
206 .num_resources = ARRAY_SIZE(tmu2_resources),
209 static struct sh_timer_config tmu3_platform_data = {
210 .name = "TMU3",
211 .channel_offset = 0x04,
212 .timer_bit = 0,
213 .clk = "peripheral_clk",
216 static struct resource tmu3_resources[] = {
217 [0] = {
218 .name = "TMU3",
219 .start = 0xffd88008,
220 .end = 0xffd88013,
221 .flags = IORESOURCE_MEM,
223 [1] = {
224 .start = 96,
225 .flags = IORESOURCE_IRQ,
229 static struct platform_device tmu3_device = {
230 .name = "sh_tmu",
231 .id = 3,
232 .dev = {
233 .platform_data = &tmu3_platform_data,
235 .resource = tmu3_resources,
236 .num_resources = ARRAY_SIZE(tmu3_resources),
239 static struct sh_timer_config tmu4_platform_data = {
240 .name = "TMU4",
241 .channel_offset = 0x10,
242 .timer_bit = 1,
243 .clk = "peripheral_clk",
246 static struct resource tmu4_resources[] = {
247 [0] = {
248 .name = "TMU4",
249 .start = 0xffd88014,
250 .end = 0xffd8801f,
251 .flags = IORESOURCE_MEM,
253 [1] = {
254 .start = 97,
255 .flags = IORESOURCE_IRQ,
259 static struct platform_device tmu4_device = {
260 .name = "sh_tmu",
261 .id = 4,
262 .dev = {
263 .platform_data = &tmu4_platform_data,
265 .resource = tmu4_resources,
266 .num_resources = ARRAY_SIZE(tmu4_resources),
269 static struct sh_timer_config tmu5_platform_data = {
270 .name = "TMU5",
271 .channel_offset = 0x1c,
272 .timer_bit = 2,
273 .clk = "peripheral_clk",
276 static struct resource tmu5_resources[] = {
277 [0] = {
278 .name = "TMU5",
279 .start = 0xffd88020,
280 .end = 0xffd8802b,
281 .flags = IORESOURCE_MEM,
283 [1] = {
284 .start = 98,
285 .flags = IORESOURCE_IRQ,
289 static struct platform_device tmu5_device = {
290 .name = "sh_tmu",
291 .id = 5,
292 .dev = {
293 .platform_data = &tmu5_platform_data,
295 .resource = tmu5_resources,
296 .num_resources = ARRAY_SIZE(tmu5_resources),
299 static struct platform_device *sh7763_devices[] __initdata = {
300 &tmu0_device,
301 &tmu1_device,
302 &tmu2_device,
303 &tmu3_device,
304 &tmu4_device,
305 &tmu5_device,
306 &rtc_device,
307 &sci_device,
308 &usb_ohci_device,
309 &usbf_device,
312 static int __init sh7763_devices_setup(void)
314 return platform_add_devices(sh7763_devices,
315 ARRAY_SIZE(sh7763_devices));
317 arch_initcall(sh7763_devices_setup);
319 static struct platform_device *sh7763_early_devices[] __initdata = {
320 &tmu0_device,
321 &tmu1_device,
322 &tmu2_device,
323 &tmu3_device,
324 &tmu4_device,
325 &tmu5_device,
328 void __init plat_early_device_setup(void)
330 early_platform_add_devices(sh7763_early_devices,
331 ARRAY_SIZE(sh7763_early_devices));
334 enum {
335 UNUSED = 0,
337 /* interrupt sources */
339 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
340 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
341 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
342 IRL_HHLL, IRL_HHLH, IRL_HHHL,
344 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
345 RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
346 HUDI, LCDC, DMAC, SCIF0, IIC0, IIC1, CMT, GETHER, HAC,
347 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
348 STIF0, STIF1, SCIF1, SIOF0, SIOF1, SIOF2,
349 USBH, USBF, TPU, PCC, MMCIF, SIM,
350 TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3,
351 SCIF2, GPIO,
353 /* interrupt groups */
355 TMU012, TMU345,
358 static struct intc_vect vectors[] __initdata = {
359 INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
360 INTC_VECT(RTC, 0x4c0),
361 INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580),
362 INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0),
363 INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600),
364 INTC_VECT(LCDC, 0x620),
365 INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
366 INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
367 INTC_VECT(DMAC, 0x6c0),
368 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
369 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
370 INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
371 INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0),
372 INTC_VECT(CMT, 0x900), INTC_VECT(GETHER, 0x920),
373 INTC_VECT(GETHER, 0x940), INTC_VECT(GETHER, 0x960),
374 INTC_VECT(HAC, 0x980),
375 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
376 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
377 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
378 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
379 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
380 INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60),
381 INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
382 INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
383 INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20),
384 INTC_VECT(USBH, 0xc60), INTC_VECT(USBF, 0xc80),
385 INTC_VECT(USBF, 0xca0),
386 INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0),
387 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
388 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
389 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
390 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
391 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
392 INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60),
393 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
394 INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0),
395 INTC_VECT(SCIF2, 0xf00), INTC_VECT(SCIF2, 0xf20),
396 INTC_VECT(SCIF2, 0xf40), INTC_VECT(SCIF2, 0xf60),
397 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
398 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
401 static struct intc_group groups[] __initdata = {
402 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
403 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
406 static struct intc_mask_reg mask_registers[] __initdata = {
407 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
408 { 0, 0, 0, 0, 0, 0, GPIO, 0,
409 SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB,
410 PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC,
411 HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
412 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
413 { 0, 0, 0, 0, 0, 0, SCIF2, USBF,
414 0, 0, STIF1, STIF0, 0, 0, USBH, GETHER,
415 PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1,
416 LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } },
419 static struct intc_prio_reg prio_registers[] __initdata = {
420 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
421 TMU2, TMU2_TICPI } },
422 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
423 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
424 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } },
425 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
426 PCISERR, PCIINTA } },
427 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
428 PCIINTD, PCIC5 } },
429 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } },
430 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } },
431 { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } },
432 { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } },
433 { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } },
434 { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } },
435 { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } },
436 { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } },
439 static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups,
440 mask_registers, prio_registers, NULL);
442 /* Support for external interrupt pins in IRQ mode */
443 static struct intc_vect irq_vectors[] __initdata = {
444 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
445 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
446 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
447 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
450 static struct intc_mask_reg irq_mask_registers[] __initdata = {
451 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
452 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
455 static struct intc_prio_reg irq_prio_registers[] __initdata = {
456 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
457 IRQ4, IRQ5, IRQ6, IRQ7 } },
460 static struct intc_sense_reg irq_sense_registers[] __initdata = {
461 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
462 IRQ4, IRQ5, IRQ6, IRQ7 } },
465 static struct intc_mask_reg irq_ack_registers[] __initdata = {
466 { 0xffd00024, 0, 32, /* INTREQ */
467 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
470 static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7763-irq", irq_vectors,
471 NULL, irq_mask_registers, irq_prio_registers,
472 irq_sense_registers, irq_ack_registers);
475 /* External interrupt pins in IRL mode */
476 static struct intc_vect irl_vectors[] __initdata = {
477 INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
478 INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
479 INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
480 INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
481 INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
482 INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
483 INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
484 INTC_VECT(IRL_HHHL, 0x3c0),
487 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
488 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
489 { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
490 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
491 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
492 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
495 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
496 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
497 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
498 IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
499 IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
500 IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
501 IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
504 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors,
505 NULL, irl7654_mask_registers, NULL, NULL);
507 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
508 NULL, irl3210_mask_registers, NULL, NULL);
510 #define INTC_ICR0 0xffd00000
511 #define INTC_INTMSK0 0xffd00044
512 #define INTC_INTMSK1 0xffd00048
513 #define INTC_INTMSK2 0xffd40080
514 #define INTC_INTMSKCLR1 0xffd00068
515 #define INTC_INTMSKCLR2 0xffd40084
517 void __init plat_irq_setup(void)
519 /* disable IRQ7-0 */
520 ctrl_outl(0xff000000, INTC_INTMSK0);
522 /* disable IRL3-0 + IRL7-4 */
523 ctrl_outl(0xc0000000, INTC_INTMSK1);
524 ctrl_outl(0xfffefffe, INTC_INTMSK2);
526 register_intc_controller(&intc_desc);
529 void __init plat_irq_setup_pins(int mode)
531 switch (mode) {
532 case IRQ_MODE_IRQ:
533 /* select IRQ mode for IRL3-0 + IRL7-4 */
534 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
535 register_intc_controller(&intc_irq_desc);
536 break;
537 case IRQ_MODE_IRL7654:
538 /* enable IRL7-4 but don't provide any masking */
539 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
540 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
541 break;
542 case IRQ_MODE_IRL3210:
543 /* enable IRL0-3 but don't provide any masking */
544 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
545 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
546 break;
547 case IRQ_MODE_IRL7654_MASK:
548 /* enable IRL7-4 and mask using cpu intc controller */
549 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
550 register_intc_controller(&intc_irl7654_desc);
551 break;
552 case IRQ_MODE_IRL3210_MASK:
553 /* enable IRL0-3 and mask using cpu intc controller */
554 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
555 register_intc_controller(&intc_irl3210_desc);
556 break;
557 default:
558 BUG();