drivers/staging/rt3090/rtmp_chip.h

   1 /*
   2  *************************************************************************
   3  * Ralink Tech Inc.
   4  * 5F., No.36, Taiyuan St., Jhubei City,
   5  * Hsinchu County 302,
   6  * Taiwan, R.O.C.
   7  *
   8  * (c) Copyright 2002-2007, Ralink Technology, Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify  *
  11  * it under the terms of the GNU General Public License as published by  *
  12  * the Free Software Foundation; either version 2 of the License, or     *
  13  * (at your option) any later version.                                   *
  14  *                                                                       *
  15  * This program is distributed in the hope that it will be useful,       *
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  * GNU General Public License for more details.                          *
  19  *                                                                       *
  20  * You should have received a copy of the GNU General Public License     *
  21  * along with this program; if not, write to the                         *
  22  * Free Software Foundation, Inc.,                                       *
  23  * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  24  *                                                                       *
  25  *************************************************************************
  26
  27         Module Name:
  28         rtmp_chip.h
  29
  30         Abstract:
  31         Ralink Wireless Chip related definition & structures
  32
  33         Revision History:
  34         Who                     When              What
  35         --------        ----------        ----------------------------------------------
  36 */
  37
  38 #ifndef __RTMP_CHIP_H__
  39 #define __RTMP_CHIP_H__
  40
  41 #include "rtmp_type.h"
  42
  43 #ifdef RT3090
  44 #include "rt3090.h"
  45 #endif // RT3090 //
  46
  47 #ifdef RT3370
  48 #include "rt3370.h"
  49 #endif // RT3370 //
  50
  51 #ifdef RT3390
  52 #include "rt3390.h"
  53 #endif // RT3390 //
  54
  55 // We will have a cost down version which mac version is 0x3090xxxx
  56 //
  57 // RT3090A facts
  58 //
  59 // a) 2.4 GHz
  60 // b) Replacement for RT3090
  61 // c) Internal LNA
  62 // d) Interference over channel #14
  63 // e) New BBP features (e.g., SIG re-modulation)
  64 //
  65 #define IS_RT3090A(_pAd)                                ((((_pAd)->MACVersion & 0xffff0000) == 0x30900000))
  66
  67 // We will have a cost down version which mac version is 0x3090xxxx
  68 #define IS_RT3090(_pAd)                         ((((_pAd)->MACVersion & 0xffff0000) == 0x30710000) || (IS_RT3090A(_pAd)))
  69
  70 #define IS_RT3070(_pAd)         (((_pAd)->MACVersion & 0xffff0000) == 0x30700000)
  71 #define IS_RT3071(_pAd)         (((_pAd)->MACVersion & 0xffff0000) == 0x30710000)
  72 #define IS_RT2070(_pAd)         (((_pAd)->RfIcType == RFIC_2020) || ((_pAd)->EFuseTag == 0x27))
  73
  74 #define IS_RT30xx(_pAd)         (((_pAd)->MACVersion & 0xfff00000) == 0x30700000||IS_RT3090A(_pAd))
  75 //#define IS_RT305X(_pAd)               ((_pAd)->MACVersion == 0x28720200)
  76
  77 /* RT3572, 3592, 3562, 3062 share the same MAC version */
  78 #define IS_RT3572(_pAd)         (((_pAd)->MACVersion & 0xffff0000) == 0x35720000)
  79 #define IS_VERSION_BEFORE_F(_pAd)                       (((_pAd)->MACVersion&0xffff) <= 0x0211)
  80 // F version is 0x0212, E version is 0x0211. 309x can save more power after F version.
  81 #define IS_VERSION_AFTER_F(_pAd)                        ((((_pAd)->MACVersion&0xffff) >= 0x0212) || (((_pAd)->b3090ESpecialChip == TRUE)))
  82 //
  83 // RT3390 facts
  84 //
  85 // a) Base on RT3090 (RF IC: RT3020)
  86 // b) 2.4 GHz
  87 // c) 1x1
  88 // d) Single chip
  89 // e) Internal components: PA and LNA
  90 //
  91 //RT3390,RT3370
  92 #define IS_RT3390(_pAd)                         (((_pAd)->MACVersion & 0xFFFF0000) == 0x33900000)
  93
  94 // ------------------------------------------------------
  95 // PCI registers - base address 0x0000
  96 // ------------------------------------------------------
  97 #define CHIP_PCI_CFG            0x0000
  98 #define CHIP_PCI_EECTRL         0x0004
  99 #define CHIP_PCI_MCUCTRL        0x0008
 100
 101 #define OPT_14                  0x114
 102
 103 #define RETRY_LIMIT             10
 104
 105
 106
 107 // ------------------------------------------------------
 108 // BBP & RF     definition
 109 // ------------------------------------------------------
 110 #define BUSY                            1
 111 #define IDLE                            0
 112
 113
 114 //-------------------------------------------------------------------------
 115 // EEPROM definition
 116 //-------------------------------------------------------------------------
 117 #define EEDO                        0x08
 118 #define EEDI                        0x04
 119 #define EECS                        0x02
 120 #define EESK                        0x01
 121 #define EERL                        0x80
 122
 123 #define EEPROM_WRITE_OPCODE         0x05
 124 #define EEPROM_READ_OPCODE          0x06
 125 #define EEPROM_EWDS_OPCODE          0x10
 126 #define EEPROM_EWEN_OPCODE          0x13
 127
 128 #define NUM_EEPROM_BBP_PARMS            19                      // Include NIC Config 0, 1, CR, TX ALC step, BBPs
 129 #define NUM_EEPROM_TX_G_PARMS           7
 130 #define EEPROM_NIC1_OFFSET          0x34                // The address is from NIC config 0, not BBP register ID
 131 #define EEPROM_NIC2_OFFSET          0x36                // The address is from NIC config 0, not BBP register ID
 132 #define EEPROM_BBP_BASE_OFFSET          0xf0            // The address is from NIC config 0, not BBP register ID
 133 #define EEPROM_G_TX_PWR_OFFSET          0x52
 134 #define EEPROM_G_TX2_PWR_OFFSET         0x60
 135 #define EEPROM_LED1_OFFSET                      0x3c
 136 #define EEPROM_LED2_OFFSET                      0x3e
 137 #define EEPROM_LED3_OFFSET                      0x40
 138 #define EEPROM_LNA_OFFSET                       0x44
 139 #define EEPROM_RSSI_BG_OFFSET           0x46
 140 #define EEPROM_TXMIXER_GAIN_2_4G        0x48
 141 #define EEPROM_RSSI_A_OFFSET            0x4a
 142 #define EEPROM_TXMIXER_GAIN_5G          0x4c
 143 #define EEPROM_DEFINE_MAX_TXPWR         0x4e
 144 #define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G        0xde    // 20MHZ 2.4G tx power.
 145 #define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G        0xee    // 40MHZ 2.4G tx power.
 146 #define EEPROM_TXPOWER_BYRATE_20MHZ_5G          0xfa    // 20MHZ 5G tx power.
 147 #define EEPROM_TXPOWER_BYRATE_40MHZ_5G          0x10a   // 40MHZ 5G tx power.
 148 #define EEPROM_A_TX_PWR_OFFSET      0x78
 149 #define EEPROM_A_TX2_PWR_OFFSET      0xa6
 150 //#define EEPROM_Japan_TX_PWR_OFFSET      0x90 // 802.11j
 151 //#define EEPROM_Japan_TX2_PWR_OFFSET      0xbe
 152 //#define EEPROM_TSSI_REF_OFFSET        0x54
 153 //#define EEPROM_TSSI_DELTA_OFFSET      0x24
 154 //#define EEPROM_CCK_TX_PWR_OFFSET  0x62
 155 //#define EEPROM_CALIBRATE_OFFSET       0x7c
 156 #define EEPROM_VERSION_OFFSET       0x02
 157 #define EEPROM_FREQ_OFFSET                      0x3a
 158 #define EEPROM_TXPOWER_BYRATE   0xde    // 20MHZ power.
 159 #define EEPROM_TXPOWER_DELTA            0x50    // 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ.
 160 #define VALID_EEPROM_VERSION        1
 161
 162
 163 /*
 164   *   EEPROM operation related marcos
 165   */
 166 #define RT28xx_EEPROM_READ16(_pAd, _offset, _value)                     \
 167         (_pAd)->chipOps.eeread((RTMP_ADAPTER *)(_pAd), (USHORT)(_offset), (PUSHORT)&(_value))
 168
 169 #define RT28xx_EEPROM_WRITE16(_pAd, _offset, _value)            \
 170         (_pAd)->chipOps.eewrite((RTMP_ADAPTER *)(_pAd), (USHORT)(_offset), (USHORT)(_value))
 171
 172
 173
 174 // -------------------------------------------------------------------
 175 //  E2PROM data layout
 176 // -------------------------------------------------------------------
 177
 178 //
 179 // MCU_LEDCS: MCU LED Control Setting.
 180 //
 181 typedef union  _MCU_LEDCS_STRUC {
 182         struct  {
 183 #ifdef RT_BIG_ENDIAN
 184                 UCHAR           Polarity:1;
 185                 UCHAR           LedMode:7;
 186 #else
 187                 UCHAR           LedMode:7;
 188                 UCHAR           Polarity:1;
 189 #endif // RT_BIG_ENDIAN //
 190         } field;
 191         UCHAR                           word;
 192 } MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
 193
 194
 195 //
 196 // EEPROM antenna select format
 197 //
 198 #ifdef RT_BIG_ENDIAN
 199 typedef union   _EEPROM_ANTENNA_STRUC   {
 200         struct  {
 201                 USHORT      Rsv:4;
 202                 USHORT      RfIcType:4;             // see E2PROM document
 203                 USHORT          TxPath:4;       // 1: 1T, 2: 2T
 204                 USHORT          RxPath:4;       // 1: 1R, 2: 2R, 3: 3R
 205         }       field;
 206         USHORT                  word;
 207 }       EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
 208 #else
 209 typedef union   _EEPROM_ANTENNA_STRUC   {
 210         struct  {
 211                 USHORT          RxPath:4;       // 1: 1R, 2: 2R, 3: 3R
 212                 USHORT          TxPath:4;       // 1: 1T, 2: 2T
 213                 USHORT      RfIcType:4;             // see E2PROM document
 214                 USHORT      Rsv:4;
 215         }       field;
 216         USHORT                  word;
 217 }       EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
 218 #endif
 219
 220 #ifdef RT_BIG_ENDIAN
 221 typedef union _EEPROM_NIC_CINFIG2_STRUC {
 222         struct  {
 223                 USHORT          DACTestBit:1;                   // control if driver should patch the DAC issue
 224                 USHORT          Rsv2:3;                                 // must be 0
 225                 USHORT          AntDiversity:1;                 // Antenna diversity
 226                 USHORT          Rsv1:1;                                 // must be 0
 227                 USHORT          BW40MAvailForA:1;                       // 0:enable, 1:disable
 228                 USHORT          BW40MAvailForG:1;                       // 0:enable, 1:disable
 229                 USHORT          EnableWPSPBC:1;                 // WPS PBC Control bit
 230                 USHORT          BW40MSidebandForA:1;
 231                 USHORT          BW40MSidebandForG:1;
 232                 USHORT          CardbusAcceleration:1;  // !!! NOTE: 0 - enable, 1 - disable
 233                 USHORT          ExternalLNAForA:1;                      // external LNA enable for 5G
 234                 USHORT          ExternalLNAForG:1;                      // external LNA enable for 2.4G
 235                 USHORT          DynamicTxAgcControl:1;                  //
 236                 USHORT          HardwareRadioControl:1; // Whether RF is controlled by driver or HW. 1:enable hw control, 0:disable
 237         }       field;
 238         USHORT                  word;
 239 }       EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
 240 #else
 241 typedef union _EEPROM_NIC_CINFIG2_STRUC {
 242         struct {
 243                 USHORT          HardwareRadioControl:1; // 1:enable, 0:disable
 244                 USHORT          DynamicTxAgcControl:1;                  //
 245                 USHORT          ExternalLNAForG:1;                              //
 246                 USHORT          ExternalLNAForA:1;                      // external LNA enable for 2.4G
 247                 USHORT          CardbusAcceleration:1;  // !!! NOTE: 0 - enable, 1 - disable
 248                 USHORT          BW40MSidebandForG:1;
 249                 USHORT          BW40MSidebandForA:1;
 250                 USHORT          EnableWPSPBC:1;                 // WPS PBC Control bit
 251                 USHORT          BW40MAvailForG:1;                       // 0:enable, 1:disable
 252                 USHORT          BW40MAvailForA:1;                       // 0:enable, 1:disable
 253                 USHORT          Rsv1:1;                                 // must be 0
 254                 USHORT          AntDiversity:1;                 // Antenna diversity
 255                 USHORT          Rsv2:3;                                 // must be 0
 256                 USHORT          DACTestBit:1;                   // control if driver should patch the DAC issue
 257         }       field;
 258         USHORT                  word;
 259 }       EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
 260 #endif
 261
 262 //
 263 // TX_PWR Value valid range 0xFA(-6) ~ 0x24(36)
 264 //
 265 #ifdef RT_BIG_ENDIAN
 266 typedef union   _EEPROM_TX_PWR_STRUC    {
 267         struct  {
 268                 CHAR    Byte1;                          // High Byte
 269                 CHAR    Byte0;                          // Low Byte
 270         }       field;
 271         USHORT  word;
 272 }       EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
 273 #else
 274 typedef union   _EEPROM_TX_PWR_STRUC    {
 275         struct  {
 276                 CHAR    Byte0;                          // Low Byte
 277                 CHAR    Byte1;                          // High Byte
 278         }       field;
 279         USHORT  word;
 280 }       EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
 281 #endif
 282
 283 #ifdef RT_BIG_ENDIAN
 284 typedef union   _EEPROM_VERSION_STRUC   {
 285         struct  {
 286                 UCHAR   Version;                        // High Byte
 287                 UCHAR   FaeReleaseNumber;       // Low Byte
 288         }       field;
 289         USHORT  word;
 290 }       EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
 291 #else
 292 typedef union   _EEPROM_VERSION_STRUC   {
 293         struct  {
 294                 UCHAR   FaeReleaseNumber;       // Low Byte
 295                 UCHAR   Version;                        // High Byte
 296         }       field;
 297         USHORT  word;
 298 }       EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
 299 #endif
 300
 301 #ifdef RT_BIG_ENDIAN
 302 typedef union   _EEPROM_LED_STRUC       {
 303         struct  {
 304                 USHORT  Rsvd:3;                         // Reserved
 305                 USHORT  LedMode:5;                      // Led mode.
 306                 USHORT  PolarityGPIO_4:1;       // Polarity GPIO#4 setting.
 307                 USHORT  PolarityGPIO_3:1;       // Polarity GPIO#3 setting.
 308                 USHORT  PolarityGPIO_2:1;       // Polarity GPIO#2 setting.
 309                 USHORT  PolarityGPIO_1:1;       // Polarity GPIO#1 setting.
 310                 USHORT  PolarityGPIO_0:1;       // Polarity GPIO#0 setting.
 311                 USHORT  PolarityACT:1;          // Polarity ACT setting.
 312                 USHORT  PolarityRDY_A:1;                // Polarity RDY_A setting.
 313                 USHORT  PolarityRDY_G:1;                // Polarity RDY_G setting.
 314         }       field;
 315         USHORT  word;
 316 }       EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
 317 #else
 318 typedef union   _EEPROM_LED_STRUC       {
 319         struct  {
 320                 USHORT  PolarityRDY_G:1;                // Polarity RDY_G setting.
 321                 USHORT  PolarityRDY_A:1;                // Polarity RDY_A setting.
 322                 USHORT  PolarityACT:1;          // Polarity ACT setting.
 323                 USHORT  PolarityGPIO_0:1;       // Polarity GPIO#0 setting.
 324                 USHORT  PolarityGPIO_1:1;       // Polarity GPIO#1 setting.
 325                 USHORT  PolarityGPIO_2:1;       // Polarity GPIO#2 setting.
 326                 USHORT  PolarityGPIO_3:1;       // Polarity GPIO#3 setting.
 327                 USHORT  PolarityGPIO_4:1;       // Polarity GPIO#4 setting.
 328                 USHORT  LedMode:5;                      // Led mode.
 329                 USHORT  Rsvd:3;                         // Reserved
 330         }       field;
 331         USHORT  word;
 332 }       EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
 333 #endif
 334
 335 #ifdef RT_BIG_ENDIAN
 336 typedef union   _EEPROM_TXPOWER_DELTA_STRUC     {
 337         struct  {
 338                 UCHAR   TxPowerEnable:1;// Enable
 339                 UCHAR   Type:1;                 // 1: plus the delta value, 0: minus the delta value
 340                 UCHAR   DeltaValue:6;   // Tx Power dalta value (MAX=4)
 341         }       field;
 342         UCHAR   value;
 343 }       EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
 344 #else
 345 typedef union   _EEPROM_TXPOWER_DELTA_STRUC     {
 346         struct  {
 347                 UCHAR   DeltaValue:6;   // Tx Power dalta value (MAX=4)
 348                 UCHAR   Type:1;                 // 1: plus the delta value, 0: minus the delta value
 349                 UCHAR   TxPowerEnable:1;// Enable
 350         }       field;
 351         UCHAR   value;
 352 }       EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
 353 #endif
 354
 355 #endif  // __RTMP_CHIP_H__ //