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WATCHDOG: use base address from platform resources and make 2430 boot again
[linux-ginger.git] / drivers / usb / gadget / fsl_usb2_udc.c
blob157054ea39786936ff3f269bc58bf705ba4d7c83
1 /*
2 * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved.
3 *
4 * Author: Li Yang <leoli@freescale.com>
5 * Jiang Bo <tanya.jiang@freescale.com>
6 *
7 * Description:
8 * Freescale high-speed USB SOC DR module device controller driver.
9 * This can be found on MPC8349E/MPC8313E cpus.
10 * The driver is previously named as mpc_udc. Based on bare board
11 * code from Dave Liu and Shlomi Gridish.
12 *
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
17 */
18
19 #undef VERBOSE
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 #include <linux/ioport.h>
24 #include <linux/types.h>
25 #include <linux/errno.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/init.h>
30 #include <linux/timer.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/proc_fs.h>
34 #include <linux/mm.h>
35 #include <linux/moduleparam.h>
36 #include <linux/device.h>
37 #include <linux/usb/ch9.h>
38 #include <linux/usb_gadget.h>
39 #include <linux/usb/otg.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/platform_device.h>
42 #include <linux/fsl_devices.h>
43 #include <linux/dmapool.h>
44
45 #include <asm/byteorder.h>
46 #include <asm/io.h>
47 #include <asm/irq.h>
48 #include <asm/system.h>
49 #include <asm/unaligned.h>
50 #include <asm/dma.h>
51 #include <asm/cacheflush.h>
52
53 #include "fsl_usb2_udc.h"
54
55 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
56 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
57 #define DRIVER_VERSION "Apr 20, 2007"
58
59 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
60
61 static const char driver_name[] = "fsl-usb2-udc";
62 static const char driver_desc[] = DRIVER_DESC;
63
64 volatile static struct usb_dr_device *dr_regs = NULL;
65 volatile static struct usb_sys_interface *usb_sys_regs = NULL;
66
67 /* it is initialized in probe() */
68 static struct fsl_udc *udc_controller = NULL;
69
70 static const struct usb_endpoint_descriptor
71 fsl_ep0_desc = {
72 .bLength = USB_DT_ENDPOINT_SIZE,
73 .bDescriptorType = USB_DT_ENDPOINT,
74 .bEndpointAddress = 0,
75 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
76 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
77 };
78
79 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state);
80 static int fsl_udc_resume(struct platform_device *pdev);
81 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
82
83 #ifdef CONFIG_PPC32
84 #define fsl_readl(addr) in_le32(addr)
85 #define fsl_writel(addr, val32) out_le32(val32, addr)
86 #else
87 #define fsl_readl(addr) readl(addr)
88 #define fsl_writel(addr, val32) writel(addr, val32)
89 #endif
90
91 /********************************************************************
92 * Internal Used Function
93 ********************************************************************/
94 /*-----------------------------------------------------------------
95 * done() - retire a request; caller blocked irqs
96 * @status : request status to be set, only works when
97 * request is still in progress.
98 *--------------------------------------------------------------*/
99 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
100 {
101 struct fsl_udc *udc = NULL;
102 unsigned char stopped = ep->stopped;
103 struct ep_td_struct *curr_td, *next_td;
104 int j;
105
106 udc = (struct fsl_udc *)ep->udc;
107 /* Removed the req from fsl_ep->queue */
108 list_del_init(&req->queue);
109
110 /* req.status should be set as -EINPROGRESS in ep_queue() */
111 if (req->req.status == -EINPROGRESS)
112 req->req.status = status;
113 else
114 status = req->req.status;
115
116 /* Free dtd for the request */
117 next_td = req->head;
118 for (j = 0; j < req->dtd_count; j++) {
119 curr_td = next_td;
120 if (j != req->dtd_count - 1) {
121 next_td = curr_td->next_td_virt;
122 }
123 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
124 }
125
126 if (req->mapped) {
127 dma_unmap_single(ep->udc->gadget.dev.parent,
128 req->req.dma, req->req.length,
129 ep_is_in(ep)
130 ? DMA_TO_DEVICE
131 : DMA_FROM_DEVICE);
132 req->req.dma = DMA_ADDR_INVALID;
133 req->mapped = 0;
134 } else
135 dma_sync_single_for_cpu(ep->udc->gadget.dev.parent,
136 req->req.dma, req->req.length,
137 ep_is_in(ep)
138 ? DMA_TO_DEVICE
139 : DMA_FROM_DEVICE);
140
141 if (status && (status != -ESHUTDOWN))
142 VDBG("complete %s req %p stat %d len %u/%u",
143 ep->ep.name, &req->req, status,
144 req->req.actual, req->req.length);
145
146 ep->stopped = 1;
147
148 spin_unlock(&ep->udc->lock);
149 /* complete() is from gadget layer,
150 * eg fsg->bulk_in_complete() */
151 if (req->req.complete)
152 req->req.complete(&ep->ep, &req->req);
153
154 spin_lock(&ep->udc->lock);
155 ep->stopped = stopped;
156 }
157
158 /*-----------------------------------------------------------------
159 * nuke(): delete all requests related to this ep
160 * called with spinlock held
161 *--------------------------------------------------------------*/
162 static void nuke(struct fsl_ep *ep, int status)
163 {
164 ep->stopped = 1;
165
166 /* Flush fifo */
167 fsl_ep_fifo_flush(&ep->ep);
168
169 /* Whether this eq has request linked */
170 while (!list_empty(&ep->queue)) {
171 struct fsl_req *req = NULL;
172
173 req = list_entry(ep->queue.next, struct fsl_req, queue);
174 done(ep, req, status);
175 }
176 }
177
178 /*------------------------------------------------------------------
179 Internal Hardware related function
180 ------------------------------------------------------------------*/
181
182 static int dr_controller_setup(struct fsl_udc *udc)
183 {
184 unsigned int tmp = 0, portctrl = 0, ctrl = 0;
185 unsigned long timeout;
186 #define FSL_UDC_RESET_TIMEOUT 1000
187
188 /* before here, make sure dr_regs has been initialized */
189 if (!udc)
190 return -EINVAL;
191
192 /* Stop and reset the usb controller */
193 tmp = fsl_readl(&dr_regs->usbcmd);
194 tmp &= ~USB_CMD_RUN_STOP;
195 fsl_writel(tmp, &dr_regs->usbcmd);
196
197 tmp = fsl_readl(&dr_regs->usbcmd);
198 tmp |= USB_CMD_CTRL_RESET;
199 fsl_writel(tmp, &dr_regs->usbcmd);
200
201 /* Wait for reset to complete */
202 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
203 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
204 if (time_after(jiffies, timeout)) {
205 ERR("udc reset timeout! \n");
206 return -ETIMEDOUT;
207 }
208 cpu_relax();
209 }
210
211 /* Set the controller as device mode */
212 tmp = fsl_readl(&dr_regs->usbmode);
213 tmp |= USB_MODE_CTRL_MODE_DEVICE;
214 /* Disable Setup Lockout */
215 tmp |= USB_MODE_SETUP_LOCK_OFF;
216 fsl_writel(tmp, &dr_regs->usbmode);
217
218 /* Clear the setup status */
219 fsl_writel(0, &dr_regs->usbsts);
220
221 tmp = udc->ep_qh_dma;
222 tmp &= USB_EP_LIST_ADDRESS_MASK;
223 fsl_writel(tmp, &dr_regs->endpointlistaddr);
224
225 VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
226 (int)udc->ep_qh, (int)tmp,
227 fsl_readl(&dr_regs->endpointlistaddr));
228
229 /* Config PHY interface */
230 portctrl = fsl_readl(&dr_regs->portsc1);
231 portctrl &= ~PORTSCX_PHY_TYPE_SEL;
232 switch (udc->phy_mode) {
233 case FSL_USB2_PHY_ULPI:
234 portctrl |= PORTSCX_PTS_ULPI;
235 break;
236 case FSL_USB2_PHY_UTMI:
237 case FSL_USB2_PHY_UTMI_WIDE:
238 portctrl |= PORTSCX_PTS_UTMI;
239 break;
240 case FSL_USB2_PHY_SERIAL:
241 portctrl |= PORTSCX_PTS_FSLS;
242 break;
243 default:
244 return -EINVAL;
245 }
246 fsl_writel(portctrl, &dr_regs->portsc1);
247
248 /* Config control enable i/o output, cpu endian register */
249 ctrl = __raw_readl(&usb_sys_regs->control);
250 ctrl |= USB_CTRL_IOENB;
251 __raw_writel(ctrl, &usb_sys_regs->control);
252
253 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
254 /* Turn on cache snooping hardware, since some PowerPC platforms
255 * wholly rely on hardware to deal with cache coherent. */
256
257 /* Setup Snooping for all the 4GB space */
258 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
259 __raw_writel(tmp, &usb_sys_regs->snoop1);
260 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
261 __raw_writel(tmp, &usb_sys_regs->snoop2);
262 #endif
263
264 return 0;
265 }
266
267 /* Enable DR irq and set controller to run state */
268 static void dr_controller_run(struct fsl_udc *udc)
269 {
270 u32 temp;
271
272 /* Enable DR irq reg */
273 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
274 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
275 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
276
277 fsl_writel(temp, &dr_regs->usbintr);
278
279 /* Clear stopped bit */
280 udc->stopped = 0;
281
282 /* Set the controller as device mode */
283 temp = fsl_readl(&dr_regs->usbmode);
284 temp |= USB_MODE_CTRL_MODE_DEVICE;
285 fsl_writel(temp, &dr_regs->usbmode);
286
287 /* Set controller to Run */
288 temp = fsl_readl(&dr_regs->usbcmd);
289 temp |= USB_CMD_RUN_STOP;
290 fsl_writel(temp, &dr_regs->usbcmd);
291
292 return;
293 }
294
295 static void dr_controller_stop(struct fsl_udc *udc)
296 {
297 unsigned int tmp;
298
299 /* disable all INTR */
300 fsl_writel(0, &dr_regs->usbintr);
301
302 /* Set stopped bit for isr */
303 udc->stopped = 1;
304
305 /* disable IO output */
306 /* usb_sys_regs->control = 0; */
307
308 /* set controller to Stop */
309 tmp = fsl_readl(&dr_regs->usbcmd);
310 tmp &= ~USB_CMD_RUN_STOP;
311 fsl_writel(tmp, &dr_regs->usbcmd);
312
313 return;
314 }
315
316 void dr_ep_setup(unsigned char ep_num, unsigned char dir, unsigned char ep_type)
317 {
318 unsigned int tmp_epctrl = 0;
319
320 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
321 if (dir) {
322 if (ep_num)
323 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
324 tmp_epctrl |= EPCTRL_TX_ENABLE;
325 tmp_epctrl |= ((unsigned int)(ep_type)
326 << EPCTRL_TX_EP_TYPE_SHIFT);
327 } else {
328 if (ep_num)
329 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
330 tmp_epctrl |= EPCTRL_RX_ENABLE;
331 tmp_epctrl |= ((unsigned int)(ep_type)
332 << EPCTRL_RX_EP_TYPE_SHIFT);
333 }
334
335 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
336 }
337
338 static void
339 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
340 {
341 u32 tmp_epctrl = 0;
342
343 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
344
345 if (value) {
346 /* set the stall bit */
347 if (dir)
348 tmp_epctrl |= EPCTRL_TX_EP_STALL;
349 else
350 tmp_epctrl |= EPCTRL_RX_EP_STALL;
351 } else {
352 /* clear the stall bit and reset data toggle */
353 if (dir) {
354 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
355 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
356 } else {
357 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
358 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
359 }
360 }
361 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
362 }
363
364 /* Get stall status of a specific ep
365 Return: 0: not stalled; 1:stalled */
366 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
367 {
368 u32 epctrl;
369
370 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
371 if (dir)
372 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
373 else
374 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
375 }
376
377 /********************************************************************
378 Internal Structure Build up functions
379 ********************************************************************/
380
381 /*------------------------------------------------------------------
382 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
383 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
384 * @mult: Mult field
385 ------------------------------------------------------------------*/
386 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
387 unsigned char dir, unsigned char ep_type,
388 unsigned int max_pkt_len,
389 unsigned int zlt, unsigned char mult)
390 {
391 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
392 unsigned int tmp = 0;
393
394 /* set the Endpoint Capabilites in QH */
395 switch (ep_type) {
396 case USB_ENDPOINT_XFER_CONTROL:
397 /* Interrupt On Setup (IOS). for control ep */
398 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
399 | EP_QUEUE_HEAD_IOS;
400 break;
401 case USB_ENDPOINT_XFER_ISOC:
402 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
403 | (mult << EP_QUEUE_HEAD_MULT_POS);
404 break;
405 case USB_ENDPOINT_XFER_BULK:
406 case USB_ENDPOINT_XFER_INT:
407 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
408 break;
409 default:
410 VDBG("error ep type is %d", ep_type);
411 return;
412 }
413 if (zlt)
414 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
415 p_QH->max_pkt_length = cpu_to_le32(tmp);
416
417 return;
418 }
419
420 /* Setup qh structure and ep register for ep0. */
421 static void ep0_setup(struct fsl_udc *udc)
422 {
423 /* the intialization of an ep includes: fields in QH, Regs,
424 * fsl_ep struct */
425 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
426 USB_MAX_CTRL_PAYLOAD, 0, 0);
427 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
428 USB_MAX_CTRL_PAYLOAD, 0, 0);
429 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
430 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
431
432 return;
433
434 }
435
436 /***********************************************************************
437 Endpoint Management Functions
438 ***********************************************************************/
439
440 /*-------------------------------------------------------------------------
441 * when configurations are set, or when interface settings change
442 * for example the do_set_interface() in gadget layer,
443 * the driver will enable or disable the relevant endpoints
444 * ep0 doesn't use this routine. It is always enabled.
445 -------------------------------------------------------------------------*/
446 static int fsl_ep_enable(struct usb_ep *_ep,
447 const struct usb_endpoint_descriptor *desc)
448 {
449 struct fsl_udc *udc = NULL;
450 struct fsl_ep *ep = NULL;
451 unsigned short max = 0;
452 unsigned char mult = 0, zlt;
453 int retval = -EINVAL;
454 unsigned long flags = 0;
455
456 ep = container_of(_ep, struct fsl_ep, ep);
457
458 /* catch various bogus parameters */
459 if (!_ep || !desc || ep->desc
460 || (desc->bDescriptorType != USB_DT_ENDPOINT))
461 return -EINVAL;
462
463 udc = ep->udc;
464
465 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
466 return -ESHUTDOWN;
467
468 max = le16_to_cpu(desc->wMaxPacketSize);
469
470 /* Disable automatic zlp generation. Driver is reponsible to indicate
471 * explicitly through req->req.zero. This is needed to enable multi-td
472 * request. */
473 zlt = 1;
474
475 /* Assume the max packet size from gadget is always correct */
476 switch (desc->bmAttributes & 0x03) {
477 case USB_ENDPOINT_XFER_CONTROL:
478 case USB_ENDPOINT_XFER_BULK:
479 case USB_ENDPOINT_XFER_INT:
480 /* mult = 0. Execute N Transactions as demonstrated by
481 * the USB variable length packet protocol where N is
482 * computed using the Maximum Packet Length (dQH) and
483 * the Total Bytes field (dTD) */
484 mult = 0;
485 break;
486 case USB_ENDPOINT_XFER_ISOC:
487 /* Calculate transactions needed for high bandwidth iso */
488 mult = (unsigned char)(1 + ((max >> 11) & 0x03));
489 max = max & 0x8ff; /* bit 0~10 */
490 /* 3 transactions at most */
491 if (mult > 3)
492 goto en_done;
493 break;
494 default:
495 goto en_done;
496 }
497
498 spin_lock_irqsave(&udc->lock, flags);
499 ep->ep.maxpacket = max;
500 ep->desc = desc;
501 ep->stopped = 0;
502
503 /* Controller related setup */
504 /* Init EPx Queue Head (Ep Capabilites field in QH
505 * according to max, zlt, mult) */
506 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
507 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
508 ? USB_SEND : USB_RECV),
509 (unsigned char) (desc->bmAttributes
510 & USB_ENDPOINT_XFERTYPE_MASK),
511 max, zlt, mult);
512
513 /* Init endpoint ctrl register */
514 dr_ep_setup((unsigned char) ep_index(ep),
515 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
516 ? USB_SEND : USB_RECV),
517 (unsigned char) (desc->bmAttributes
518 & USB_ENDPOINT_XFERTYPE_MASK));
519
520 spin_unlock_irqrestore(&udc->lock, flags);
521 retval = 0;
522
523 VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
524 ep->desc->bEndpointAddress & 0x0f,
525 (desc->bEndpointAddress & USB_DIR_IN)
526 ? "in" : "out", max);
527 en_done:
528 return retval;
529 }
530
531 /*---------------------------------------------------------------------
532 * @ep : the ep being unconfigured. May not be ep0
533 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
534 *---------------------------------------------------------------------*/
535 static int fsl_ep_disable(struct usb_ep *_ep)
536 {
537 struct fsl_udc *udc = NULL;
538 struct fsl_ep *ep = NULL;
539 unsigned long flags = 0;
540 u32 epctrl;
541 int ep_num;
542
543 ep = container_of(_ep, struct fsl_ep, ep);
544 if (!_ep || !ep->desc) {
545 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
546 return -EINVAL;
547 }
548
549 /* disable ep on controller */
550 ep_num = ep_index(ep);
551 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
552 if (ep_is_in(ep))
553 epctrl &= ~EPCTRL_TX_ENABLE;
554 else
555 epctrl &= ~EPCTRL_RX_ENABLE;
556 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
557
558 udc = (struct fsl_udc *)ep->udc;
559 spin_lock_irqsave(&udc->lock, flags);
560
561 /* nuke all pending requests (does flush) */
562 nuke(ep, -ESHUTDOWN);
563
564 ep->desc = 0;
565 ep->stopped = 1;
566 spin_unlock_irqrestore(&udc->lock, flags);
567
568 VDBG("disabled %s OK", _ep->name);
569 return 0;
570 }
571
572 /*---------------------------------------------------------------------
573 * allocate a request object used by this endpoint
574 * the main operation is to insert the req->queue to the eq->queue
575 * Returns the request, or null if one could not be allocated
576 *---------------------------------------------------------------------*/
577 static struct usb_request *
578 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
579 {
580 struct fsl_req *req = NULL;
581
582 req = kzalloc(sizeof *req, gfp_flags);
583 if (!req)
584 return NULL;
585
586 req->req.dma = DMA_ADDR_INVALID;
587 INIT_LIST_HEAD(&req->queue);
588
589 return &req->req;
590 }
591
592 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
593 {
594 struct fsl_req *req = NULL;
595
596 req = container_of(_req, struct fsl_req, req);
597
598 if (_req)
599 kfree(req);
600 }
601
602 /*------------------------------------------------------------------
603 * Allocate an I/O buffer
604 *---------------------------------------------------------------------*/
605 static void *fsl_alloc_buffer(struct usb_ep *_ep, unsigned bytes,
606 dma_addr_t *dma, gfp_t gfp_flags)
607 {
608 struct fsl_ep *ep;
609
610 if (!_ep)
611 return NULL;
612
613 ep = container_of(_ep, struct fsl_ep, ep);
614
615 return dma_alloc_coherent(ep->udc->gadget.dev.parent,
616 bytes, dma, gfp_flags);
617 }
618
619 /*------------------------------------------------------------------
620 * frees an i/o buffer
621 *---------------------------------------------------------------------*/
622 static void fsl_free_buffer(struct usb_ep *_ep, void *buf,
623 dma_addr_t dma, unsigned bytes)
624 {
625 struct fsl_ep *ep;
626
627 if (!_ep)
628 return NULL;
629
630 ep = container_of(_ep, struct fsl_ep, ep);
631
632 dma_free_coherent(ep->udc->gadget.dev.parent, bytes, buf, dma);
633 }
634
635 /*-------------------------------------------------------------------------*/
636 static int fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
637 {
638 int i = ep_index(ep) * 2 + ep_is_in(ep);
639 u32 temp, bitmask, tmp_stat;
640 struct ep_queue_head *dQH = &ep->udc->ep_qh[i];
641
642 /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
643 VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
644
645 bitmask = ep_is_in(ep)
646 ? (1 << (ep_index(ep) + 16))
647 : (1 << (ep_index(ep)));
648
649 /* check if the pipe is empty */
650 if (!(list_empty(&ep->queue))) {
651 /* Add td to the end */
652 struct fsl_req *lastreq;
653 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
654 lastreq->tail->next_td_ptr =
655 cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK);
656 /* Read prime bit, if 1 goto done */
657 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
658 goto out;
659
660 do {
661 /* Set ATDTW bit in USBCMD */
662 temp = fsl_readl(&dr_regs->usbcmd);
663 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
664
665 /* Read correct status bit */
666 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
667
668 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
669
670 /* Write ATDTW bit to 0 */
671 temp = fsl_readl(&dr_regs->usbcmd);
672 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
673
674 if (tmp_stat)
675 goto out;
676 }
677
678 /* Write dQH next pointer and terminate bit to 0 */
679 temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
680 dQH->next_dtd_ptr = cpu_to_le32(temp);
681
682 /* Clear active and halt bit */
683 temp = cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
684 | EP_QUEUE_HEAD_STATUS_HALT));
685 dQH->size_ioc_int_sts &= temp;
686
687 /* Prime endpoint by writing 1 to ENDPTPRIME */
688 temp = ep_is_in(ep)
689 ? (1 << (ep_index(ep) + 16))
690 : (1 << (ep_index(ep)));
691 fsl_writel(temp, &dr_regs->endpointprime);
692 out:
693 return 0;
694 }
695
696 /* Fill in the dTD structure
697 * @req: request that the transfer belongs to
698 * @length: return actually data length of the dTD
699 * @dma: return dma address of the dTD
700 * @is_last: return flag if it is the last dTD of the request
701 * return: pointer to the built dTD */
702 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
703 dma_addr_t *dma, int *is_last)
704 {
705 u32 swap_temp;
706 struct ep_td_struct *dtd;
707
708 /* how big will this transfer be? */
709 *length = min(req->req.length - req->req.actual,
710 (unsigned)EP_MAX_LENGTH_TRANSFER);
711
712 dtd = dma_pool_alloc(udc_controller->td_pool, GFP_KERNEL, dma);
713 if (dtd == NULL)
714 return dtd;
715
716 dtd->td_dma = *dma;
717 /* Clear reserved field */
718 swap_temp = cpu_to_le32(dtd->size_ioc_sts);
719 swap_temp &= ~DTD_RESERVED_FIELDS;
720 dtd->size_ioc_sts = cpu_to_le32(swap_temp);
721
722 /* Init all of buffer page pointers */
723 swap_temp = (u32) (req->req.dma + req->req.actual);
724 dtd->buff_ptr0 = cpu_to_le32(swap_temp);
725 dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000);
726 dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000);
727 dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000);
728 dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000);
729
730 req->req.actual += *length;
731
732 /* zlp is needed if req->req.zero is set */
733 if (req->req.zero) {
734 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
735 *is_last = 1;
736 else
737 *is_last = 0;
738 } else if (req->req.length == req->req.actual)
739 *is_last = 1;
740 else
741 *is_last = 0;
742
743 if ((*is_last) == 0)
744 VDBG("multi-dtd request!\n");
745 /* Fill in the transfer size; set active bit */
746 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
747
748 /* Enable interrupt for the last dtd of a request */
749 if (*is_last && !req->req.no_interrupt)
750 swap_temp |= DTD_IOC;
751
752 dtd->size_ioc_sts = cpu_to_le32(swap_temp);
753
754 mb();
755
756 VDBG("length = %d address= 0x%x", *length, (int)*dma);
757
758 return dtd;
759 }
760
761 /* Generate dtd chain for a request */
762 static int fsl_req_to_dtd(struct fsl_req *req)
763 {
764 unsigned count;
765 int is_last;
766 int is_first =1;
767 struct ep_td_struct *last_dtd = NULL, *dtd;
768 dma_addr_t dma;
769
770 do {
771 dtd = fsl_build_dtd(req, &count, &dma, &is_last);
772 if (dtd == NULL)
773 return -ENOMEM;
774
775 if (is_first) {
776 is_first = 0;
777 req->head = dtd;
778 } else {
779 last_dtd->next_td_ptr = cpu_to_le32(dma);
780 last_dtd->next_td_virt = dtd;
781 }
782 last_dtd = dtd;
783
784 req->dtd_count++;
785 } while (!is_last);
786
787 dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE);
788
789 req->tail = dtd;
790
791 return 0;
792 }
793
794 /* queues (submits) an I/O request to an endpoint */
795 static int
796 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
797 {
798 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
799 struct fsl_req *req = container_of(_req, struct fsl_req, req);
800 struct fsl_udc *udc;
801 unsigned long flags;
802 int is_iso = 0;
803
804 /* catch various bogus parameters */
805 if (!_req || !req->req.complete || !req->req.buf
806 || !list_empty(&req->queue)) {
807 VDBG("%s, bad params\n", __FUNCTION__);
808 return -EINVAL;
809 }
810 if (!_ep || (!ep->desc && ep_index(ep))) {
811 VDBG("%s, bad ep\n", __FUNCTION__);
812 return -EINVAL;
813 }
814 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
815 if (req->req.length > ep->ep.maxpacket)
816 return -EMSGSIZE;
817 is_iso = 1;
818 }
819
820 udc = ep->udc;
821 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
822 return -ESHUTDOWN;
823
824 req->ep = ep;
825
826 /* map virtual address to hardware */
827 if (req->req.dma == DMA_ADDR_INVALID) {
828 req->req.dma = dma_map_single(ep->udc->gadget.dev.parent,
829 req->req.buf,
830 req->req.length, ep_is_in(ep)
831 ? DMA_TO_DEVICE
832 : DMA_FROM_DEVICE);
833 req->mapped = 1;
834 } else {
835 dma_sync_single_for_device(ep->udc->gadget.dev.parent,
836 req->req.dma, req->req.length,
837 ep_is_in(ep)
838 ? DMA_TO_DEVICE
839 : DMA_FROM_DEVICE);
840 req->mapped = 0;
841 }
842
843 req->req.status = -EINPROGRESS;
844 req->req.actual = 0;
845 req->dtd_count = 0;
846
847 spin_lock_irqsave(&udc->lock, flags);
848
849 /* build dtds and push them to device queue */
850 if (!fsl_req_to_dtd(req)) {
851 fsl_queue_td(ep, req);
852 } else {
853 spin_unlock_irqrestore(&udc->lock, flags);
854 return -ENOMEM;
855 }
856
857 /* Update ep0 state */
858 if ((ep_index(ep) == 0))
859 udc->ep0_state = DATA_STATE_XMIT;
860
861 /* irq handler advances the queue */
862 if (req != NULL)
863 list_add_tail(&req->queue, &ep->queue);
864 spin_unlock_irqrestore(&udc->lock, flags);
865
866 return 0;
867 }
868
869 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
870 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
871 {
872 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
873 struct fsl_req *req;
874 unsigned long flags;
875 int ep_num, stopped, ret = 0;
876 u32 epctrl;
877
878 if (!_ep || !_req)
879 return -EINVAL;
880
881 spin_lock_irqsave(&ep->udc->lock, flags);
882 stopped = ep->stopped;
883
884 /* Stop the ep before we deal with the queue */
885 ep->stopped = 1;
886 ep_num = ep_index(ep);
887 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
888 if (ep_is_in(ep))
889 epctrl &= ~EPCTRL_TX_ENABLE;
890 else
891 epctrl &= ~EPCTRL_RX_ENABLE;
892 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
893
894 /* make sure it's actually queued on this endpoint */
895 list_for_each_entry(req, &ep->queue, queue) {
896 if (&req->req == _req)
897 break;
898 }
899 if (&req->req != _req) {
900 ret = -EINVAL;
901 goto out;
902 }
903
904 /* The request is in progress, or completed but not dequeued */
905 if (ep->queue.next == &req->queue) {
906 _req->status = -ECONNRESET;
907 fsl_ep_fifo_flush(_ep); /* flush current transfer */
908
909 /* The request isn't the last request in this ep queue */
910 if (req->queue.next != &ep->queue) {
911 struct ep_queue_head *qh;
912 struct fsl_req *next_req;
913
914 qh = ep->qh;
915 next_req = list_entry(req->queue.next, struct fsl_req,
916 queue);
917
918 /* Point the QH to the first TD of next request */
919 fsl_writel((u32) next_req->head, &qh->curr_dtd_ptr);
920 }
921
922 /* The request hasn't been processed, patch up the TD chain */
923 } else {
924 struct fsl_req *prev_req;
925
926 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
927 fsl_writel(fsl_readl(&req->tail->next_td_ptr),
928 &prev_req->tail->next_td_ptr);
929
930 }
931
932 done(ep, req, -ECONNRESET);
933
934 /* Enable EP */
935 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
936 if (ep_is_in(ep))
937 epctrl |= EPCTRL_TX_ENABLE;
938 else
939 epctrl |= EPCTRL_RX_ENABLE;
940 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
941 ep->stopped = stopped;
942
943 spin_unlock_irqrestore(&ep->udc->lock, flags);
944 return ret;
945 }
946
947 /*-------------------------------------------------------------------------*/
948
949 /*-----------------------------------------------------------------
950 * modify the endpoint halt feature
951 * @ep: the non-isochronous endpoint being stalled
952 * @value: 1--set halt 0--clear halt
953 * Returns zero, or a negative error code.
954 *----------------------------------------------------------------*/
955 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
956 {
957 struct fsl_ep *ep = NULL;
958 unsigned long flags = 0;
959 int status = -EOPNOTSUPP; /* operation not supported */
960 unsigned char ep_dir = 0, ep_num = 0;
961 struct fsl_udc *udc = NULL;
962
963 ep = container_of(_ep, struct fsl_ep, ep);
964 udc = ep->udc;
965 if (!_ep || !ep->desc) {
966 status = -EINVAL;
967 goto out;
968 }
969
970 if (ep->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
971 status = -EOPNOTSUPP;
972 goto out;
973 }
974
975 /* Attempt to halt IN ep will fail if any transfer requests
976 * are still queue */
977 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
978 status = -EAGAIN;
979 goto out;
980 }
981
982 status = 0;
983 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
984 ep_num = (unsigned char)(ep_index(ep));
985 spin_lock_irqsave(&ep->udc->lock, flags);
986 dr_ep_change_stall(ep_num, ep_dir, value);
987 spin_unlock_irqrestore(&ep->udc->lock, flags);
988
989 if (ep_index(ep) == 0) {
990 udc->ep0_state = WAIT_FOR_SETUP;
991 udc->ep0_dir = 0;
992 }
993 out:
994 VDBG(" %s %s halt stat %d", ep->ep.name,
995 value ? "set" : "clear", status);
996
997 return status;
998 }
999
1000 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1001 {
1002 struct fsl_ep *ep;
1003 int ep_num, ep_dir;
1004 u32 bits;
1005 unsigned long timeout;
1006 #define FSL_UDC_FLUSH_TIMEOUT 1000
1007
1008 if (!_ep) {
1009 return;
1010 } else {
1011 ep = container_of(_ep, struct fsl_ep, ep);
1012 if (!ep->desc)
1013 return;
1014 }
1015 ep_num = ep_index(ep);
1016 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1017
1018 if (ep_num == 0)
1019 bits = (1 << 16) | 1;
1020 else if (ep_dir == USB_SEND)
1021 bits = 1 << (16 + ep_num);
1022 else
1023 bits = 1 << ep_num;
1024
1025 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1026 do {
1027 fsl_writel(bits, &dr_regs->endptflush);
1028
1029 /* Wait until flush complete */
1030 while (fsl_readl(&dr_regs->endptflush)) {
1031 if (time_after(jiffies, timeout)) {
1032 ERR("ep flush timeout\n");
1033 return;
1034 }
1035 cpu_relax();
1036 }
1037 /* See if we need to flush again */
1038 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1039 }
1040
1041 static struct usb_ep_ops fsl_ep_ops = {
1042 .enable = fsl_ep_enable,
1043 .disable = fsl_ep_disable,
1044
1045 .alloc_request = fsl_alloc_request,
1046 .free_request = fsl_free_request,
1047
1048 .alloc_buffer = fsl_alloc_buffer,
1049 .free_buffer = fsl_free_buffer,
1050
1051 .queue = fsl_ep_queue,
1052 .dequeue = fsl_ep_dequeue,
1053
1054 .set_halt = fsl_ep_set_halt,
1055 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1056 };
1057
1058 /*-------------------------------------------------------------------------
1059 Gadget Driver Layer Operations
1060 -------------------------------------------------------------------------*/
1061
1062 /*----------------------------------------------------------------------
1063 * Get the current frame number (from DR frame_index Reg )
1064 *----------------------------------------------------------------------*/
1065 static int fsl_get_frame(struct usb_gadget *gadget)
1066 {
1067 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1068 }
1069
1070 /*-----------------------------------------------------------------------
1071 * Tries to wake up the host connected to this gadget
1072 -----------------------------------------------------------------------*/
1073 static int fsl_wakeup(struct usb_gadget *gadget)
1074 {
1075 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1076 u32 portsc;
1077
1078 /* Remote wakeup feature not enabled by host */
1079 if (!udc->remote_wakeup)
1080 return -ENOTSUPP;
1081
1082 portsc = fsl_readl(&dr_regs->portsc1);
1083 /* not suspended? */
1084 if (!(portsc & PORTSCX_PORT_SUSPEND))
1085 return 0;
1086 /* trigger force resume */
1087 portsc |= PORTSCX_PORT_FORCE_RESUME;
1088 fsl_writel(portsc, &dr_regs->portsc1);
1089 return 0;
1090 }
1091
1092 static int can_pullup(struct fsl_udc *udc)
1093 {
1094 return udc->driver && udc->softconnect && udc->vbus_active;
1095 }
1096
1097 /* Notify controller that VBUS is powered, Called by whatever
1098 detects VBUS sessions */
1099 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1100 {
1101 struct fsl_udc *udc;
1102 unsigned long flags;
1103
1104 udc = container_of(gadget, struct fsl_udc, gadget);
1105 spin_lock_irqsave(&udc->lock, flags);
1106 VDBG("VBUS %s\n", is_active ? "on" : "off");
1107 udc->vbus_active = (is_active != 0);
1108 if (can_pullup(udc))
1109 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1110 &dr_regs->usbcmd);
1111 else
1112 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1113 &dr_regs->usbcmd);
1114 spin_unlock_irqrestore(&udc->lock, flags);
1115 return 0;
1116 }
1117
1118 /* constrain controller's VBUS power usage
1119 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1120 * reporting how much power the device may consume. For example, this
1121 * could affect how quickly batteries are recharged.
1122 *
1123 * Returns zero on success, else negative errno.
1124 */
1125 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1126 {
1127 #ifdef CONFIG_USB_OTG
1128 struct fsl_udc *udc;
1129
1130 udc = container_of(gadget, struct fsl_udc, gadget);
1131
1132 if (udc->transceiver)
1133 return otg_set_power(udc->transceiver, mA);
1134 #endif
1135 return -ENOTSUPP;
1136 }
1137
1138 /* Change Data+ pullup status
1139 * this func is used by usb_gadget_connect/disconnet
1140 */
1141 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1142 {
1143 struct fsl_udc *udc;
1144
1145 udc = container_of(gadget, struct fsl_udc, gadget);
1146 udc->softconnect = (is_on != 0);
1147 if (can_pullup(udc))
1148 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1149 &dr_regs->usbcmd);
1150 else
1151 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1152 &dr_regs->usbcmd);
1153
1154 return 0;
1155 }
1156
1157 /* defined in usb_gadget.h */
1158 static struct usb_gadget_ops fsl_gadget_ops = {
1159 .get_frame = fsl_get_frame,
1160 .wakeup = fsl_wakeup,
1161 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1162 .vbus_session = fsl_vbus_session,
1163 .vbus_draw = fsl_vbus_draw,
1164 .pullup = fsl_pullup,
1165 };
1166
1167 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1168 on new transaction */
1169 static void ep0stall(struct fsl_udc *udc)
1170 {
1171 u32 tmp;
1172
1173 /* must set tx and rx to stall at the same time */
1174 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1175 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1176 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1177 udc->ep0_state = WAIT_FOR_SETUP;
1178 udc->ep0_dir = 0;
1179 }
1180
1181 /* Prime a status phase for ep0 */
1182 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1183 {
1184 struct fsl_req *req = udc->status_req;
1185 struct fsl_ep *ep;
1186 int status = 0;
1187
1188 if (direction == EP_DIR_IN)
1189 udc->ep0_dir = USB_DIR_IN;
1190 else
1191 udc->ep0_dir = USB_DIR_OUT;
1192
1193 ep = &udc->eps[0];
1194 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1195
1196 req->ep = ep;
1197 req->req.length = 0;
1198 req->req.status = -EINPROGRESS;
1199 req->req.actual = 0;
1200 req->req.complete = NULL;
1201 req->dtd_count = 0;
1202
1203 if (fsl_req_to_dtd(req) == 0)
1204 status = fsl_queue_td(ep, req);
1205 else
1206 return -ENOMEM;
1207
1208 if (status)
1209 ERR("Can't queue ep0 status request \n");
1210 list_add_tail(&req->queue, &ep->queue);
1211
1212 return status;
1213 }
1214
1215 static inline int udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1216 {
1217 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1218
1219 if (!ep->name)
1220 return 0;
1221
1222 nuke(ep, -ESHUTDOWN);
1223
1224 return 0;
1225 }
1226
1227 /*
1228 * ch9 Set address
1229 */
1230 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1231 {
1232 /* Save the new address to device struct */
1233 udc->device_address = (u8) value;
1234 /* Update usb state */
1235 udc->usb_state = USB_STATE_ADDRESS;
1236 /* Status phase */
1237 if (ep0_prime_status(udc, EP_DIR_IN))
1238 ep0stall(udc);
1239 }
1240
1241 /*
1242 * ch9 Get status
1243 */
1244 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1245 u16 index, u16 length)
1246 {
1247 u16 tmp = 0; /* Status, cpu endian */
1248
1249 struct fsl_req *req;
1250 struct fsl_ep *ep;
1251 int status = 0;
1252
1253 ep = &udc->eps[0];
1254
1255 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1256 /* Get device status */
1257 tmp = 1 << USB_DEVICE_SELF_POWERED;
1258 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1259 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1260 /* Get interface status */
1261 /* We don't have interface information in udc driver */
1262 tmp = 0;
1263 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1264 /* Get endpoint status */
1265 struct fsl_ep *target_ep;
1266
1267 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1268
1269 /* stall if endpoint doesn't exist */
1270 if (!target_ep->desc)
1271 goto stall;
1272 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1273 << USB_ENDPOINT_HALT;
1274 }
1275
1276 udc->ep0_dir = USB_DIR_IN;
1277 /* Borrow the per device status_req */
1278 req = udc->status_req;
1279 /* Fill in the reqest structure */
1280 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1281 req->ep = ep;
1282 req->req.length = 2;
1283 req->req.status = -EINPROGRESS;
1284 req->req.actual = 0;
1285 req->req.complete = NULL;
1286 req->dtd_count = 0;
1287
1288 /* prime the data phase */
1289 if ((fsl_req_to_dtd(req) == 0))
1290 status = fsl_queue_td(ep, req);
1291 else /* no mem */
1292 goto stall;
1293
1294 if (status) {
1295 ERR("Can't respond to getstatus request \n");
1296 goto stall;
1297 }
1298 list_add_tail(&req->queue, &ep->queue);
1299 udc->ep0_state = DATA_STATE_XMIT;
1300 return;
1301 stall:
1302 ep0stall(udc);
1303 }
1304
1305 static void setup_received_irq(struct fsl_udc *udc,
1306 struct usb_ctrlrequest *setup)
1307 {
1308 u16 wValue = le16_to_cpu(setup->wValue);
1309 u16 wIndex = le16_to_cpu(setup->wIndex);
1310 u16 wLength = le16_to_cpu(setup->wLength);
1311
1312 udc_reset_ep_queue(udc, 0);
1313
1314 switch (setup->bRequest) {
1315 /* Request that need Data+Status phase from udc */
1316 case USB_REQ_GET_STATUS:
1317 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_STANDARD))
1318 != (USB_DIR_IN | USB_TYPE_STANDARD))
1319 break;
1320 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1321 break;
1322
1323 /* Requests that need Status phase from udc */
1324 case USB_REQ_SET_ADDRESS:
1325 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1326 | USB_RECIP_DEVICE))
1327 break;
1328 ch9setaddress(udc, wValue, wIndex, wLength);
1329 break;
1330
1331 /* Handled by udc, no data, status by udc */
1332 case USB_REQ_CLEAR_FEATURE:
1333 case USB_REQ_SET_FEATURE:
1334 { /* status transaction */
1335 int rc = -EOPNOTSUPP;
1336
1337 if ((setup->bRequestType & USB_RECIP_MASK)
1338 == USB_RECIP_ENDPOINT) {
1339 int pipe = get_pipe_by_windex(wIndex);
1340 struct fsl_ep *ep;
1341
1342 if (wValue != 0 || wLength != 0 || pipe > udc->max_ep)
1343 break;
1344 ep = get_ep_by_pipe(udc, pipe);
1345
1346 spin_unlock(&udc->lock);
1347 rc = fsl_ep_set_halt(&ep->ep,
1348 (setup->bRequest == USB_REQ_SET_FEATURE)
1349 ? 1 : 0);
1350 spin_lock(&udc->lock);
1351
1352 } else if ((setup->bRequestType & USB_RECIP_MASK)
1353 == USB_RECIP_DEVICE) {
1354 /* Note: The driver has not include OTG support yet.
1355 * This will be set when OTG support is added */
1356 if (!udc->gadget.is_otg)
1357 break;
1358 else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE)
1359 udc->gadget.b_hnp_enable = 1;
1360 else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
1361 udc->gadget.a_hnp_support = 1;
1362 else if (setup->bRequest ==
1363 USB_DEVICE_A_ALT_HNP_SUPPORT)
1364 udc->gadget.a_alt_hnp_support = 1;
1365 rc = 0;
1366 }
1367 if (rc == 0) {
1368 if (ep0_prime_status(udc, EP_DIR_IN))
1369 ep0stall(udc);
1370 }
1371 break;
1372 }
1373 /* Requests handled by gadget */
1374 default:
1375 if (wLength) {
1376 /* Data phase from gadget, status phase from udc */
1377 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1378 ? USB_DIR_IN : USB_DIR_OUT;
1379 spin_unlock(&udc->lock);
1380 if (udc->driver->setup(&udc->gadget,
1381 &udc->local_setup_buff) < 0)
1382 ep0stall(udc);
1383 spin_lock(&udc->lock);
1384 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1385 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1386
1387 } else {
1388 /* No data phase, IN status from gadget */
1389 udc->ep0_dir = USB_DIR_IN;
1390 spin_unlock(&udc->lock);
1391 if (udc->driver->setup(&udc->gadget,
1392 &udc->local_setup_buff) < 0)
1393 ep0stall(udc);
1394 spin_lock(&udc->lock);
1395 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1396 }
1397 break;
1398 }
1399 }
1400
1401 /* Process request for Data or Status phase of ep0
1402 * prime status phase if needed */
1403 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1404 struct fsl_req *req)
1405 {
1406 if (udc->usb_state == USB_STATE_ADDRESS) {
1407 /* Set the new address */
1408 u32 new_address = (u32) udc->device_address;
1409 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1410 &dr_regs->deviceaddr);
1411 }
1412
1413 done(ep0, req, 0);
1414
1415 switch (udc->ep0_state) {
1416 case DATA_STATE_XMIT:
1417 /* receive status phase */
1418 if (ep0_prime_status(udc, EP_DIR_OUT))
1419 ep0stall(udc);
1420 break;
1421 case DATA_STATE_RECV:
1422 /* send status phase */
1423 if (ep0_prime_status(udc, EP_DIR_IN))
1424 ep0stall(udc);
1425 break;
1426 case WAIT_FOR_OUT_STATUS:
1427 udc->ep0_state = WAIT_FOR_SETUP;
1428 break;
1429 case WAIT_FOR_SETUP:
1430 ERR("Unexpect ep0 packets \n");
1431 break;
1432 default:
1433 ep0stall(udc);
1434 break;
1435 }
1436 }
1437
1438 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1439 * being corrupted by another incoming setup packet */
1440 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1441 {
1442 u32 temp;
1443 struct ep_queue_head *qh;
1444
1445 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1446
1447 /* Clear bit in ENDPTSETUPSTAT */
1448 temp = fsl_readl(&dr_regs->endptsetupstat);
1449 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1450
1451 /* while a hazard exists when setup package arrives */
1452 do {
1453 /* Set Setup Tripwire */
1454 temp = fsl_readl(&dr_regs->usbcmd);
1455 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1456
1457 /* Copy the setup packet to local buffer */
1458 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1459 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1460
1461 /* Clear Setup Tripwire */
1462 temp = fsl_readl(&dr_regs->usbcmd);
1463 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1464 }
1465
1466 /* process-ep_req(): free the completed Tds for this req */
1467 static int process_ep_req(struct fsl_udc *udc, int pipe,
1468 struct fsl_req *curr_req)
1469 {
1470 struct ep_td_struct *curr_td;
1471 int td_complete, actual, remaining_length, j, tmp;
1472 int status = 0;
1473 int errors = 0;
1474 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1475 int direction = pipe % 2;
1476
1477 curr_td = curr_req->head;
1478 td_complete = 0;
1479 actual = curr_req->req.length;
1480
1481 for (j = 0; j < curr_req->dtd_count; j++) {
1482 remaining_length = (le32_to_cpu(curr_td->size_ioc_sts)
1483 & DTD_PACKET_SIZE)
1484 >> DTD_LENGTH_BIT_POS;
1485 actual -= remaining_length;
1486
1487 if ((errors = le32_to_cpu(curr_td->size_ioc_sts) &
1488 DTD_ERROR_MASK)) {
1489 if (errors & DTD_STATUS_HALTED) {
1490 ERR("dTD error %08x QH=%d\n", errors, pipe);
1491 /* Clear the errors and Halt condition */
1492 tmp = le32_to_cpu(curr_qh->size_ioc_int_sts);
1493 tmp &= ~errors;
1494 curr_qh->size_ioc_int_sts = cpu_to_le32(tmp);
1495 status = -EPIPE;
1496 /* FIXME: continue with next queued TD? */
1497
1498 break;
1499 }
1500 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1501 VDBG("Transfer overflow");
1502 status = -EPROTO;
1503 break;
1504 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1505 VDBG("ISO error");
1506 status = -EILSEQ;
1507 break;
1508 } else
1509 ERR("Unknown error has occured (0x%x)!\r\n",
1510 errors);
1511
1512 } else if (le32_to_cpu(curr_td->size_ioc_sts)
1513 & DTD_STATUS_ACTIVE) {
1514 VDBG("Request not complete");
1515 status = REQ_UNCOMPLETE;
1516 return status;
1517 } else if (remaining_length) {
1518 if (direction) {
1519 VDBG("Transmit dTD remaining length not zero");
1520 status = -EPROTO;
1521 break;
1522 } else {
1523 td_complete++;
1524 break;
1525 }
1526 } else {
1527 td_complete++;
1528 VDBG("dTD transmitted successful ");
1529 }
1530
1531 if (j != curr_req->dtd_count - 1)
1532 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1533 }
1534
1535 if (status)
1536 return status;
1537
1538 curr_req->req.actual = actual;
1539
1540 return 0;
1541 }
1542
1543 /* Process a DTD completion interrupt */
1544 static void dtd_complete_irq(struct fsl_udc *udc)
1545 {
1546 u32 bit_pos;
1547 int i, ep_num, direction, bit_mask, status;
1548 struct fsl_ep *curr_ep;
1549 struct fsl_req *curr_req, *temp_req;
1550
1551 /* Clear the bits in the register */
1552 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1553 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1554
1555 if (!bit_pos)
1556 return;
1557
1558 for (i = 0; i < udc->max_ep * 2; i++) {
1559 ep_num = i >> 1;
1560 direction = i % 2;
1561
1562 bit_mask = 1 << (ep_num + 16 * direction);
1563
1564 if (!(bit_pos & bit_mask))
1565 continue;
1566
1567 curr_ep = get_ep_by_pipe(udc, i);
1568
1569 /* If the ep is configured */
1570 if (curr_ep->name == NULL) {
1571 WARN("Invalid EP?");
1572 continue;
1573 }
1574
1575 /* process the req queue until an uncomplete request */
1576 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1577 queue) {
1578 status = process_ep_req(udc, i, curr_req);
1579
1580 VDBG("status of process_ep_req= %d, ep = %d",
1581 status, ep_num);
1582 if (status == REQ_UNCOMPLETE)
1583 break;
1584 /* write back status to req */
1585 curr_req->req.status = status;
1586
1587 if (ep_num == 0) {
1588 ep0_req_complete(udc, curr_ep, curr_req);
1589 break;
1590 } else
1591 done(curr_ep, curr_req, status);
1592 }
1593 }
1594 }
1595
1596 /* Process a port change interrupt */
1597 static void port_change_irq(struct fsl_udc *udc)
1598 {
1599 u32 speed;
1600
1601 if (udc->bus_reset)
1602 udc->bus_reset = 0;
1603
1604 /* Bus resetting is finished */
1605 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
1606 /* Get the speed */
1607 speed = (fsl_readl(&dr_regs->portsc1)
1608 & PORTSCX_PORT_SPEED_MASK);
1609 switch (speed) {
1610 case PORTSCX_PORT_SPEED_HIGH:
1611 udc->gadget.speed = USB_SPEED_HIGH;
1612 break;
1613 case PORTSCX_PORT_SPEED_FULL:
1614 udc->gadget.speed = USB_SPEED_FULL;
1615 break;
1616 case PORTSCX_PORT_SPEED_LOW:
1617 udc->gadget.speed = USB_SPEED_LOW;
1618 break;
1619 default:
1620 udc->gadget.speed = USB_SPEED_UNKNOWN;
1621 break;
1622 }
1623 }
1624
1625 /* Update USB state */
1626 if (!udc->resume_state)
1627 udc->usb_state = USB_STATE_DEFAULT;
1628 }
1629
1630 /* Process suspend interrupt */
1631 static void suspend_irq(struct fsl_udc *udc)
1632 {
1633 udc->resume_state = udc->usb_state;
1634 udc->usb_state = USB_STATE_SUSPENDED;
1635
1636 /* report suspend to the driver, serial.c does not support this */
1637 if (udc->driver->suspend)
1638 udc->driver->suspend(&udc->gadget);
1639 }
1640
1641 static void bus_resume(struct fsl_udc *udc)
1642 {
1643 udc->usb_state = udc->resume_state;
1644 udc->resume_state = 0;
1645
1646 /* report resume to the driver, serial.c does not support this */
1647 if (udc->driver->resume)
1648 udc->driver->resume(&udc->gadget);
1649 }
1650
1651 /* Clear up all ep queues */
1652 static int reset_queues(struct fsl_udc *udc)
1653 {
1654 u8 pipe;
1655
1656 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1657 udc_reset_ep_queue(udc, pipe);
1658
1659 /* report disconnect; the driver is already quiesced */
1660 udc->driver->disconnect(&udc->gadget);
1661
1662 return 0;
1663 }
1664
1665 /* Process reset interrupt */
1666 static void reset_irq(struct fsl_udc *udc)
1667 {
1668 u32 temp;
1669 unsigned long timeout;
1670
1671 /* Clear the device address */
1672 temp = fsl_readl(&dr_regs->deviceaddr);
1673 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1674
1675 udc->device_address = 0;
1676
1677 /* Clear usb state */
1678 udc->resume_state = 0;
1679 udc->ep0_dir = 0;
1680 udc->ep0_state = WAIT_FOR_SETUP;
1681 udc->remote_wakeup = 0; /* default to 0 on reset */
1682 udc->gadget.b_hnp_enable = 0;
1683 udc->gadget.a_hnp_support = 0;
1684 udc->gadget.a_alt_hnp_support = 0;
1685
1686 /* Clear all the setup token semaphores */
1687 temp = fsl_readl(&dr_regs->endptsetupstat);
1688 fsl_writel(temp, &dr_regs->endptsetupstat);
1689
1690 /* Clear all the endpoint complete status bits */
1691 temp = fsl_readl(&dr_regs->endptcomplete);
1692 fsl_writel(temp, &dr_regs->endptcomplete);
1693
1694 timeout = jiffies + 100;
1695 while (fsl_readl(&dr_regs->endpointprime)) {
1696 /* Wait until all endptprime bits cleared */
1697 if (time_after(jiffies, timeout)) {
1698 ERR("Timeout for reset\n");
1699 break;
1700 }
1701 cpu_relax();
1702 }
1703
1704 /* Write 1s to the flush register */
1705 fsl_writel(0xffffffff, &dr_regs->endptflush);
1706
1707 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1708 VDBG("Bus reset");
1709 /* Bus is reseting */
1710 udc->bus_reset = 1;
1711 /* Reset all the queues, include XD, dTD, EP queue
1712 * head and TR Queue */
1713 reset_queues(udc);
1714 udc->usb_state = USB_STATE_DEFAULT;
1715 } else {
1716 VDBG("Controller reset");
1717 /* initialize usb hw reg except for regs for EP, not
1718 * touch usbintr reg */
1719 dr_controller_setup(udc);
1720
1721 /* Reset all internal used Queues */
1722 reset_queues(udc);
1723
1724 ep0_setup(udc);
1725
1726 /* Enable DR IRQ reg, Set Run bit, change udc state */
1727 dr_controller_run(udc);
1728 udc->usb_state = USB_STATE_ATTACHED;
1729 }
1730 }
1731
1732 /*
1733 * USB device controller interrupt handler
1734 */
1735 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1736 {
1737 struct fsl_udc *udc = _udc;
1738 u32 irq_src;
1739 irqreturn_t status = IRQ_NONE;
1740 unsigned long flags;
1741
1742 /* Disable ISR for OTG host mode */
1743 if (udc->stopped)
1744 return IRQ_NONE;
1745 spin_lock_irqsave(&udc->lock, flags);
1746 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1747 /* Clear notification bits */
1748 fsl_writel(irq_src, &dr_regs->usbsts);
1749
1750 /* VDBG("irq_src [0x%8x]", irq_src); */
1751
1752 /* Need to resume? */
1753 if (udc->usb_state == USB_STATE_SUSPENDED)
1754 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1755 bus_resume(udc);
1756
1757 /* USB Interrupt */
1758 if (irq_src & USB_STS_INT) {
1759 VDBG("Packet int");
1760 /* Setup package, we only support ep0 as control ep */
1761 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1762 tripwire_handler(udc, 0,
1763 (u8 *) (&udc->local_setup_buff));
1764 setup_received_irq(udc, &udc->local_setup_buff);
1765 status = IRQ_HANDLED;
1766 }
1767
1768 /* completion of dtd */
1769 if (fsl_readl(&dr_regs->endptcomplete)) {
1770 dtd_complete_irq(udc);
1771 status = IRQ_HANDLED;
1772 }
1773 }
1774
1775 /* SOF (for ISO transfer) */
1776 if (irq_src & USB_STS_SOF) {
1777 status = IRQ_HANDLED;
1778 }
1779
1780 /* Port Change */
1781 if (irq_src & USB_STS_PORT_CHANGE) {
1782 port_change_irq(udc);
1783 status = IRQ_HANDLED;
1784 }
1785
1786 /* Reset Received */
1787 if (irq_src & USB_STS_RESET) {
1788 reset_irq(udc);
1789 status = IRQ_HANDLED;
1790 }
1791
1792 /* Sleep Enable (Suspend) */
1793 if (irq_src & USB_STS_SUSPEND) {
1794 suspend_irq(udc);
1795 status = IRQ_HANDLED;
1796 }
1797
1798 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1799 VDBG("Error IRQ %x ", irq_src);
1800 }
1801
1802 spin_unlock_irqrestore(&udc->lock, flags);
1803 return status;
1804 }
1805
1806 /*----------------------------------------------------------------*
1807 * Hook to gadget drivers
1808 * Called by initialization code of gadget drivers
1809 *----------------------------------------------------------------*/
1810 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1811 {
1812 int retval = -ENODEV;
1813 unsigned long flags = 0;
1814
1815 if (!udc_controller)
1816 return -ENODEV;
1817
1818 if (!driver || (driver->speed != USB_SPEED_FULL
1819 && driver->speed != USB_SPEED_HIGH)
1820 || !driver->bind || !driver->disconnect
1821 || !driver->setup)
1822 return -EINVAL;
1823
1824 if (udc_controller->driver)
1825 return -EBUSY;
1826
1827 /* lock is needed but whether should use this lock or another */
1828 spin_lock_irqsave(&udc_controller->lock, flags);
1829
1830 driver->driver.bus = 0;
1831 /* hook up the driver */
1832 udc_controller->driver = driver;
1833 udc_controller->gadget.dev.driver = &driver->driver;
1834 spin_unlock_irqrestore(&udc_controller->lock, flags);
1835
1836 /* bind udc driver to gadget driver */
1837 retval = driver->bind(&udc_controller->gadget);
1838 if (retval) {
1839 VDBG("bind to %s --> %d", driver->driver.name, retval);
1840 udc_controller->gadget.dev.driver = 0;
1841 udc_controller->driver = 0;
1842 goto out;
1843 }
1844
1845 /* Enable DR IRQ reg and Set usbcmd reg Run bit */
1846 dr_controller_run(udc_controller);
1847 udc_controller->usb_state = USB_STATE_ATTACHED;
1848 udc_controller->ep0_state = WAIT_FOR_SETUP;
1849 udc_controller->ep0_dir = 0;
1850 printk(KERN_INFO "%s: bind to driver %s \n",
1851 udc_controller->gadget.name, driver->driver.name);
1852
1853 out:
1854 if (retval)
1855 printk("retval %d \n", retval);
1856 return retval;
1857 }
1858 EXPORT_SYMBOL(usb_gadget_register_driver);
1859
1860 /* Disconnect from gadget driver */
1861 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1862 {
1863 struct fsl_ep *loop_ep;
1864 unsigned long flags;
1865
1866 if (!udc_controller)
1867 return -ENODEV;
1868
1869 if (!driver || driver != udc_controller->driver || !driver->unbind)
1870 return -EINVAL;
1871
1872 #ifdef CONFIG_USB_OTG
1873 if (udc_controller->transceiver)
1874 (void)otg_set_peripheral(udc_controller->transceiver, 0);
1875 #endif
1876
1877 /* stop DR, disable intr */
1878 dr_controller_stop(udc_controller);
1879
1880 /* in fact, no needed */
1881 udc_controller->usb_state = USB_STATE_ATTACHED;
1882 udc_controller->ep0_state = WAIT_FOR_SETUP;
1883 udc_controller->ep0_dir = 0;
1884
1885 /* stand operation */
1886 spin_lock_irqsave(&udc_controller->lock, flags);
1887 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
1888 nuke(&udc_controller->eps[0], -ESHUTDOWN);
1889 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
1890 ep.ep_list)
1891 nuke(loop_ep, -ESHUTDOWN);
1892 spin_unlock_irqrestore(&udc_controller->lock, flags);
1893
1894 /* unbind gadget and unhook driver. */
1895 driver->unbind(&udc_controller->gadget);
1896 udc_controller->gadget.dev.driver = 0;
1897 udc_controller->driver = 0;
1898
1899 printk("unregistered gadget driver '%s'\r\n", driver->driver.name);
1900 return 0;
1901 }
1902 EXPORT_SYMBOL(usb_gadget_unregister_driver);
1903
1904 /*-------------------------------------------------------------------------
1905 PROC File System Support
1906 -------------------------------------------------------------------------*/
1907 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1908
1909 #include <linux/seq_file.h>
1910
1911 static const char proc_filename[] = "driver/fsl_usb2_udc";
1912
1913 static int fsl_proc_read(char *page, char **start, off_t off, int count,
1914 int *eof, void *_dev)
1915 {
1916 char *buf = page;
1917 char *next = buf;
1918 unsigned size = count;
1919 unsigned long flags;
1920 int t, i;
1921 u32 tmp_reg;
1922 struct fsl_ep *ep = NULL;
1923 struct fsl_req *req;
1924
1925 struct fsl_udc *udc = udc_controller;
1926 if (off != 0)
1927 return 0;
1928
1929 spin_lock_irqsave(&udc->lock, flags);
1930
1931 /* ------basic driver infomation ---- */
1932 t = scnprintf(next, size,
1933 DRIVER_DESC "\n"
1934 "%s version: %s\n"
1935 "Gadget driver: %s\n\n",
1936 driver_name, DRIVER_VERSION,
1937 udc->driver ? udc->driver->driver.name : "(none)");
1938 size -= t;
1939 next += t;
1940
1941 /* ------ DR Registers ----- */
1942 tmp_reg = fsl_readl(&dr_regs->usbcmd);
1943 t = scnprintf(next, size,
1944 "USBCMD reg:\n"
1945 "SetupTW: %d\n"
1946 "Run/Stop: %s\n\n",
1947 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
1948 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
1949 size -= t;
1950 next += t;
1951
1952 tmp_reg = fsl_readl(&dr_regs->usbsts);
1953 t = scnprintf(next, size,
1954 "USB Status Reg:\n"
1955 "Dr Suspend: %d" "Reset Received: %d" "System Error: %s"
1956 "USB Error Interrupt: %s\n\n",
1957 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
1958 (tmp_reg & USB_STS_RESET) ? 1 : 0,
1959 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
1960 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
1961 size -= t;
1962 next += t;
1963
1964 tmp_reg = fsl_readl(&dr_regs->usbintr);
1965 t = scnprintf(next, size,
1966 "USB Intrrupt Enable Reg:\n"
1967 "Sleep Enable: %d" "SOF Received Enable: %d"
1968 "Reset Enable: %d\n"
1969 "System Error Enable: %d"
1970 "Port Change Dectected Enable: %d\n"
1971 "USB Error Intr Enable: %d" "USB Intr Enable: %d\n\n",
1972 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
1973 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
1974 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
1975 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
1976 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
1977 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
1978 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
1979 size -= t;
1980 next += t;
1981
1982 tmp_reg = fsl_readl(&dr_regs->frindex);
1983 t = scnprintf(next, size,
1984 "USB Frame Index Reg:" "Frame Number is 0x%x\n\n",
1985 (tmp_reg & USB_FRINDEX_MASKS));
1986 size -= t;
1987 next += t;
1988
1989 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
1990 t = scnprintf(next, size,
1991 "USB Device Address Reg:" "Device Addr is 0x%x\n\n",
1992 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
1993 size -= t;
1994 next += t;
1995
1996 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
1997 t = scnprintf(next, size,
1998 "USB Endpoint List Address Reg:"
1999 "Device Addr is 0x%x\n\n",
2000 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2001 size -= t;
2002 next += t;
2003
2004 tmp_reg = fsl_readl(&dr_regs->portsc1);
2005 t = scnprintf(next, size,
2006 "USB Port Status&Control Reg:\n"
2007 "Port Transceiver Type : %s" "Port Speed: %s \n"
2008 "PHY Low Power Suspend: %s" "Port Reset: %s"
2009 "Port Suspend Mode: %s \n" "Over-current Change: %s"
2010 "Port Enable/Disable Change: %s\n"
2011 "Port Enabled/Disabled: %s"
2012 "Current Connect Status: %s\n\n", ( {
2013 char *s;
2014 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2015 case PORTSCX_PTS_UTMI:
2016 s = "UTMI"; break;
2017 case PORTSCX_PTS_ULPI:
2018 s = "ULPI "; break;
2019 case PORTSCX_PTS_FSLS:
2020 s = "FS/LS Serial"; break;
2021 default:
2022 s = "None"; break;
2023 }
2024 s;} ), ( {
2025 char *s;
2026 switch (tmp_reg & PORTSCX_PORT_SPEED_UNDEF) {
2027 case PORTSCX_PORT_SPEED_FULL:
2028 s = "Full Speed"; break;
2029 case PORTSCX_PORT_SPEED_LOW:
2030 s = "Low Speed"; break;
2031 case PORTSCX_PORT_SPEED_HIGH:
2032 s = "High Speed"; break;
2033 default:
2034 s = "Undefined"; break;
2035 }
2036 s;
2037 } ),
2038 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2039 "Normal PHY mode" : "Low power mode",
2040 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2041 "Not in Reset",
2042 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2043 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2044 "No",
2045 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2046 "Not change",
2047 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2048 "Not correct",
2049 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2050 "Attached" : "Not-Att");
2051 size -= t;
2052 next += t;
2053
2054 tmp_reg = fsl_readl(&dr_regs->usbmode);
2055 t = scnprintf(next, size,
2056 "USB Mode Reg:" "Controller Mode is : %s\n\n", ( {
2057 char *s;
2058 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2059 case USB_MODE_CTRL_MODE_IDLE:
2060 s = "Idle"; break;
2061 case USB_MODE_CTRL_MODE_DEVICE:
2062 s = "Device Controller"; break;
2063 case USB_MODE_CTRL_MODE_HOST:
2064 s = "Host Controller"; break;
2065 default:
2066 s = "None"; break;
2067 }
2068 s;
2069 } ));
2070 size -= t;
2071 next += t;
2072
2073 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2074 t = scnprintf(next, size,
2075 "Endpoint Setup Status Reg:" "SETUP on ep 0x%x\n\n",
2076 (tmp_reg & EP_SETUP_STATUS_MASK));
2077 size -= t;
2078 next += t;
2079
2080 for (i = 0; i < udc->max_ep / 2; i++) {
2081 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2082 t = scnprintf(next, size, "EP Ctrl Reg [0x%x]: = [0x%x]\n",
2083 i, tmp_reg);
2084 size -= t;
2085 next += t;
2086 }
2087 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2088 t = scnprintf(next, size, "EP Prime Reg = [0x%x]\n", tmp_reg);
2089 size -= t;
2090 next += t;
2091
2092 tmp_reg = usb_sys_regs->snoop1;
2093 t = scnprintf(next, size, "\nSnoop1 Reg : = [0x%x]\n\n", tmp_reg);
2094 size -= t;
2095 next += t;
2096
2097 tmp_reg = usb_sys_regs->control;
2098 t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
2099 tmp_reg);
2100 size -= t;
2101 next += t;
2102
2103 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2104 ep = &udc->eps[0];
2105 t = scnprintf(next, size, "For %s Maxpkt is 0x%x index is 0x%x\n",
2106 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2107 size -= t;
2108 next += t;
2109
2110 if (list_empty(&ep->queue)) {
2111 t = scnprintf(next, size, "its req queue is empty\n\n");
2112 size -= t;
2113 next += t;
2114 } else {
2115 list_for_each_entry(req, &ep->queue, queue) {
2116 t = scnprintf(next, size,
2117 "req %p actual 0x%x length 0x%x buf %p\n",
2118 &req->req, req->req.actual,
2119 req->req.length, req->req.buf);
2120 size -= t;
2121 next += t;
2122 }
2123 }
2124 /* other gadget->eplist ep */
2125 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2126 if (ep->desc) {
2127 t = scnprintf(next, size,
2128 "\nFor %s Maxpkt is 0x%x "
2129 "index is 0x%x\n",
2130 ep->ep.name, ep_maxpacket(ep),
2131 ep_index(ep));
2132 size -= t;
2133 next += t;
2134
2135 if (list_empty(&ep->queue)) {
2136 t = scnprintf(next, size,
2137 "its req queue is empty\n\n");
2138 size -= t;
2139 next += t;
2140 } else {
2141 list_for_each_entry(req, &ep->queue, queue) {
2142 t = scnprintf(next, size,
2143 "req %p actual 0x%x length"
2144 "0x%x buf %p\n",
2145 &req->req, req->req.actual,
2146 req->req.length, req->req.buf);
2147 size -= t;
2148 next += t;
2149 } /* end for each_entry of ep req */
2150 } /* end for else */
2151 } /* end for if(ep->queue) */
2152 } /* end (ep->desc) */
2153
2154 spin_unlock_irqrestore(&udc->lock, flags);
2155
2156 *eof = 1;
2157 return count - size;
2158 }
2159
2160 #define create_proc_file() create_proc_read_entry(proc_filename, \
2161 0, NULL, fsl_proc_read, NULL)
2162
2163 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2164
2165 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2166
2167 #define create_proc_file() do {} while (0)
2168 #define remove_proc_file() do {} while (0)
2169
2170 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2171
2172 /*-------------------------------------------------------------------------*/
2173
2174 /* Release udc structures */
2175 static void fsl_udc_release(struct device *dev)
2176 {
2177 complete(udc_controller->done);
2178 dma_free_coherent(dev, udc_controller->ep_qh_size,
2179 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2180 kfree(udc_controller);
2181 }
2182
2183 /******************************************************************
2184 Internal structure setup functions
2185 *******************************************************************/
2186 /*------------------------------------------------------------------
2187 * init resource for globle controller
2188 * Return the udc handle on success or NULL on failure
2189 ------------------------------------------------------------------*/
2190 static struct fsl_udc *__init struct_udc_setup(struct platform_device *pdev)
2191 {
2192 struct fsl_udc *udc;
2193 struct fsl_usb2_platform_data *pdata;
2194 size_t size;
2195
2196 udc = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2197 if (udc == NULL) {
2198 ERR("malloc udc failed\n");
2199 return NULL;
2200 }
2201
2202 pdata = pdev->dev.platform_data;
2203 udc->phy_mode = pdata->phy_mode;
2204 /* max_ep_nr is bidirectional ep number, max_ep doubles the number */
2205 udc->max_ep = pdata->max_ep_nr * 2;
2206
2207 udc->eps = kzalloc(sizeof(struct fsl_ep) * udc->max_ep, GFP_KERNEL);
2208 if (!udc->eps) {
2209 ERR("malloc fsl_ep failed\n");
2210 goto cleanup;
2211 }
2212
2213 /* initialized QHs, take care of alignment */
2214 size = udc->max_ep * sizeof(struct ep_queue_head);
2215 if (size < QH_ALIGNMENT)
2216 size = QH_ALIGNMENT;
2217 else if ((size % QH_ALIGNMENT) != 0) {
2218 size += QH_ALIGNMENT + 1;
2219 size &= ~(QH_ALIGNMENT - 1);
2220 }
2221 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2222 &udc->ep_qh_dma, GFP_KERNEL);
2223 if (!udc->ep_qh) {
2224 ERR("malloc QHs for udc failed\n");
2225 kfree(udc->eps);
2226 goto cleanup;
2227 }
2228
2229 udc->ep_qh_size = size;
2230
2231 /* Initialize ep0 status request structure */
2232 /* FIXME: fsl_alloc_request() ignores ep argument */
2233 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2234 struct fsl_req, req);
2235 /* allocate a small amount of memory to get valid address */
2236 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2237 udc->status_req->req.dma = virt_to_phys(udc->status_req->req.buf);
2238
2239 udc->resume_state = USB_STATE_NOTATTACHED;
2240 udc->usb_state = USB_STATE_POWERED;
2241 udc->ep0_dir = 0;
2242 udc->remote_wakeup = 0; /* default to 0 on reset */
2243 spin_lock_init(&udc->lock);
2244
2245 return udc;
2246
2247 cleanup:
2248 kfree(udc);
2249 return NULL;
2250 }
2251
2252 /*----------------------------------------------------------------
2253 * Setup the fsl_ep struct for eps
2254 * Link fsl_ep->ep to gadget->ep_list
2255 * ep0out is not used so do nothing here
2256 * ep0in should be taken care
2257 *--------------------------------------------------------------*/
2258 static int __init struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2259 char *name, int link)
2260 {
2261 struct fsl_ep *ep = &udc->eps[index];
2262
2263 ep->udc = udc;
2264 strcpy(ep->name, name);
2265 ep->ep.name = ep->name;
2266
2267 ep->ep.ops = &fsl_ep_ops;
2268 ep->stopped = 0;
2269
2270 /* for ep0: maxP defined in desc
2271 * for other eps, maxP is set by epautoconfig() called by gadget layer
2272 */
2273 ep->ep.maxpacket = (unsigned short) ~0;
2274
2275 /* the queue lists any req for this ep */
2276 INIT_LIST_HEAD(&ep->queue);
2277
2278 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2279 if (link)
2280 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2281 ep->gadget = &udc->gadget;
2282 ep->qh = &udc->ep_qh[index];
2283
2284 return 0;
2285 }
2286
2287 /* Driver probe function
2288 * all intialize operations implemented here except enabling usb_intr reg
2289 */
2290 static int __init fsl_udc_probe(struct platform_device *pdev)
2291 {
2292 struct resource *res;
2293 int ret = -ENODEV;
2294 unsigned int i;
2295
2296 if (strcmp(pdev->name, driver_name)) {
2297 VDBG("Wrong device\n");
2298 return -ENODEV;
2299 }
2300
2301 /* board setup should have been done in the platform code */
2302
2303 /* Initialize the udc structure including QH member and other member */
2304 udc_controller = struct_udc_setup(pdev);
2305 if (!udc_controller) {
2306 VDBG("udc_controller is NULL \n");
2307 return -ENOMEM;
2308 }
2309
2310 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2311 if (!res)
2312 return -ENXIO;
2313
2314 if (!request_mem_region(res->start, res->end - res->start + 1,
2315 driver_name)) {
2316 ERR("request mem region for %s failed \n", pdev->name);
2317 return -EBUSY;
2318 }
2319
2320 dr_regs = ioremap(res->start, res->end - res->start + 1);
2321 if (!dr_regs) {
2322 ret = -ENOMEM;
2323 goto err1;
2324 }
2325
2326 usb_sys_regs = (struct usb_sys_interface *)
2327 ((u32)dr_regs + USB_DR_SYS_OFFSET);
2328
2329 udc_controller->irq = platform_get_irq(pdev, 0);
2330 if (!udc_controller->irq) {
2331 ret = -ENODEV;
2332 goto err2;
2333 }
2334
2335 ret = request_irq(udc_controller->irq, fsl_udc_irq, SA_SHIRQ,
2336 driver_name, udc_controller);
2337 if (ret != 0) {
2338 ERR("cannot request irq %d err %d \n",
2339 udc_controller->irq, ret);
2340 goto err2;
2341 }
2342
2343 /* initialize usb hw reg except for regs for EP,
2344 * leave usbintr reg untouched */
2345 dr_controller_setup(udc_controller);
2346
2347 /* Setup gadget structure */
2348 udc_controller->gadget.ops = &fsl_gadget_ops;
2349 udc_controller->gadget.is_dualspeed = 1;
2350 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2351 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2352 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2353 udc_controller->gadget.name = driver_name;
2354
2355 /* Setup gadget.dev and register with kernel */
2356 strcpy(udc_controller->gadget.dev.bus_id, "gadget");
2357 udc_controller->gadget.dev.release = fsl_udc_release;
2358 udc_controller->gadget.dev.parent = &pdev->dev;
2359 ret = device_register(&udc_controller->gadget.dev);
2360 if (ret < 0)
2361 goto err3;
2362
2363 /* setup QH and epctrl for ep0 */
2364 ep0_setup(udc_controller);
2365
2366 /* setup udc->eps[] for ep0 */
2367 struct_ep_setup(udc_controller, 0, "ep0", 0);
2368 /* for ep0: the desc defined here;
2369 * for other eps, gadget layer called ep_enable with defined desc
2370 */
2371 udc_controller->eps[0].desc = &fsl_ep0_desc;
2372 udc_controller->eps[0].ep.maxpacket = USB_MAX_CTRL_PAYLOAD;
2373
2374 /* setup the udc->eps[] for non-control endpoints and link
2375 * to gadget.ep_list */
2376 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2377 char name[14];
2378
2379 sprintf(name, "ep%dout", i);
2380 struct_ep_setup(udc_controller, i * 2, name, 1);
2381 sprintf(name, "ep%din", i);
2382 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2383 }
2384
2385 /* use dma_pool for TD management */
2386 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2387 sizeof(struct ep_td_struct),
2388 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2389 if (udc_controller->td_pool == NULL) {
2390 ret = -ENOMEM;
2391 goto err4;
2392 }
2393 create_proc_file();
2394 return 0;
2395
2396 err4:
2397 device_unregister(&udc_controller->gadget.dev);
2398 err3:
2399 free_irq(udc_controller->irq, udc_controller);
2400 err2:
2401 iounmap(dr_regs);
2402 err1:
2403 release_mem_region(res->start, res->end - res->start + 1);
2404 return ret;
2405 }
2406
2407 /* Driver removal function
2408 * Free resources and finish pending transactions
2409 */
2410 static int __exit fsl_udc_remove(struct platform_device *pdev)
2411 {
2412 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2413
2414 DECLARE_COMPLETION(done);
2415
2416 if (!udc_controller)
2417 return -ENODEV;
2418 udc_controller->done = &done;
2419
2420 /* DR has been stopped in usb_gadget_unregister_driver() */
2421 remove_proc_file();
2422
2423 /* Free allocated memory */
2424 kfree(udc_controller->status_req->req.buf);
2425 kfree(udc_controller->status_req);
2426 kfree(udc_controller->eps);
2427
2428 dma_pool_destroy(udc_controller->td_pool);
2429 free_irq(udc_controller->irq, udc_controller);
2430 iounmap(dr_regs);
2431 release_mem_region(res->start, res->end - res->start + 1);
2432
2433 device_unregister(&udc_controller->gadget.dev);
2434 /* free udc --wait for the release() finished */
2435 wait_for_completion(&done);
2436
2437 return 0;
2438 }
2439
2440 /*-----------------------------------------------------------------
2441 * Modify Power management attributes
2442 * Used by OTG statemachine to disable gadget temporarily
2443 -----------------------------------------------------------------*/
2444 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2445 {
2446 dr_controller_stop(udc_controller);
2447 return 0;
2448 }
2449
2450 /*-----------------------------------------------------------------
2451 * Invoked on USB resume. May be called in_interrupt.
2452 * Here we start the DR controller and enable the irq
2453 *-----------------------------------------------------------------*/
2454 static int fsl_udc_resume(struct platform_device *pdev)
2455 {
2456 /* Enable DR irq reg and set controller Run */
2457 if (udc_controller->stopped) {
2458 dr_controller_setup(udc_controller);
2459 dr_controller_run(udc_controller);
2460 }
2461 udc_controller->usb_state = USB_STATE_ATTACHED;
2462 udc_controller->ep0_state = WAIT_FOR_SETUP;
2463 udc_controller->ep0_dir = 0;
2464 return 0;
2465 }
2466
2467 /*-------------------------------------------------------------------------
2468 Register entry point for the peripheral controller driver
2469 --------------------------------------------------------------------------*/
2470
2471 static struct platform_driver udc_driver = {
2472 .remove = __exit_p(fsl_udc_remove),
2473 /* these suspend and resume are not usb suspend and resume */
2474 .suspend = fsl_udc_suspend,
2475 .resume = fsl_udc_resume,
2476 .driver = {
2477 .name = (char *)driver_name,
2478 .owner = THIS_MODULE,
2479 },
2480 };
2481
2482 static int __init udc_init(void)
2483 {
2484 printk(KERN_INFO "%s (%s)\n", driver_desc, DRIVER_VERSION);
2485 return platform_driver_probe(&udc_driver, fsl_udc_probe);
2486 }
2487
2488 module_init(udc_init);
2489
2490 static void __exit udc_exit(void)
2491 {
2492 platform_driver_unregister(&udc_driver);
2493 printk("%s unregistered \n", driver_desc);
2494 }
2495
2496 module_exit(udc_exit);
2497
2498 MODULE_DESCRIPTION(DRIVER_DESC);
2499 MODULE_AUTHOR(DRIVER_AUTHOR);
2500 MODULE_LICENSE("GPL");
Linux for Ginger Game Console