| commit | 8ff120e5303e27e03aba7b774e86fd43eaf90376 | |
| author | Rajendra Nayak <rnayak@ti.com> | |
| Sat, 25 Jul 2009 01:44:01 +0000 (24 19:44 -0600) | ||
| committer | paul <paul@twilight.(none)> | |
| Sat, 25 Jul 2009 02:10:35 +0000 (24 20:10 -0600) | ||
| tree | 09d4487d784cf9656ea98615a7ebc8db52f25ef8 | treesnapshot (tar.gz zip) |
| parent | 75f251e3d0803b028f3474fdc75be0994c377ab5 | commitdiff |
OMAP3 SDRC: Fix freeze when scaling CORE dpll to < 83Mhz
This patch fixes a bug in the CORE dpll scaling sequence which was
errouneously clearing some bits in the SDRC DLLA CTRL register and
hence causing a freeze. The issue was observed only on platforms
which scale CORE dpll to < 83Mhz and hence program the DLL in fixed
delay mode.
Issue reported by Limei Wang <E12499@motorola.com>, with debugging
assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish
Ghongdemath <girishsg@ti.com>.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Limei Wang <E12499@motorola.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Girish Ghongdemath <girishsg@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: updated patch description to include collaboration credits]
This patch fixes a bug in the CORE dpll scaling sequence which was
errouneously clearing some bits in the SDRC DLLA CTRL register and
hence causing a freeze. The issue was observed only on platforms
which scale CORE dpll to < 83Mhz and hence program the DLL in fixed
delay mode.
Issue reported by Limei Wang <E12499@motorola.com>, with debugging
assistance from Richard Woodruff <r-woodruff2@ti.com> and Girish
Ghongdemath <girishsg@ti.com>.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Cc: Limei Wang <E12499@motorola.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Cc: Girish Ghongdemath <girishsg@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
[paul@pwsan.com: updated patch description to include collaboration credits]
| arch/arm/mach-omap2/sram34xx.S | diffblobblamehistory |