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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux.git] / drivers / clk / meson / gxbb.c
blob8575b848538598fcd5b7f4504fd6be48037a2743
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2016 AmLogic, Inc.
4 * Michael Turquette <mturquette@baylibre.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/init.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/platform_device.h>
11 #include <linux/module.h>
12
13 #include "gxbb.h"
14 #include "clk-regmap.h"
15 #include "clk-pll.h"
16 #include "clk-mpll.h"
17 #include "meson-eeclk.h"
18 #include "vid-pll-div.h"
19
20 #include <dt-bindings/clock/gxbb-clkc.h>
21
22 static const struct pll_params_table gxbb_gp0_pll_params_table[] = {
23 PLL_PARAMS(32, 1),
24 PLL_PARAMS(33, 1),
25 PLL_PARAMS(34, 1),
26 PLL_PARAMS(35, 1),
27 PLL_PARAMS(36, 1),
28 PLL_PARAMS(37, 1),
29 PLL_PARAMS(38, 1),
30 PLL_PARAMS(39, 1),
31 PLL_PARAMS(40, 1),
32 PLL_PARAMS(41, 1),
33 PLL_PARAMS(42, 1),
34 PLL_PARAMS(43, 1),
35 PLL_PARAMS(44, 1),
36 PLL_PARAMS(45, 1),
37 PLL_PARAMS(46, 1),
38 PLL_PARAMS(47, 1),
39 PLL_PARAMS(48, 1),
40 PLL_PARAMS(49, 1),
41 PLL_PARAMS(50, 1),
42 PLL_PARAMS(51, 1),
43 PLL_PARAMS(52, 1),
44 PLL_PARAMS(53, 1),
45 PLL_PARAMS(54, 1),
46 PLL_PARAMS(55, 1),
47 PLL_PARAMS(56, 1),
48 PLL_PARAMS(57, 1),
49 PLL_PARAMS(58, 1),
50 PLL_PARAMS(59, 1),
51 PLL_PARAMS(60, 1),
52 PLL_PARAMS(61, 1),
53 PLL_PARAMS(62, 1),
54 { /* sentinel */ },
55 };
56
57 static const struct pll_params_table gxl_gp0_pll_params_table[] = {
58 PLL_PARAMS(42, 1),
59 PLL_PARAMS(43, 1),
60 PLL_PARAMS(44, 1),
61 PLL_PARAMS(45, 1),
62 PLL_PARAMS(46, 1),
63 PLL_PARAMS(47, 1),
64 PLL_PARAMS(48, 1),
65 PLL_PARAMS(49, 1),
66 PLL_PARAMS(50, 1),
67 PLL_PARAMS(51, 1),
68 PLL_PARAMS(52, 1),
69 PLL_PARAMS(53, 1),
70 PLL_PARAMS(54, 1),
71 PLL_PARAMS(55, 1),
72 PLL_PARAMS(56, 1),
73 PLL_PARAMS(57, 1),
74 PLL_PARAMS(58, 1),
75 PLL_PARAMS(59, 1),
76 PLL_PARAMS(60, 1),
77 PLL_PARAMS(61, 1),
78 PLL_PARAMS(62, 1),
79 PLL_PARAMS(63, 1),
80 PLL_PARAMS(64, 1),
81 PLL_PARAMS(65, 1),
82 PLL_PARAMS(66, 1),
83 { /* sentinel */ },
84 };
85
86 static struct clk_regmap gxbb_fixed_pll_dco = {
87 .data = &(struct meson_clk_pll_data){
88 .en = {
89 .reg_off = HHI_MPLL_CNTL,
90 .shift = 30,
91 .width = 1,
92 },
93 .m = {
94 .reg_off = HHI_MPLL_CNTL,
95 .shift = 0,
96 .width = 9,
97 },
98 .n = {
99 .reg_off = HHI_MPLL_CNTL,
100 .shift = 9,
101 .width = 5,
102 },
103 .frac = {
104 .reg_off = HHI_MPLL_CNTL2,
105 .shift = 0,
106 .width = 12,
107 },
108 .l = {
109 .reg_off = HHI_MPLL_CNTL,
110 .shift = 31,
111 .width = 1,
112 },
113 .rst = {
114 .reg_off = HHI_MPLL_CNTL,
115 .shift = 29,
116 .width = 1,
117 },
118 },
119 .hw.init = &(struct clk_init_data){
120 .name = "fixed_pll_dco",
121 .ops = &meson_clk_pll_ro_ops,
122 .parent_data = &(const struct clk_parent_data) {
123 .fw_name = "xtal",
124 },
125 .num_parents = 1,
126 },
127 };
128
129 static struct clk_regmap gxbb_fixed_pll = {
130 .data = &(struct clk_regmap_div_data){
131 .offset = HHI_MPLL_CNTL,
132 .shift = 16,
133 .width = 2,
134 .flags = CLK_DIVIDER_POWER_OF_TWO,
135 },
136 .hw.init = &(struct clk_init_data){
137 .name = "fixed_pll",
138 .ops = &clk_regmap_divider_ro_ops,
139 .parent_hws = (const struct clk_hw *[]) {
140 &gxbb_fixed_pll_dco.hw
141 },
142 .num_parents = 1,
143 /*
144 * This clock won't ever change at runtime so
145 * CLK_SET_RATE_PARENT is not required
146 */
147 },
148 };
149
150 static struct clk_fixed_factor gxbb_hdmi_pll_pre_mult = {
151 .mult = 2,
152 .div = 1,
153 .hw.init = &(struct clk_init_data){
154 .name = "hdmi_pll_pre_mult",
155 .ops = &clk_fixed_factor_ops,
156 .parent_data = &(const struct clk_parent_data) {
157 .fw_name = "xtal",
158 },
159 .num_parents = 1,
160 },
161 };
162
163 static struct clk_regmap gxbb_hdmi_pll_dco = {
164 .data = &(struct meson_clk_pll_data){
165 .en = {
166 .reg_off = HHI_HDMI_PLL_CNTL,
167 .shift = 30,
168 .width = 1,
169 },
170 .m = {
171 .reg_off = HHI_HDMI_PLL_CNTL,
172 .shift = 0,
173 .width = 9,
174 },
175 .n = {
176 .reg_off = HHI_HDMI_PLL_CNTL,
177 .shift = 9,
178 .width = 5,
179 },
180 .frac = {
181 .reg_off = HHI_HDMI_PLL_CNTL2,
182 .shift = 0,
183 .width = 12,
184 },
185 .l = {
186 .reg_off = HHI_HDMI_PLL_CNTL,
187 .shift = 31,
188 .width = 1,
189 },
190 .rst = {
191 .reg_off = HHI_HDMI_PLL_CNTL,
192 .shift = 28,
193 .width = 1,
194 },
195 },
196 .hw.init = &(struct clk_init_data){
197 .name = "hdmi_pll_dco",
198 .ops = &meson_clk_pll_ro_ops,
199 .parent_hws = (const struct clk_hw *[]) {
200 &gxbb_hdmi_pll_pre_mult.hw
201 },
202 .num_parents = 1,
203 /*
204 * Display directly handle hdmi pll registers ATM, we need
205 * NOCACHE to keep our view of the clock as accurate as possible
206 */
207 .flags = CLK_GET_RATE_NOCACHE,
208 },
209 };
210
211 static struct clk_regmap gxl_hdmi_pll_dco = {
212 .data = &(struct meson_clk_pll_data){
213 .en = {
214 .reg_off = HHI_HDMI_PLL_CNTL,
215 .shift = 30,
216 .width = 1,
217 },
218 .m = {
219 .reg_off = HHI_HDMI_PLL_CNTL,
220 .shift = 0,
221 .width = 9,
222 },
223 .n = {
224 .reg_off = HHI_HDMI_PLL_CNTL,
225 .shift = 9,
226 .width = 5,
227 },
228 /*
229 * On gxl, there is a register shift due to
230 * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
231 * so we use the HHI_HDMI_PLL_CNTL2 define from GXBB
232 * instead which is defined at the same offset.
233 */
234 .frac = {
235 .reg_off = HHI_HDMI_PLL_CNTL2,
236 .shift = 0,
237 .width = 10,
238 },
239 .l = {
240 .reg_off = HHI_HDMI_PLL_CNTL,
241 .shift = 31,
242 .width = 1,
243 },
244 .rst = {
245 .reg_off = HHI_HDMI_PLL_CNTL,
246 .shift = 28,
247 .width = 1,
248 },
249 },
250 .hw.init = &(struct clk_init_data){
251 .name = "hdmi_pll_dco",
252 .ops = &meson_clk_pll_ro_ops,
253 .parent_data = &(const struct clk_parent_data) {
254 .fw_name = "xtal",
255 },
256 .num_parents = 1,
257 /*
258 * Display directly handle hdmi pll registers ATM, we need
259 * NOCACHE to keep our view of the clock as accurate as possible
260 */
261 .flags = CLK_GET_RATE_NOCACHE,
262 },
263 };
264
265 static struct clk_regmap gxbb_hdmi_pll_od = {
266 .data = &(struct clk_regmap_div_data){
267 .offset = HHI_HDMI_PLL_CNTL2,
268 .shift = 16,
269 .width = 2,
270 .flags = CLK_DIVIDER_POWER_OF_TWO,
271 },
272 .hw.init = &(struct clk_init_data){
273 .name = "hdmi_pll_od",
274 .ops = &clk_regmap_divider_ro_ops,
275 .parent_hws = (const struct clk_hw *[]) {
276 &gxbb_hdmi_pll_dco.hw
277 },
278 .num_parents = 1,
279 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
280 },
281 };
282
283 static struct clk_regmap gxbb_hdmi_pll_od2 = {
284 .data = &(struct clk_regmap_div_data){
285 .offset = HHI_HDMI_PLL_CNTL2,
286 .shift = 22,
287 .width = 2,
288 .flags = CLK_DIVIDER_POWER_OF_TWO,
289 },
290 .hw.init = &(struct clk_init_data){
291 .name = "hdmi_pll_od2",
292 .ops = &clk_regmap_divider_ro_ops,
293 .parent_hws = (const struct clk_hw *[]) {
294 &gxbb_hdmi_pll_od.hw
295 },
296 .num_parents = 1,
297 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
298 },
299 };
300
301 static struct clk_regmap gxbb_hdmi_pll = {
302 .data = &(struct clk_regmap_div_data){
303 .offset = HHI_HDMI_PLL_CNTL2,
304 .shift = 18,
305 .width = 2,
306 .flags = CLK_DIVIDER_POWER_OF_TWO,
307 },
308 .hw.init = &(struct clk_init_data){
309 .name = "hdmi_pll",
310 .ops = &clk_regmap_divider_ro_ops,
311 .parent_hws = (const struct clk_hw *[]) {
312 &gxbb_hdmi_pll_od2.hw
313 },
314 .num_parents = 1,
315 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
316 },
317 };
318
319 static struct clk_regmap gxl_hdmi_pll_od = {
320 .data = &(struct clk_regmap_div_data){
321 .offset = HHI_HDMI_PLL_CNTL + 8,
322 .shift = 21,
323 .width = 2,
324 .flags = CLK_DIVIDER_POWER_OF_TWO,
325 },
326 .hw.init = &(struct clk_init_data){
327 .name = "hdmi_pll_od",
328 .ops = &clk_regmap_divider_ro_ops,
329 .parent_hws = (const struct clk_hw *[]) {
330 &gxl_hdmi_pll_dco.hw
331 },
332 .num_parents = 1,
333 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
334 },
335 };
336
337 static struct clk_regmap gxl_hdmi_pll_od2 = {
338 .data = &(struct clk_regmap_div_data){
339 .offset = HHI_HDMI_PLL_CNTL + 8,
340 .shift = 23,
341 .width = 2,
342 .flags = CLK_DIVIDER_POWER_OF_TWO,
343 },
344 .hw.init = &(struct clk_init_data){
345 .name = "hdmi_pll_od2",
346 .ops = &clk_regmap_divider_ro_ops,
347 .parent_hws = (const struct clk_hw *[]) {
348 &gxl_hdmi_pll_od.hw
349 },
350 .num_parents = 1,
351 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
352 },
353 };
354
355 static struct clk_regmap gxl_hdmi_pll = {
356 .data = &(struct clk_regmap_div_data){
357 .offset = HHI_HDMI_PLL_CNTL + 8,
358 .shift = 19,
359 .width = 2,
360 .flags = CLK_DIVIDER_POWER_OF_TWO,
361 },
362 .hw.init = &(struct clk_init_data){
363 .name = "hdmi_pll",
364 .ops = &clk_regmap_divider_ro_ops,
365 .parent_hws = (const struct clk_hw *[]) {
366 &gxl_hdmi_pll_od2.hw
367 },
368 .num_parents = 1,
369 .flags = CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT,
370 },
371 };
372
373 static struct clk_regmap gxbb_sys_pll_dco = {
374 .data = &(struct meson_clk_pll_data){
375 .en = {
376 .reg_off = HHI_SYS_PLL_CNTL,
377 .shift = 30,
378 .width = 1,
379 },
380 .m = {
381 .reg_off = HHI_SYS_PLL_CNTL,
382 .shift = 0,
383 .width = 9,
384 },
385 .n = {
386 .reg_off = HHI_SYS_PLL_CNTL,
387 .shift = 9,
388 .width = 5,
389 },
390 .l = {
391 .reg_off = HHI_SYS_PLL_CNTL,
392 .shift = 31,
393 .width = 1,
394 },
395 .rst = {
396 .reg_off = HHI_SYS_PLL_CNTL,
397 .shift = 29,
398 .width = 1,
399 },
400 },
401 .hw.init = &(struct clk_init_data){
402 .name = "sys_pll_dco",
403 .ops = &meson_clk_pll_ro_ops,
404 .parent_data = &(const struct clk_parent_data) {
405 .fw_name = "xtal",
406 },
407 .num_parents = 1,
408 },
409 };
410
411 static struct clk_regmap gxbb_sys_pll = {
412 .data = &(struct clk_regmap_div_data){
413 .offset = HHI_SYS_PLL_CNTL,
414 .shift = 10,
415 .width = 2,
416 .flags = CLK_DIVIDER_POWER_OF_TWO,
417 },
418 .hw.init = &(struct clk_init_data){
419 .name = "sys_pll",
420 .ops = &clk_regmap_divider_ro_ops,
421 .parent_hws = (const struct clk_hw *[]) {
422 &gxbb_sys_pll_dco.hw
423 },
424 .num_parents = 1,
425 .flags = CLK_SET_RATE_PARENT,
426 },
427 };
428
429 static const struct reg_sequence gxbb_gp0_init_regs[] = {
430 { .reg = HHI_GP0_PLL_CNTL2, .def = 0x69c80000 },
431 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a5590c4 },
432 { .reg = HHI_GP0_PLL_CNTL4, .def = 0x0000500d },
433 };
434
435 static struct clk_regmap gxbb_gp0_pll_dco = {
436 .data = &(struct meson_clk_pll_data){
437 .en = {
438 .reg_off = HHI_GP0_PLL_CNTL,
439 .shift = 30,
440 .width = 1,
441 },
442 .m = {
443 .reg_off = HHI_GP0_PLL_CNTL,
444 .shift = 0,
445 .width = 9,
446 },
447 .n = {
448 .reg_off = HHI_GP0_PLL_CNTL,
449 .shift = 9,
450 .width = 5,
451 },
452 .l = {
453 .reg_off = HHI_GP0_PLL_CNTL,
454 .shift = 31,
455 .width = 1,
456 },
457 .rst = {
458 .reg_off = HHI_GP0_PLL_CNTL,
459 .shift = 29,
460 .width = 1,
461 },
462 .table = gxbb_gp0_pll_params_table,
463 .init_regs = gxbb_gp0_init_regs,
464 .init_count = ARRAY_SIZE(gxbb_gp0_init_regs),
465 },
466 .hw.init = &(struct clk_init_data){
467 .name = "gp0_pll_dco",
468 .ops = &meson_clk_pll_ops,
469 .parent_data = &(const struct clk_parent_data) {
470 .fw_name = "xtal",
471 },
472 .num_parents = 1,
473 },
474 };
475
476 static const struct reg_sequence gxl_gp0_init_regs[] = {
477 { .reg = HHI_GP0_PLL_CNTL1, .def = 0xc084b000 },
478 { .reg = HHI_GP0_PLL_CNTL2, .def = 0xb75020be },
479 { .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
480 { .reg = HHI_GP0_PLL_CNTL4, .def = 0xc000004d },
481 { .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
482 };
483
484 static struct clk_regmap gxl_gp0_pll_dco = {
485 .data = &(struct meson_clk_pll_data){
486 .en = {
487 .reg_off = HHI_GP0_PLL_CNTL,
488 .shift = 30,
489 .width = 1,
490 },
491 .m = {
492 .reg_off = HHI_GP0_PLL_CNTL,
493 .shift = 0,
494 .width = 9,
495 },
496 .n = {
497 .reg_off = HHI_GP0_PLL_CNTL,
498 .shift = 9,
499 .width = 5,
500 },
501 .frac = {
502 .reg_off = HHI_GP0_PLL_CNTL1,
503 .shift = 0,
504 .width = 10,
505 },
506 .l = {
507 .reg_off = HHI_GP0_PLL_CNTL,
508 .shift = 31,
509 .width = 1,
510 },
511 .rst = {
512 .reg_off = HHI_GP0_PLL_CNTL,
513 .shift = 29,
514 .width = 1,
515 },
516 .table = gxl_gp0_pll_params_table,
517 .init_regs = gxl_gp0_init_regs,
518 .init_count = ARRAY_SIZE(gxl_gp0_init_regs),
519 },
520 .hw.init = &(struct clk_init_data){
521 .name = "gp0_pll_dco",
522 .ops = &meson_clk_pll_ops,
523 .parent_data = &(const struct clk_parent_data) {
524 .fw_name = "xtal",
525 },
526 .num_parents = 1,
527 },
528 };
529
530 static struct clk_regmap gxbb_gp0_pll = {
531 .data = &(struct clk_regmap_div_data){
532 .offset = HHI_GP0_PLL_CNTL,
533 .shift = 16,
534 .width = 2,
535 .flags = CLK_DIVIDER_POWER_OF_TWO,
536 },
537 .hw.init = &(struct clk_init_data){
538 .name = "gp0_pll",
539 .ops = &clk_regmap_divider_ops,
540 .parent_data = &(const struct clk_parent_data) {
541 /*
542 * Note:
543 * GXL and GXBB have different gp0_pll_dco (with
544 * different struct clk_hw). We fallback to the global
545 * naming string mechanism so gp0_pll picks up the
546 * appropriate one.
547 */
548 .name = "gp0_pll_dco",
549 .index = -1,
550 },
551 .num_parents = 1,
552 .flags = CLK_SET_RATE_PARENT,
553 },
554 };
555
556 static struct clk_fixed_factor gxbb_fclk_div2_div = {
557 .mult = 1,
558 .div = 2,
559 .hw.init = &(struct clk_init_data){
560 .name = "fclk_div2_div",
561 .ops = &clk_fixed_factor_ops,
562 .parent_hws = (const struct clk_hw *[]) {
563 &gxbb_fixed_pll.hw
564 },
565 .num_parents = 1,
566 },
567 };
568
569 static struct clk_regmap gxbb_fclk_div2 = {
570 .data = &(struct clk_regmap_gate_data){
571 .offset = HHI_MPLL_CNTL6,
572 .bit_idx = 27,
573 },
574 .hw.init = &(struct clk_init_data){
575 .name = "fclk_div2",
576 .ops = &clk_regmap_gate_ops,
577 .parent_hws = (const struct clk_hw *[]) {
578 &gxbb_fclk_div2_div.hw
579 },
580 .num_parents = 1,
581 .flags = CLK_IS_CRITICAL,
582 },
583 };
584
585 static struct clk_fixed_factor gxbb_fclk_div3_div = {
586 .mult = 1,
587 .div = 3,
588 .hw.init = &(struct clk_init_data){
589 .name = "fclk_div3_div",
590 .ops = &clk_fixed_factor_ops,
591 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
592 .num_parents = 1,
593 },
594 };
595
596 static struct clk_regmap gxbb_fclk_div3 = {
597 .data = &(struct clk_regmap_gate_data){
598 .offset = HHI_MPLL_CNTL6,
599 .bit_idx = 28,
600 },
601 .hw.init = &(struct clk_init_data){
602 .name = "fclk_div3",
603 .ops = &clk_regmap_gate_ops,
604 .parent_hws = (const struct clk_hw *[]) {
605 &gxbb_fclk_div3_div.hw
606 },
607 .num_parents = 1,
608 /*
609 * FIXME:
610 * This clock, as fdiv2, is used by the SCPI FW and is required
611 * by the platform to operate correctly.
612 * Until the following condition are met, we need this clock to
613 * be marked as critical:
614 * a) The SCPI generic driver claims and enable all the clocks
615 * it needs
616 * b) CCF has a clock hand-off mechanism to make the sure the
617 * clock stays on until the proper driver comes along
618 */
619 .flags = CLK_IS_CRITICAL,
620 },
621 };
622
623 static struct clk_fixed_factor gxbb_fclk_div4_div = {
624 .mult = 1,
625 .div = 4,
626 .hw.init = &(struct clk_init_data){
627 .name = "fclk_div4_div",
628 .ops = &clk_fixed_factor_ops,
629 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
630 .num_parents = 1,
631 },
632 };
633
634 static struct clk_regmap gxbb_fclk_div4 = {
635 .data = &(struct clk_regmap_gate_data){
636 .offset = HHI_MPLL_CNTL6,
637 .bit_idx = 29,
638 },
639 .hw.init = &(struct clk_init_data){
640 .name = "fclk_div4",
641 .ops = &clk_regmap_gate_ops,
642 .parent_hws = (const struct clk_hw *[]) {
643 &gxbb_fclk_div4_div.hw
644 },
645 .num_parents = 1,
646 },
647 };
648
649 static struct clk_fixed_factor gxbb_fclk_div5_div = {
650 .mult = 1,
651 .div = 5,
652 .hw.init = &(struct clk_init_data){
653 .name = "fclk_div5_div",
654 .ops = &clk_fixed_factor_ops,
655 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
656 .num_parents = 1,
657 },
658 };
659
660 static struct clk_regmap gxbb_fclk_div5 = {
661 .data = &(struct clk_regmap_gate_data){
662 .offset = HHI_MPLL_CNTL6,
663 .bit_idx = 30,
664 },
665 .hw.init = &(struct clk_init_data){
666 .name = "fclk_div5",
667 .ops = &clk_regmap_gate_ops,
668 .parent_hws = (const struct clk_hw *[]) {
669 &gxbb_fclk_div5_div.hw
670 },
671 .num_parents = 1,
672 },
673 };
674
675 static struct clk_fixed_factor gxbb_fclk_div7_div = {
676 .mult = 1,
677 .div = 7,
678 .hw.init = &(struct clk_init_data){
679 .name = "fclk_div7_div",
680 .ops = &clk_fixed_factor_ops,
681 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
682 .num_parents = 1,
683 },
684 };
685
686 static struct clk_regmap gxbb_fclk_div7 = {
687 .data = &(struct clk_regmap_gate_data){
688 .offset = HHI_MPLL_CNTL6,
689 .bit_idx = 31,
690 },
691 .hw.init = &(struct clk_init_data){
692 .name = "fclk_div7",
693 .ops = &clk_regmap_gate_ops,
694 .parent_hws = (const struct clk_hw *[]) {
695 &gxbb_fclk_div7_div.hw
696 },
697 .num_parents = 1,
698 },
699 };
700
701 static struct clk_regmap gxbb_mpll_prediv = {
702 .data = &(struct clk_regmap_div_data){
703 .offset = HHI_MPLL_CNTL5,
704 .shift = 12,
705 .width = 1,
706 },
707 .hw.init = &(struct clk_init_data){
708 .name = "mpll_prediv",
709 .ops = &clk_regmap_divider_ro_ops,
710 .parent_hws = (const struct clk_hw *[]) { &gxbb_fixed_pll.hw },
711 .num_parents = 1,
712 },
713 };
714
715 static struct clk_regmap gxbb_mpll0_div = {
716 .data = &(struct meson_clk_mpll_data){
717 .sdm = {
718 .reg_off = HHI_MPLL_CNTL7,
719 .shift = 0,
720 .width = 14,
721 },
722 .sdm_en = {
723 .reg_off = HHI_MPLL_CNTL,
724 .shift = 25,
725 .width = 1,
726 },
727 .n2 = {
728 .reg_off = HHI_MPLL_CNTL7,
729 .shift = 16,
730 .width = 9,
731 },
732 },
733 .hw.init = &(struct clk_init_data){
734 .name = "mpll0_div",
735 .ops = &meson_clk_mpll_ops,
736 .parent_hws = (const struct clk_hw *[]) {
737 &gxbb_mpll_prediv.hw
738 },
739 .num_parents = 1,
740 },
741 };
742
743 static struct clk_regmap gxl_mpll0_div = {
744 .data = &(struct meson_clk_mpll_data){
745 .sdm = {
746 .reg_off = HHI_MPLL_CNTL7,
747 .shift = 0,
748 .width = 14,
749 },
750 .sdm_en = {
751 .reg_off = HHI_MPLL_CNTL7,
752 .shift = 15,
753 .width = 1,
754 },
755 .n2 = {
756 .reg_off = HHI_MPLL_CNTL7,
757 .shift = 16,
758 .width = 9,
759 },
760 },
761 .hw.init = &(struct clk_init_data){
762 .name = "mpll0_div",
763 .ops = &meson_clk_mpll_ops,
764 .parent_hws = (const struct clk_hw *[]) {
765 &gxbb_mpll_prediv.hw
766 },
767 .num_parents = 1,
768 },
769 };
770
771 static struct clk_regmap gxbb_mpll0 = {
772 .data = &(struct clk_regmap_gate_data){
773 .offset = HHI_MPLL_CNTL7,
774 .bit_idx = 14,
775 },
776 .hw.init = &(struct clk_init_data){
777 .name = "mpll0",
778 .ops = &clk_regmap_gate_ops,
779 .parent_data = &(const struct clk_parent_data) {
780 /*
781 * Note:
782 * GXL and GXBB have different SDM_EN registers. We
783 * fallback to the global naming string mechanism so
784 * mpll0_div picks up the appropriate one.
785 */
786 .name = "mpll0_div",
787 .index = -1,
788 },
789 .num_parents = 1,
790 .flags = CLK_SET_RATE_PARENT,
791 },
792 };
793
794 static struct clk_regmap gxbb_mpll1_div = {
795 .data = &(struct meson_clk_mpll_data){
796 .sdm = {
797 .reg_off = HHI_MPLL_CNTL8,
798 .shift = 0,
799 .width = 14,
800 },
801 .sdm_en = {
802 .reg_off = HHI_MPLL_CNTL8,
803 .shift = 15,
804 .width = 1,
805 },
806 .n2 = {
807 .reg_off = HHI_MPLL_CNTL8,
808 .shift = 16,
809 .width = 9,
810 },
811 },
812 .hw.init = &(struct clk_init_data){
813 .name = "mpll1_div",
814 .ops = &meson_clk_mpll_ops,
815 .parent_hws = (const struct clk_hw *[]) {
816 &gxbb_mpll_prediv.hw
817 },
818 .num_parents = 1,
819 },
820 };
821
822 static struct clk_regmap gxbb_mpll1 = {
823 .data = &(struct clk_regmap_gate_data){
824 .offset = HHI_MPLL_CNTL8,
825 .bit_idx = 14,
826 },
827 .hw.init = &(struct clk_init_data){
828 .name = "mpll1",
829 .ops = &clk_regmap_gate_ops,
830 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll1_div.hw },
831 .num_parents = 1,
832 .flags = CLK_SET_RATE_PARENT,
833 },
834 };
835
836 static struct clk_regmap gxbb_mpll2_div = {
837 .data = &(struct meson_clk_mpll_data){
838 .sdm = {
839 .reg_off = HHI_MPLL_CNTL9,
840 .shift = 0,
841 .width = 14,
842 },
843 .sdm_en = {
844 .reg_off = HHI_MPLL_CNTL9,
845 .shift = 15,
846 .width = 1,
847 },
848 .n2 = {
849 .reg_off = HHI_MPLL_CNTL9,
850 .shift = 16,
851 .width = 9,
852 },
853 },
854 .hw.init = &(struct clk_init_data){
855 .name = "mpll2_div",
856 .ops = &meson_clk_mpll_ops,
857 .parent_hws = (const struct clk_hw *[]) {
858 &gxbb_mpll_prediv.hw
859 },
860 .num_parents = 1,
861 },
862 };
863
864 static struct clk_regmap gxbb_mpll2 = {
865 .data = &(struct clk_regmap_gate_data){
866 .offset = HHI_MPLL_CNTL9,
867 .bit_idx = 14,
868 },
869 .hw.init = &(struct clk_init_data){
870 .name = "mpll2",
871 .ops = &clk_regmap_gate_ops,
872 .parent_hws = (const struct clk_hw *[]) { &gxbb_mpll2_div.hw },
873 .num_parents = 1,
874 .flags = CLK_SET_RATE_PARENT,
875 },
876 };
877
878 static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
879 static const struct clk_parent_data clk81_parent_data[] = {
880 { .fw_name = "xtal", },
881 { .hw = &gxbb_fclk_div7.hw },
882 { .hw = &gxbb_mpll1.hw },
883 { .hw = &gxbb_mpll2.hw },
884 { .hw = &gxbb_fclk_div4.hw },
885 { .hw = &gxbb_fclk_div3.hw },
886 { .hw = &gxbb_fclk_div5.hw },
887 };
888
889 static struct clk_regmap gxbb_mpeg_clk_sel = {
890 .data = &(struct clk_regmap_mux_data){
891 .offset = HHI_MPEG_CLK_CNTL,
892 .mask = 0x7,
893 .shift = 12,
894 .table = mux_table_clk81,
895 },
896 .hw.init = &(struct clk_init_data){
897 .name = "mpeg_clk_sel",
898 .ops = &clk_regmap_mux_ro_ops,
899 /*
900 * bits 14:12 selects from 8 possible parents:
901 * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
902 * fclk_div4, fclk_div3, fclk_div5
903 */
904 .parent_data = clk81_parent_data,
905 .num_parents = ARRAY_SIZE(clk81_parent_data),
906 },
907 };
908
909 static struct clk_regmap gxbb_mpeg_clk_div = {
910 .data = &(struct clk_regmap_div_data){
911 .offset = HHI_MPEG_CLK_CNTL,
912 .shift = 0,
913 .width = 7,
914 },
915 .hw.init = &(struct clk_init_data){
916 .name = "mpeg_clk_div",
917 .ops = &clk_regmap_divider_ro_ops,
918 .parent_hws = (const struct clk_hw *[]) {
919 &gxbb_mpeg_clk_sel.hw
920 },
921 .num_parents = 1,
922 },
923 };
924
925 /* the mother of dragons gates */
926 static struct clk_regmap gxbb_clk81 = {
927 .data = &(struct clk_regmap_gate_data){
928 .offset = HHI_MPEG_CLK_CNTL,
929 .bit_idx = 7,
930 },
931 .hw.init = &(struct clk_init_data){
932 .name = "clk81",
933 .ops = &clk_regmap_gate_ops,
934 .parent_hws = (const struct clk_hw *[]) {
935 &gxbb_mpeg_clk_div.hw
936 },
937 .num_parents = 1,
938 .flags = CLK_IS_CRITICAL,
939 },
940 };
941
942 static struct clk_regmap gxbb_sar_adc_clk_sel = {
943 .data = &(struct clk_regmap_mux_data){
944 .offset = HHI_SAR_CLK_CNTL,
945 .mask = 0x3,
946 .shift = 9,
947 },
948 .hw.init = &(struct clk_init_data){
949 .name = "sar_adc_clk_sel",
950 .ops = &clk_regmap_mux_ops,
951 /* NOTE: The datasheet doesn't list the parents for bit 10 */
952 .parent_data = (const struct clk_parent_data []) {
953 { .fw_name = "xtal", },
954 { .hw = &gxbb_clk81.hw },
955 },
956 .num_parents = 2,
957 },
958 };
959
960 static struct clk_regmap gxbb_sar_adc_clk_div = {
961 .data = &(struct clk_regmap_div_data){
962 .offset = HHI_SAR_CLK_CNTL,
963 .shift = 0,
964 .width = 8,
965 },
966 .hw.init = &(struct clk_init_data){
967 .name = "sar_adc_clk_div",
968 .ops = &clk_regmap_divider_ops,
969 .parent_hws = (const struct clk_hw *[]) {
970 &gxbb_sar_adc_clk_sel.hw
971 },
972 .num_parents = 1,
973 .flags = CLK_SET_RATE_PARENT,
974 },
975 };
976
977 static struct clk_regmap gxbb_sar_adc_clk = {
978 .data = &(struct clk_regmap_gate_data){
979 .offset = HHI_SAR_CLK_CNTL,
980 .bit_idx = 8,
981 },
982 .hw.init = &(struct clk_init_data){
983 .name = "sar_adc_clk",
984 .ops = &clk_regmap_gate_ops,
985 .parent_hws = (const struct clk_hw *[]) {
986 &gxbb_sar_adc_clk_div.hw
987 },
988 .num_parents = 1,
989 .flags = CLK_SET_RATE_PARENT,
990 },
991 };
992
993 /*
994 * The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
995 * muxed by a glitch-free switch. The CCF can manage this glitch-free
996 * mux because it does top-to-bottom updates the each clock tree and
997 * switches to the "inactive" one when CLK_SET_RATE_GATE is set.
998 */
999
1000 static const struct clk_parent_data gxbb_mali_0_1_parent_data[] = {
1001 { .fw_name = "xtal", },
1002 { .hw = &gxbb_gp0_pll.hw },
1003 { .hw = &gxbb_mpll2.hw },
1004 { .hw = &gxbb_mpll1.hw },
1005 { .hw = &gxbb_fclk_div7.hw },
1006 { .hw = &gxbb_fclk_div4.hw },
1007 { .hw = &gxbb_fclk_div3.hw },
1008 { .hw = &gxbb_fclk_div5.hw },
1009 };
1010
1011 static struct clk_regmap gxbb_mali_0_sel = {
1012 .data = &(struct clk_regmap_mux_data){
1013 .offset = HHI_MALI_CLK_CNTL,
1014 .mask = 0x7,
1015 .shift = 9,
1016 },
1017 .hw.init = &(struct clk_init_data){
1018 .name = "mali_0_sel",
1019 .ops = &clk_regmap_mux_ops,
1020 .parent_data = gxbb_mali_0_1_parent_data,
1021 .num_parents = 8,
1022 /*
1023 * Don't request the parent to change the rate because
1024 * all GPU frequencies can be derived from the fclk_*
1025 * clocks and one special GP0_PLL setting. This is
1026 * important because we need the MPLL clocks for audio.
1027 */
1028 .flags = 0,
1029 },
1030 };
1031
1032 static struct clk_regmap gxbb_mali_0_div = {
1033 .data = &(struct clk_regmap_div_data){
1034 .offset = HHI_MALI_CLK_CNTL,
1035 .shift = 0,
1036 .width = 7,
1037 },
1038 .hw.init = &(struct clk_init_data){
1039 .name = "mali_0_div",
1040 .ops = &clk_regmap_divider_ops,
1041 .parent_hws = (const struct clk_hw *[]) {
1042 &gxbb_mali_0_sel.hw
1043 },
1044 .num_parents = 1,
1045 .flags = CLK_SET_RATE_PARENT,
1046 },
1047 };
1048
1049 static struct clk_regmap gxbb_mali_0 = {
1050 .data = &(struct clk_regmap_gate_data){
1051 .offset = HHI_MALI_CLK_CNTL,
1052 .bit_idx = 8,
1053 },
1054 .hw.init = &(struct clk_init_data){
1055 .name = "mali_0",
1056 .ops = &clk_regmap_gate_ops,
1057 .parent_hws = (const struct clk_hw *[]) {
1058 &gxbb_mali_0_div.hw
1059 },
1060 .num_parents = 1,
1061 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1062 },
1063 };
1064
1065 static struct clk_regmap gxbb_mali_1_sel = {
1066 .data = &(struct clk_regmap_mux_data){
1067 .offset = HHI_MALI_CLK_CNTL,
1068 .mask = 0x7,
1069 .shift = 25,
1070 },
1071 .hw.init = &(struct clk_init_data){
1072 .name = "mali_1_sel",
1073 .ops = &clk_regmap_mux_ops,
1074 .parent_data = gxbb_mali_0_1_parent_data,
1075 .num_parents = 8,
1076 /*
1077 * Don't request the parent to change the rate because
1078 * all GPU frequencies can be derived from the fclk_*
1079 * clocks and one special GP0_PLL setting. This is
1080 * important because we need the MPLL clocks for audio.
1081 */
1082 .flags = 0,
1083 },
1084 };
1085
1086 static struct clk_regmap gxbb_mali_1_div = {
1087 .data = &(struct clk_regmap_div_data){
1088 .offset = HHI_MALI_CLK_CNTL,
1089 .shift = 16,
1090 .width = 7,
1091 },
1092 .hw.init = &(struct clk_init_data){
1093 .name = "mali_1_div",
1094 .ops = &clk_regmap_divider_ops,
1095 .parent_hws = (const struct clk_hw *[]) {
1096 &gxbb_mali_1_sel.hw
1097 },
1098 .num_parents = 1,
1099 .flags = CLK_SET_RATE_PARENT,
1100 },
1101 };
1102
1103 static struct clk_regmap gxbb_mali_1 = {
1104 .data = &(struct clk_regmap_gate_data){
1105 .offset = HHI_MALI_CLK_CNTL,
1106 .bit_idx = 24,
1107 },
1108 .hw.init = &(struct clk_init_data){
1109 .name = "mali_1",
1110 .ops = &clk_regmap_gate_ops,
1111 .parent_hws = (const struct clk_hw *[]) {
1112 &gxbb_mali_1_div.hw
1113 },
1114 .num_parents = 1,
1115 .flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
1116 },
1117 };
1118
1119 static const struct clk_hw *gxbb_mali_parent_hws[] = {
1120 &gxbb_mali_0.hw,
1121 &gxbb_mali_1.hw,
1122 };
1123
1124 static struct clk_regmap gxbb_mali = {
1125 .data = &(struct clk_regmap_mux_data){
1126 .offset = HHI_MALI_CLK_CNTL,
1127 .mask = 1,
1128 .shift = 31,
1129 },
1130 .hw.init = &(struct clk_init_data){
1131 .name = "mali",
1132 .ops = &clk_regmap_mux_ops,
1133 .parent_hws = gxbb_mali_parent_hws,
1134 .num_parents = 2,
1135 .flags = CLK_SET_RATE_PARENT,
1136 },
1137 };
1138
1139 static struct clk_regmap gxbb_cts_amclk_sel = {
1140 .data = &(struct clk_regmap_mux_data){
1141 .offset = HHI_AUD_CLK_CNTL,
1142 .mask = 0x3,
1143 .shift = 9,
1144 .table = (u32[]){ 1, 2, 3 },
1145 .flags = CLK_MUX_ROUND_CLOSEST,
1146 },
1147 .hw.init = &(struct clk_init_data){
1148 .name = "cts_amclk_sel",
1149 .ops = &clk_regmap_mux_ops,
1150 .parent_hws = (const struct clk_hw *[]) {
1151 &gxbb_mpll0.hw,
1152 &gxbb_mpll1.hw,
1153 &gxbb_mpll2.hw,
1154 },
1155 .num_parents = 3,
1156 },
1157 };
1158
1159 static struct clk_regmap gxbb_cts_amclk_div = {
1160 .data = &(struct clk_regmap_div_data) {
1161 .offset = HHI_AUD_CLK_CNTL,
1162 .shift = 0,
1163 .width = 8,
1164 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1165 },
1166 .hw.init = &(struct clk_init_data){
1167 .name = "cts_amclk_div",
1168 .ops = &clk_regmap_divider_ops,
1169 .parent_hws = (const struct clk_hw *[]) {
1170 &gxbb_cts_amclk_sel.hw
1171 },
1172 .num_parents = 1,
1173 .flags = CLK_SET_RATE_PARENT,
1174 },
1175 };
1176
1177 static struct clk_regmap gxbb_cts_amclk = {
1178 .data = &(struct clk_regmap_gate_data){
1179 .offset = HHI_AUD_CLK_CNTL,
1180 .bit_idx = 8,
1181 },
1182 .hw.init = &(struct clk_init_data){
1183 .name = "cts_amclk",
1184 .ops = &clk_regmap_gate_ops,
1185 .parent_hws = (const struct clk_hw *[]) {
1186 &gxbb_cts_amclk_div.hw
1187 },
1188 .num_parents = 1,
1189 .flags = CLK_SET_RATE_PARENT,
1190 },
1191 };
1192
1193 static struct clk_regmap gxbb_cts_mclk_i958_sel = {
1194 .data = &(struct clk_regmap_mux_data){
1195 .offset = HHI_AUD_CLK_CNTL2,
1196 .mask = 0x3,
1197 .shift = 25,
1198 .table = (u32[]){ 1, 2, 3 },
1199 .flags = CLK_MUX_ROUND_CLOSEST,
1200 },
1201 .hw.init = &(struct clk_init_data) {
1202 .name = "cts_mclk_i958_sel",
1203 .ops = &clk_regmap_mux_ops,
1204 .parent_hws = (const struct clk_hw *[]) {
1205 &gxbb_mpll0.hw,
1206 &gxbb_mpll1.hw,
1207 &gxbb_mpll2.hw,
1208 },
1209 .num_parents = 3,
1210 },
1211 };
1212
1213 static struct clk_regmap gxbb_cts_mclk_i958_div = {
1214 .data = &(struct clk_regmap_div_data){
1215 .offset = HHI_AUD_CLK_CNTL2,
1216 .shift = 16,
1217 .width = 8,
1218 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1219 },
1220 .hw.init = &(struct clk_init_data) {
1221 .name = "cts_mclk_i958_div",
1222 .ops = &clk_regmap_divider_ops,
1223 .parent_hws = (const struct clk_hw *[]) {
1224 &gxbb_cts_mclk_i958_sel.hw
1225 },
1226 .num_parents = 1,
1227 .flags = CLK_SET_RATE_PARENT,
1228 },
1229 };
1230
1231 static struct clk_regmap gxbb_cts_mclk_i958 = {
1232 .data = &(struct clk_regmap_gate_data){
1233 .offset = HHI_AUD_CLK_CNTL2,
1234 .bit_idx = 24,
1235 },
1236 .hw.init = &(struct clk_init_data){
1237 .name = "cts_mclk_i958",
1238 .ops = &clk_regmap_gate_ops,
1239 .parent_hws = (const struct clk_hw *[]) {
1240 &gxbb_cts_mclk_i958_div.hw
1241 },
1242 .num_parents = 1,
1243 .flags = CLK_SET_RATE_PARENT,
1244 },
1245 };
1246
1247 static struct clk_regmap gxbb_cts_i958 = {
1248 .data = &(struct clk_regmap_mux_data){
1249 .offset = HHI_AUD_CLK_CNTL2,
1250 .mask = 0x1,
1251 .shift = 27,
1252 },
1253 .hw.init = &(struct clk_init_data){
1254 .name = "cts_i958",
1255 .ops = &clk_regmap_mux_ops,
1256 .parent_hws = (const struct clk_hw *[]) {
1257 &gxbb_cts_amclk.hw,
1258 &gxbb_cts_mclk_i958.hw
1259 },
1260 .num_parents = 2,
1261 /*
1262 *The parent is specific to origin of the audio data. Let the
1263 * consumer choose the appropriate parent
1264 */
1265 .flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
1266 },
1267 };
1268
1269 static const struct clk_parent_data gxbb_32k_clk_parent_data[] = {
1270 { .fw_name = "xtal", },
1271 /*
1272 * FIXME: This clock is provided by the ao clock controller but the
1273 * clock is not yet part of the binding of this controller, so string
1274 * name must be use to set this parent.
1275 */
1276 { .name = "cts_slow_oscin", .index = -1 },
1277 { .hw = &gxbb_fclk_div3.hw },
1278 { .hw = &gxbb_fclk_div5.hw },
1279 };
1280
1281 static struct clk_regmap gxbb_32k_clk_sel = {
1282 .data = &(struct clk_regmap_mux_data){
1283 .offset = HHI_32K_CLK_CNTL,
1284 .mask = 0x3,
1285 .shift = 16,
1286 },
1287 .hw.init = &(struct clk_init_data){
1288 .name = "32k_clk_sel",
1289 .ops = &clk_regmap_mux_ops,
1290 .parent_data = gxbb_32k_clk_parent_data,
1291 .num_parents = 4,
1292 .flags = CLK_SET_RATE_PARENT,
1293 },
1294 };
1295
1296 static struct clk_regmap gxbb_32k_clk_div = {
1297 .data = &(struct clk_regmap_div_data){
1298 .offset = HHI_32K_CLK_CNTL,
1299 .shift = 0,
1300 .width = 14,
1301 },
1302 .hw.init = &(struct clk_init_data){
1303 .name = "32k_clk_div",
1304 .ops = &clk_regmap_divider_ops,
1305 .parent_hws = (const struct clk_hw *[]) {
1306 &gxbb_32k_clk_sel.hw
1307 },
1308 .num_parents = 1,
1309 .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
1310 },
1311 };
1312
1313 static struct clk_regmap gxbb_32k_clk = {
1314 .data = &(struct clk_regmap_gate_data){
1315 .offset = HHI_32K_CLK_CNTL,
1316 .bit_idx = 15,
1317 },
1318 .hw.init = &(struct clk_init_data){
1319 .name = "32k_clk",
1320 .ops = &clk_regmap_gate_ops,
1321 .parent_hws = (const struct clk_hw *[]) {
1322 &gxbb_32k_clk_div.hw
1323 },
1324 .num_parents = 1,
1325 .flags = CLK_SET_RATE_PARENT,
1326 },
1327 };
1328
1329 static const struct clk_parent_data gxbb_sd_emmc_clk0_parent_data[] = {
1330 { .fw_name = "xtal", },
1331 { .hw = &gxbb_fclk_div2.hw },
1332 { .hw = &gxbb_fclk_div3.hw },
1333 { .hw = &gxbb_fclk_div5.hw },
1334 { .hw = &gxbb_fclk_div7.hw },
1335 /*
1336 * Following these parent clocks, we should also have had mpll2, mpll3
1337 * and gp0_pll but these clocks are too precious to be used here. All
1338 * the necessary rates for MMC and NAND operation can be acheived using
1339 * xtal or fclk_div clocks
1340 */
1341 };
1342
1343 /* SDIO clock */
1344 static struct clk_regmap gxbb_sd_emmc_a_clk0_sel = {
1345 .data = &(struct clk_regmap_mux_data){
1346 .offset = HHI_SD_EMMC_CLK_CNTL,
1347 .mask = 0x7,
1348 .shift = 9,
1349 },
1350 .hw.init = &(struct clk_init_data) {
1351 .name = "sd_emmc_a_clk0_sel",
1352 .ops = &clk_regmap_mux_ops,
1353 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1354 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1355 .flags = CLK_SET_RATE_PARENT,
1356 },
1357 };
1358
1359 static struct clk_regmap gxbb_sd_emmc_a_clk0_div = {
1360 .data = &(struct clk_regmap_div_data){
1361 .offset = HHI_SD_EMMC_CLK_CNTL,
1362 .shift = 0,
1363 .width = 7,
1364 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1365 },
1366 .hw.init = &(struct clk_init_data) {
1367 .name = "sd_emmc_a_clk0_div",
1368 .ops = &clk_regmap_divider_ops,
1369 .parent_hws = (const struct clk_hw *[]) {
1370 &gxbb_sd_emmc_a_clk0_sel.hw
1371 },
1372 .num_parents = 1,
1373 .flags = CLK_SET_RATE_PARENT,
1374 },
1375 };
1376
1377 static struct clk_regmap gxbb_sd_emmc_a_clk0 = {
1378 .data = &(struct clk_regmap_gate_data){
1379 .offset = HHI_SD_EMMC_CLK_CNTL,
1380 .bit_idx = 7,
1381 },
1382 .hw.init = &(struct clk_init_data){
1383 .name = "sd_emmc_a_clk0",
1384 .ops = &clk_regmap_gate_ops,
1385 .parent_hws = (const struct clk_hw *[]) {
1386 &gxbb_sd_emmc_a_clk0_div.hw
1387 },
1388 .num_parents = 1,
1389 .flags = CLK_SET_RATE_PARENT,
1390 },
1391 };
1392
1393 /* SDcard clock */
1394 static struct clk_regmap gxbb_sd_emmc_b_clk0_sel = {
1395 .data = &(struct clk_regmap_mux_data){
1396 .offset = HHI_SD_EMMC_CLK_CNTL,
1397 .mask = 0x7,
1398 .shift = 25,
1399 },
1400 .hw.init = &(struct clk_init_data) {
1401 .name = "sd_emmc_b_clk0_sel",
1402 .ops = &clk_regmap_mux_ops,
1403 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1404 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1405 .flags = CLK_SET_RATE_PARENT,
1406 },
1407 };
1408
1409 static struct clk_regmap gxbb_sd_emmc_b_clk0_div = {
1410 .data = &(struct clk_regmap_div_data){
1411 .offset = HHI_SD_EMMC_CLK_CNTL,
1412 .shift = 16,
1413 .width = 7,
1414 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1415 },
1416 .hw.init = &(struct clk_init_data) {
1417 .name = "sd_emmc_b_clk0_div",
1418 .ops = &clk_regmap_divider_ops,
1419 .parent_hws = (const struct clk_hw *[]) {
1420 &gxbb_sd_emmc_b_clk0_sel.hw
1421 },
1422 .num_parents = 1,
1423 .flags = CLK_SET_RATE_PARENT,
1424 },
1425 };
1426
1427 static struct clk_regmap gxbb_sd_emmc_b_clk0 = {
1428 .data = &(struct clk_regmap_gate_data){
1429 .offset = HHI_SD_EMMC_CLK_CNTL,
1430 .bit_idx = 23,
1431 },
1432 .hw.init = &(struct clk_init_data){
1433 .name = "sd_emmc_b_clk0",
1434 .ops = &clk_regmap_gate_ops,
1435 .parent_hws = (const struct clk_hw *[]) {
1436 &gxbb_sd_emmc_b_clk0_div.hw
1437 },
1438 .num_parents = 1,
1439 .flags = CLK_SET_RATE_PARENT,
1440 },
1441 };
1442
1443 /* EMMC/NAND clock */
1444 static struct clk_regmap gxbb_sd_emmc_c_clk0_sel = {
1445 .data = &(struct clk_regmap_mux_data){
1446 .offset = HHI_NAND_CLK_CNTL,
1447 .mask = 0x7,
1448 .shift = 9,
1449 },
1450 .hw.init = &(struct clk_init_data) {
1451 .name = "sd_emmc_c_clk0_sel",
1452 .ops = &clk_regmap_mux_ops,
1453 .parent_data = gxbb_sd_emmc_clk0_parent_data,
1454 .num_parents = ARRAY_SIZE(gxbb_sd_emmc_clk0_parent_data),
1455 .flags = CLK_SET_RATE_PARENT,
1456 },
1457 };
1458
1459 static struct clk_regmap gxbb_sd_emmc_c_clk0_div = {
1460 .data = &(struct clk_regmap_div_data){
1461 .offset = HHI_NAND_CLK_CNTL,
1462 .shift = 0,
1463 .width = 7,
1464 .flags = CLK_DIVIDER_ROUND_CLOSEST,
1465 },
1466 .hw.init = &(struct clk_init_data) {
1467 .name = "sd_emmc_c_clk0_div",
1468 .ops = &clk_regmap_divider_ops,
1469 .parent_hws = (const struct clk_hw *[]) {
1470 &gxbb_sd_emmc_c_clk0_sel.hw
1471 },
1472 .num_parents = 1,
1473 .flags = CLK_SET_RATE_PARENT,
1474 },
1475 };
1476
1477 static struct clk_regmap gxbb_sd_emmc_c_clk0 = {
1478 .data = &(struct clk_regmap_gate_data){
1479 .offset = HHI_NAND_CLK_CNTL,
1480 .bit_idx = 7,
1481 },
1482 .hw.init = &(struct clk_init_data){
1483 .name = "sd_emmc_c_clk0",
1484 .ops = &clk_regmap_gate_ops,
1485 .parent_hws = (const struct clk_hw *[]) {
1486 &gxbb_sd_emmc_c_clk0_div.hw
1487 },
1488 .num_parents = 1,
1489 .flags = CLK_SET_RATE_PARENT,
1490 },
1491 };
1492
1493 /* VPU Clock */
1494
1495 static const struct clk_hw *gxbb_vpu_parent_hws[] = {
1496 &gxbb_fclk_div4.hw,
1497 &gxbb_fclk_div3.hw,
1498 &gxbb_fclk_div5.hw,
1499 &gxbb_fclk_div7.hw,
1500 };
1501
1502 static struct clk_regmap gxbb_vpu_0_sel = {
1503 .data = &(struct clk_regmap_mux_data){
1504 .offset = HHI_VPU_CLK_CNTL,
1505 .mask = 0x3,
1506 .shift = 9,
1507 },
1508 .hw.init = &(struct clk_init_data){
1509 .name = "vpu_0_sel",
1510 .ops = &clk_regmap_mux_ops,
1511 /*
1512 * bits 9:10 selects from 4 possible parents:
1513 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1514 */
1515 .parent_hws = gxbb_vpu_parent_hws,
1516 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1517 .flags = CLK_SET_RATE_NO_REPARENT,
1518 },
1519 };
1520
1521 static struct clk_regmap gxbb_vpu_0_div = {
1522 .data = &(struct clk_regmap_div_data){
1523 .offset = HHI_VPU_CLK_CNTL,
1524 .shift = 0,
1525 .width = 7,
1526 },
1527 .hw.init = &(struct clk_init_data){
1528 .name = "vpu_0_div",
1529 .ops = &clk_regmap_divider_ops,
1530 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_sel.hw },
1531 .num_parents = 1,
1532 .flags = CLK_SET_RATE_PARENT,
1533 },
1534 };
1535
1536 static struct clk_regmap gxbb_vpu_0 = {
1537 .data = &(struct clk_regmap_gate_data){
1538 .offset = HHI_VPU_CLK_CNTL,
1539 .bit_idx = 8,
1540 },
1541 .hw.init = &(struct clk_init_data) {
1542 .name = "vpu_0",
1543 .ops = &clk_regmap_gate_ops,
1544 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_0_div.hw },
1545 .num_parents = 1,
1546 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1547 },
1548 };
1549
1550 static struct clk_regmap gxbb_vpu_1_sel = {
1551 .data = &(struct clk_regmap_mux_data){
1552 .offset = HHI_VPU_CLK_CNTL,
1553 .mask = 0x3,
1554 .shift = 25,
1555 },
1556 .hw.init = &(struct clk_init_data){
1557 .name = "vpu_1_sel",
1558 .ops = &clk_regmap_mux_ops,
1559 /*
1560 * bits 25:26 selects from 4 possible parents:
1561 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1562 */
1563 .parent_hws = gxbb_vpu_parent_hws,
1564 .num_parents = ARRAY_SIZE(gxbb_vpu_parent_hws),
1565 .flags = CLK_SET_RATE_NO_REPARENT,
1566 },
1567 };
1568
1569 static struct clk_regmap gxbb_vpu_1_div = {
1570 .data = &(struct clk_regmap_div_data){
1571 .offset = HHI_VPU_CLK_CNTL,
1572 .shift = 16,
1573 .width = 7,
1574 },
1575 .hw.init = &(struct clk_init_data){
1576 .name = "vpu_1_div",
1577 .ops = &clk_regmap_divider_ops,
1578 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_sel.hw },
1579 .num_parents = 1,
1580 .flags = CLK_SET_RATE_PARENT,
1581 },
1582 };
1583
1584 static struct clk_regmap gxbb_vpu_1 = {
1585 .data = &(struct clk_regmap_gate_data){
1586 .offset = HHI_VPU_CLK_CNTL,
1587 .bit_idx = 24,
1588 },
1589 .hw.init = &(struct clk_init_data) {
1590 .name = "vpu_1",
1591 .ops = &clk_regmap_gate_ops,
1592 .parent_hws = (const struct clk_hw *[]) { &gxbb_vpu_1_div.hw },
1593 .num_parents = 1,
1594 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1595 },
1596 };
1597
1598 static struct clk_regmap gxbb_vpu = {
1599 .data = &(struct clk_regmap_mux_data){
1600 .offset = HHI_VPU_CLK_CNTL,
1601 .mask = 1,
1602 .shift = 31,
1603 },
1604 .hw.init = &(struct clk_init_data){
1605 .name = "vpu",
1606 .ops = &clk_regmap_mux_ops,
1607 /*
1608 * bit 31 selects from 2 possible parents:
1609 * vpu_0 or vpu_1
1610 */
1611 .parent_hws = (const struct clk_hw *[]) {
1612 &gxbb_vpu_0.hw,
1613 &gxbb_vpu_1.hw
1614 },
1615 .num_parents = 2,
1616 .flags = CLK_SET_RATE_NO_REPARENT,
1617 },
1618 };
1619
1620 /* VAPB Clock */
1621
1622 static const struct clk_hw *gxbb_vapb_parent_hws[] = {
1623 &gxbb_fclk_div4.hw,
1624 &gxbb_fclk_div3.hw,
1625 &gxbb_fclk_div5.hw,
1626 &gxbb_fclk_div7.hw,
1627 };
1628
1629 static struct clk_regmap gxbb_vapb_0_sel = {
1630 .data = &(struct clk_regmap_mux_data){
1631 .offset = HHI_VAPBCLK_CNTL,
1632 .mask = 0x3,
1633 .shift = 9,
1634 },
1635 .hw.init = &(struct clk_init_data){
1636 .name = "vapb_0_sel",
1637 .ops = &clk_regmap_mux_ops,
1638 /*
1639 * bits 9:10 selects from 4 possible parents:
1640 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1641 */
1642 .parent_hws = gxbb_vapb_parent_hws,
1643 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1644 .flags = CLK_SET_RATE_NO_REPARENT,
1645 },
1646 };
1647
1648 static struct clk_regmap gxbb_vapb_0_div = {
1649 .data = &(struct clk_regmap_div_data){
1650 .offset = HHI_VAPBCLK_CNTL,
1651 .shift = 0,
1652 .width = 7,
1653 },
1654 .hw.init = &(struct clk_init_data){
1655 .name = "vapb_0_div",
1656 .ops = &clk_regmap_divider_ops,
1657 .parent_hws = (const struct clk_hw *[]) {
1658 &gxbb_vapb_0_sel.hw
1659 },
1660 .num_parents = 1,
1661 .flags = CLK_SET_RATE_PARENT,
1662 },
1663 };
1664
1665 static struct clk_regmap gxbb_vapb_0 = {
1666 .data = &(struct clk_regmap_gate_data){
1667 .offset = HHI_VAPBCLK_CNTL,
1668 .bit_idx = 8,
1669 },
1670 .hw.init = &(struct clk_init_data) {
1671 .name = "vapb_0",
1672 .ops = &clk_regmap_gate_ops,
1673 .parent_hws = (const struct clk_hw *[]) {
1674 &gxbb_vapb_0_div.hw
1675 },
1676 .num_parents = 1,
1677 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1678 },
1679 };
1680
1681 static struct clk_regmap gxbb_vapb_1_sel = {
1682 .data = &(struct clk_regmap_mux_data){
1683 .offset = HHI_VAPBCLK_CNTL,
1684 .mask = 0x3,
1685 .shift = 25,
1686 },
1687 .hw.init = &(struct clk_init_data){
1688 .name = "vapb_1_sel",
1689 .ops = &clk_regmap_mux_ops,
1690 /*
1691 * bits 25:26 selects from 4 possible parents:
1692 * fclk_div4, fclk_div3, fclk_div5, fclk_div7,
1693 */
1694 .parent_hws = gxbb_vapb_parent_hws,
1695 .num_parents = ARRAY_SIZE(gxbb_vapb_parent_hws),
1696 .flags = CLK_SET_RATE_NO_REPARENT,
1697 },
1698 };
1699
1700 static struct clk_regmap gxbb_vapb_1_div = {
1701 .data = &(struct clk_regmap_div_data){
1702 .offset = HHI_VAPBCLK_CNTL,
1703 .shift = 16,
1704 .width = 7,
1705 },
1706 .hw.init = &(struct clk_init_data){
1707 .name = "vapb_1_div",
1708 .ops = &clk_regmap_divider_ops,
1709 .parent_hws = (const struct clk_hw *[]) {
1710 &gxbb_vapb_1_sel.hw
1711 },
1712 .num_parents = 1,
1713 .flags = CLK_SET_RATE_PARENT,
1714 },
1715 };
1716
1717 static struct clk_regmap gxbb_vapb_1 = {
1718 .data = &(struct clk_regmap_gate_data){
1719 .offset = HHI_VAPBCLK_CNTL,
1720 .bit_idx = 24,
1721 },
1722 .hw.init = &(struct clk_init_data) {
1723 .name = "vapb_1",
1724 .ops = &clk_regmap_gate_ops,
1725 .parent_hws = (const struct clk_hw *[]) {
1726 &gxbb_vapb_1_div.hw
1727 },
1728 .num_parents = 1,
1729 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1730 },
1731 };
1732
1733 static struct clk_regmap gxbb_vapb_sel = {
1734 .data = &(struct clk_regmap_mux_data){
1735 .offset = HHI_VAPBCLK_CNTL,
1736 .mask = 1,
1737 .shift = 31,
1738 },
1739 .hw.init = &(struct clk_init_data){
1740 .name = "vapb_sel",
1741 .ops = &clk_regmap_mux_ops,
1742 /*
1743 * bit 31 selects from 2 possible parents:
1744 * vapb_0 or vapb_1
1745 */
1746 .parent_hws = (const struct clk_hw *[]) {
1747 &gxbb_vapb_0.hw,
1748 &gxbb_vapb_1.hw
1749 },
1750 .num_parents = 2,
1751 .flags = CLK_SET_RATE_NO_REPARENT,
1752 },
1753 };
1754
1755 static struct clk_regmap gxbb_vapb = {
1756 .data = &(struct clk_regmap_gate_data){
1757 .offset = HHI_VAPBCLK_CNTL,
1758 .bit_idx = 30,
1759 },
1760 .hw.init = &(struct clk_init_data) {
1761 .name = "vapb",
1762 .ops = &clk_regmap_gate_ops,
1763 .parent_hws = (const struct clk_hw *[]) { &gxbb_vapb_sel.hw },
1764 .num_parents = 1,
1765 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1766 },
1767 };
1768
1769 /* Video Clocks */
1770
1771 static struct clk_regmap gxbb_vid_pll_div = {
1772 .data = &(struct meson_vid_pll_div_data){
1773 .val = {
1774 .reg_off = HHI_VID_PLL_CLK_DIV,
1775 .shift = 0,
1776 .width = 15,
1777 },
1778 .sel = {
1779 .reg_off = HHI_VID_PLL_CLK_DIV,
1780 .shift = 16,
1781 .width = 2,
1782 },
1783 },
1784 .hw.init = &(struct clk_init_data) {
1785 .name = "vid_pll_div",
1786 .ops = &meson_vid_pll_div_ro_ops,
1787 .parent_data = &(const struct clk_parent_data) {
1788 /*
1789 * Note:
1790 * GXL and GXBB have different hdmi_plls (with
1791 * different struct clk_hw). We fallback to the global
1792 * naming string mechanism so vid_pll_div picks up the
1793 * appropriate one.
1794 */
1795 .name = "hdmi_pll",
1796 .index = -1,
1797 },
1798 .num_parents = 1,
1799 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
1800 },
1801 };
1802
1803 static const struct clk_parent_data gxbb_vid_pll_parent_data[] = {
1804 { .hw = &gxbb_vid_pll_div.hw },
1805 /*
1806 * Note:
1807 * GXL and GXBB have different hdmi_plls (with
1808 * different struct clk_hw). We fallback to the global
1809 * naming string mechanism so vid_pll_div picks up the
1810 * appropriate one.
1811 */
1812 { .name = "hdmi_pll", .index = -1 },
1813 };
1814
1815 static struct clk_regmap gxbb_vid_pll_sel = {
1816 .data = &(struct clk_regmap_mux_data){
1817 .offset = HHI_VID_PLL_CLK_DIV,
1818 .mask = 0x1,
1819 .shift = 18,
1820 },
1821 .hw.init = &(struct clk_init_data){
1822 .name = "vid_pll_sel",
1823 .ops = &clk_regmap_mux_ops,
1824 /*
1825 * bit 18 selects from 2 possible parents:
1826 * vid_pll_div or hdmi_pll
1827 */
1828 .parent_data = gxbb_vid_pll_parent_data,
1829 .num_parents = ARRAY_SIZE(gxbb_vid_pll_parent_data),
1830 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1831 },
1832 };
1833
1834 static struct clk_regmap gxbb_vid_pll = {
1835 .data = &(struct clk_regmap_gate_data){
1836 .offset = HHI_VID_PLL_CLK_DIV,
1837 .bit_idx = 19,
1838 },
1839 .hw.init = &(struct clk_init_data) {
1840 .name = "vid_pll",
1841 .ops = &clk_regmap_gate_ops,
1842 .parent_hws = (const struct clk_hw *[]) {
1843 &gxbb_vid_pll_sel.hw
1844 },
1845 .num_parents = 1,
1846 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1847 },
1848 };
1849
1850 static const struct clk_hw *gxbb_vclk_parent_hws[] = {
1851 &gxbb_vid_pll.hw,
1852 &gxbb_fclk_div4.hw,
1853 &gxbb_fclk_div3.hw,
1854 &gxbb_fclk_div5.hw,
1855 &gxbb_vid_pll.hw,
1856 &gxbb_fclk_div7.hw,
1857 &gxbb_mpll1.hw,
1858 };
1859
1860 static struct clk_regmap gxbb_vclk_sel = {
1861 .data = &(struct clk_regmap_mux_data){
1862 .offset = HHI_VID_CLK_CNTL,
1863 .mask = 0x7,
1864 .shift = 16,
1865 },
1866 .hw.init = &(struct clk_init_data){
1867 .name = "vclk_sel",
1868 .ops = &clk_regmap_mux_ops,
1869 /*
1870 * bits 16:18 selects from 8 possible parents:
1871 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1872 * vid_pll, fclk_div7, mp1
1873 */
1874 .parent_hws = gxbb_vclk_parent_hws,
1875 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1876 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1877 },
1878 };
1879
1880 static struct clk_regmap gxbb_vclk2_sel = {
1881 .data = &(struct clk_regmap_mux_data){
1882 .offset = HHI_VIID_CLK_CNTL,
1883 .mask = 0x7,
1884 .shift = 16,
1885 },
1886 .hw.init = &(struct clk_init_data){
1887 .name = "vclk2_sel",
1888 .ops = &clk_regmap_mux_ops,
1889 /*
1890 * bits 16:18 selects from 8 possible parents:
1891 * vid_pll, fclk_div4, fclk_div3, fclk_div5,
1892 * vid_pll, fclk_div7, mp1
1893 */
1894 .parent_hws = gxbb_vclk_parent_hws,
1895 .num_parents = ARRAY_SIZE(gxbb_vclk_parent_hws),
1896 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
1897 },
1898 };
1899
1900 static struct clk_regmap gxbb_vclk_input = {
1901 .data = &(struct clk_regmap_gate_data){
1902 .offset = HHI_VID_CLK_DIV,
1903 .bit_idx = 16,
1904 },
1905 .hw.init = &(struct clk_init_data) {
1906 .name = "vclk_input",
1907 .ops = &clk_regmap_gate_ops,
1908 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_sel.hw },
1909 .num_parents = 1,
1910 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1911 },
1912 };
1913
1914 static struct clk_regmap gxbb_vclk2_input = {
1915 .data = &(struct clk_regmap_gate_data){
1916 .offset = HHI_VIID_CLK_DIV,
1917 .bit_idx = 16,
1918 },
1919 .hw.init = &(struct clk_init_data) {
1920 .name = "vclk2_input",
1921 .ops = &clk_regmap_gate_ops,
1922 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_sel.hw },
1923 .num_parents = 1,
1924 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1925 },
1926 };
1927
1928 static struct clk_regmap gxbb_vclk_div = {
1929 .data = &(struct clk_regmap_div_data){
1930 .offset = HHI_VID_CLK_DIV,
1931 .shift = 0,
1932 .width = 8,
1933 },
1934 .hw.init = &(struct clk_init_data){
1935 .name = "vclk_div",
1936 .ops = &clk_regmap_divider_ops,
1937 .parent_hws = (const struct clk_hw *[]) {
1938 &gxbb_vclk_input.hw
1939 },
1940 .num_parents = 1,
1941 .flags = CLK_GET_RATE_NOCACHE,
1942 },
1943 };
1944
1945 static struct clk_regmap gxbb_vclk2_div = {
1946 .data = &(struct clk_regmap_div_data){
1947 .offset = HHI_VIID_CLK_DIV,
1948 .shift = 0,
1949 .width = 8,
1950 },
1951 .hw.init = &(struct clk_init_data){
1952 .name = "vclk2_div",
1953 .ops = &clk_regmap_divider_ops,
1954 .parent_hws = (const struct clk_hw *[]) {
1955 &gxbb_vclk2_input.hw
1956 },
1957 .num_parents = 1,
1958 .flags = CLK_GET_RATE_NOCACHE,
1959 },
1960 };
1961
1962 static struct clk_regmap gxbb_vclk = {
1963 .data = &(struct clk_regmap_gate_data){
1964 .offset = HHI_VID_CLK_CNTL,
1965 .bit_idx = 19,
1966 },
1967 .hw.init = &(struct clk_init_data) {
1968 .name = "vclk",
1969 .ops = &clk_regmap_gate_ops,
1970 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk_div.hw },
1971 .num_parents = 1,
1972 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1973 },
1974 };
1975
1976 static struct clk_regmap gxbb_vclk2 = {
1977 .data = &(struct clk_regmap_gate_data){
1978 .offset = HHI_VIID_CLK_CNTL,
1979 .bit_idx = 19,
1980 },
1981 .hw.init = &(struct clk_init_data) {
1982 .name = "vclk2",
1983 .ops = &clk_regmap_gate_ops,
1984 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2_div.hw },
1985 .num_parents = 1,
1986 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
1987 },
1988 };
1989
1990 static struct clk_regmap gxbb_vclk_div1 = {
1991 .data = &(struct clk_regmap_gate_data){
1992 .offset = HHI_VID_CLK_CNTL,
1993 .bit_idx = 0,
1994 },
1995 .hw.init = &(struct clk_init_data) {
1996 .name = "vclk_div1",
1997 .ops = &clk_regmap_gate_ops,
1998 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
1999 .num_parents = 1,
2000 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2001 },
2002 };
2003
2004 static struct clk_regmap gxbb_vclk_div2_en = {
2005 .data = &(struct clk_regmap_gate_data){
2006 .offset = HHI_VID_CLK_CNTL,
2007 .bit_idx = 1,
2008 },
2009 .hw.init = &(struct clk_init_data) {
2010 .name = "vclk_div2_en",
2011 .ops = &clk_regmap_gate_ops,
2012 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2013 .num_parents = 1,
2014 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2015 },
2016 };
2017
2018 static struct clk_regmap gxbb_vclk_div4_en = {
2019 .data = &(struct clk_regmap_gate_data){
2020 .offset = HHI_VID_CLK_CNTL,
2021 .bit_idx = 2,
2022 },
2023 .hw.init = &(struct clk_init_data) {
2024 .name = "vclk_div4_en",
2025 .ops = &clk_regmap_gate_ops,
2026 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2027 .num_parents = 1,
2028 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2029 },
2030 };
2031
2032 static struct clk_regmap gxbb_vclk_div6_en = {
2033 .data = &(struct clk_regmap_gate_data){
2034 .offset = HHI_VID_CLK_CNTL,
2035 .bit_idx = 3,
2036 },
2037 .hw.init = &(struct clk_init_data) {
2038 .name = "vclk_div6_en",
2039 .ops = &clk_regmap_gate_ops,
2040 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2041 .num_parents = 1,
2042 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2043 },
2044 };
2045
2046 static struct clk_regmap gxbb_vclk_div12_en = {
2047 .data = &(struct clk_regmap_gate_data){
2048 .offset = HHI_VID_CLK_CNTL,
2049 .bit_idx = 4,
2050 },
2051 .hw.init = &(struct clk_init_data) {
2052 .name = "vclk_div12_en",
2053 .ops = &clk_regmap_gate_ops,
2054 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk.hw },
2055 .num_parents = 1,
2056 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2057 },
2058 };
2059
2060 static struct clk_regmap gxbb_vclk2_div1 = {
2061 .data = &(struct clk_regmap_gate_data){
2062 .offset = HHI_VIID_CLK_CNTL,
2063 .bit_idx = 0,
2064 },
2065 .hw.init = &(struct clk_init_data) {
2066 .name = "vclk2_div1",
2067 .ops = &clk_regmap_gate_ops,
2068 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2069 .num_parents = 1,
2070 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2071 },
2072 };
2073
2074 static struct clk_regmap gxbb_vclk2_div2_en = {
2075 .data = &(struct clk_regmap_gate_data){
2076 .offset = HHI_VIID_CLK_CNTL,
2077 .bit_idx = 1,
2078 },
2079 .hw.init = &(struct clk_init_data) {
2080 .name = "vclk2_div2_en",
2081 .ops = &clk_regmap_gate_ops,
2082 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2083 .num_parents = 1,
2084 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2085 },
2086 };
2087
2088 static struct clk_regmap gxbb_vclk2_div4_en = {
2089 .data = &(struct clk_regmap_gate_data){
2090 .offset = HHI_VIID_CLK_CNTL,
2091 .bit_idx = 2,
2092 },
2093 .hw.init = &(struct clk_init_data) {
2094 .name = "vclk2_div4_en",
2095 .ops = &clk_regmap_gate_ops,
2096 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2097 .num_parents = 1,
2098 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2099 },
2100 };
2101
2102 static struct clk_regmap gxbb_vclk2_div6_en = {
2103 .data = &(struct clk_regmap_gate_data){
2104 .offset = HHI_VIID_CLK_CNTL,
2105 .bit_idx = 3,
2106 },
2107 .hw.init = &(struct clk_init_data) {
2108 .name = "vclk2_div6_en",
2109 .ops = &clk_regmap_gate_ops,
2110 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2111 .num_parents = 1,
2112 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2113 },
2114 };
2115
2116 static struct clk_regmap gxbb_vclk2_div12_en = {
2117 .data = &(struct clk_regmap_gate_data){
2118 .offset = HHI_VIID_CLK_CNTL,
2119 .bit_idx = 4,
2120 },
2121 .hw.init = &(struct clk_init_data) {
2122 .name = "vclk2_div12_en",
2123 .ops = &clk_regmap_gate_ops,
2124 .parent_hws = (const struct clk_hw *[]) { &gxbb_vclk2.hw },
2125 .num_parents = 1,
2126 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2127 },
2128 };
2129
2130 static struct clk_fixed_factor gxbb_vclk_div2 = {
2131 .mult = 1,
2132 .div = 2,
2133 .hw.init = &(struct clk_init_data){
2134 .name = "vclk_div2",
2135 .ops = &clk_fixed_factor_ops,
2136 .parent_hws = (const struct clk_hw *[]) {
2137 &gxbb_vclk_div2_en.hw
2138 },
2139 .num_parents = 1,
2140 },
2141 };
2142
2143 static struct clk_fixed_factor gxbb_vclk_div4 = {
2144 .mult = 1,
2145 .div = 4,
2146 .hw.init = &(struct clk_init_data){
2147 .name = "vclk_div4",
2148 .ops = &clk_fixed_factor_ops,
2149 .parent_hws = (const struct clk_hw *[]) {
2150 &gxbb_vclk_div4_en.hw
2151 },
2152 .num_parents = 1,
2153 },
2154 };
2155
2156 static struct clk_fixed_factor gxbb_vclk_div6 = {
2157 .mult = 1,
2158 .div = 6,
2159 .hw.init = &(struct clk_init_data){
2160 .name = "vclk_div6",
2161 .ops = &clk_fixed_factor_ops,
2162 .parent_hws = (const struct clk_hw *[]) {
2163 &gxbb_vclk_div6_en.hw
2164 },
2165 .num_parents = 1,
2166 },
2167 };
2168
2169 static struct clk_fixed_factor gxbb_vclk_div12 = {
2170 .mult = 1,
2171 .div = 12,
2172 .hw.init = &(struct clk_init_data){
2173 .name = "vclk_div12",
2174 .ops = &clk_fixed_factor_ops,
2175 .parent_hws = (const struct clk_hw *[]) {
2176 &gxbb_vclk_div12_en.hw
2177 },
2178 .num_parents = 1,
2179 },
2180 };
2181
2182 static struct clk_fixed_factor gxbb_vclk2_div2 = {
2183 .mult = 1,
2184 .div = 2,
2185 .hw.init = &(struct clk_init_data){
2186 .name = "vclk2_div2",
2187 .ops = &clk_fixed_factor_ops,
2188 .parent_hws = (const struct clk_hw *[]) {
2189 &gxbb_vclk2_div2_en.hw
2190 },
2191 .num_parents = 1,
2192 },
2193 };
2194
2195 static struct clk_fixed_factor gxbb_vclk2_div4 = {
2196 .mult = 1,
2197 .div = 4,
2198 .hw.init = &(struct clk_init_data){
2199 .name = "vclk2_div4",
2200 .ops = &clk_fixed_factor_ops,
2201 .parent_hws = (const struct clk_hw *[]) {
2202 &gxbb_vclk2_div4_en.hw
2203 },
2204 .num_parents = 1,
2205 },
2206 };
2207
2208 static struct clk_fixed_factor gxbb_vclk2_div6 = {
2209 .mult = 1,
2210 .div = 6,
2211 .hw.init = &(struct clk_init_data){
2212 .name = "vclk2_div6",
2213 .ops = &clk_fixed_factor_ops,
2214 .parent_hws = (const struct clk_hw *[]) {
2215 &gxbb_vclk2_div6_en.hw
2216 },
2217 .num_parents = 1,
2218 },
2219 };
2220
2221 static struct clk_fixed_factor gxbb_vclk2_div12 = {
2222 .mult = 1,
2223 .div = 12,
2224 .hw.init = &(struct clk_init_data){
2225 .name = "vclk2_div12",
2226 .ops = &clk_fixed_factor_ops,
2227 .parent_hws = (const struct clk_hw *[]) {
2228 &gxbb_vclk2_div12_en.hw
2229 },
2230 .num_parents = 1,
2231 },
2232 };
2233
2234 static u32 mux_table_cts_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2235 static const struct clk_hw *gxbb_cts_parent_hws[] = {
2236 &gxbb_vclk_div1.hw,
2237 &gxbb_vclk_div2.hw,
2238 &gxbb_vclk_div4.hw,
2239 &gxbb_vclk_div6.hw,
2240 &gxbb_vclk_div12.hw,
2241 &gxbb_vclk2_div1.hw,
2242 &gxbb_vclk2_div2.hw,
2243 &gxbb_vclk2_div4.hw,
2244 &gxbb_vclk2_div6.hw,
2245 &gxbb_vclk2_div12.hw,
2246 };
2247
2248 static struct clk_regmap gxbb_cts_enci_sel = {
2249 .data = &(struct clk_regmap_mux_data){
2250 .offset = HHI_VID_CLK_DIV,
2251 .mask = 0xf,
2252 .shift = 28,
2253 .table = mux_table_cts_sel,
2254 },
2255 .hw.init = &(struct clk_init_data){
2256 .name = "cts_enci_sel",
2257 .ops = &clk_regmap_mux_ops,
2258 .parent_hws = gxbb_cts_parent_hws,
2259 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2260 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2261 },
2262 };
2263
2264 static struct clk_regmap gxbb_cts_encp_sel = {
2265 .data = &(struct clk_regmap_mux_data){
2266 .offset = HHI_VID_CLK_DIV,
2267 .mask = 0xf,
2268 .shift = 20,
2269 .table = mux_table_cts_sel,
2270 },
2271 .hw.init = &(struct clk_init_data){
2272 .name = "cts_encp_sel",
2273 .ops = &clk_regmap_mux_ops,
2274 .parent_hws = gxbb_cts_parent_hws,
2275 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2276 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2277 },
2278 };
2279
2280 static struct clk_regmap gxbb_cts_vdac_sel = {
2281 .data = &(struct clk_regmap_mux_data){
2282 .offset = HHI_VIID_CLK_DIV,
2283 .mask = 0xf,
2284 .shift = 28,
2285 .table = mux_table_cts_sel,
2286 },
2287 .hw.init = &(struct clk_init_data){
2288 .name = "cts_vdac_sel",
2289 .ops = &clk_regmap_mux_ops,
2290 .parent_hws = gxbb_cts_parent_hws,
2291 .num_parents = ARRAY_SIZE(gxbb_cts_parent_hws),
2292 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2293 },
2294 };
2295
2296 /* TOFIX: add support for cts_tcon */
2297 static u32 mux_table_hdmi_tx_sel[] = { 0, 1, 2, 3, 4, 8, 9, 10, 11, 12 };
2298 static const struct clk_hw *gxbb_cts_hdmi_tx_parent_hws[] = {
2299 &gxbb_vclk_div1.hw,
2300 &gxbb_vclk_div2.hw,
2301 &gxbb_vclk_div4.hw,
2302 &gxbb_vclk_div6.hw,
2303 &gxbb_vclk_div12.hw,
2304 &gxbb_vclk2_div1.hw,
2305 &gxbb_vclk2_div2.hw,
2306 &gxbb_vclk2_div4.hw,
2307 &gxbb_vclk2_div6.hw,
2308 &gxbb_vclk2_div12.hw,
2309 };
2310
2311 static struct clk_regmap gxbb_hdmi_tx_sel = {
2312 .data = &(struct clk_regmap_mux_data){
2313 .offset = HHI_HDMI_CLK_CNTL,
2314 .mask = 0xf,
2315 .shift = 16,
2316 .table = mux_table_hdmi_tx_sel,
2317 },
2318 .hw.init = &(struct clk_init_data){
2319 .name = "hdmi_tx_sel",
2320 .ops = &clk_regmap_mux_ops,
2321 /*
2322 * bits 31:28 selects from 12 possible parents:
2323 * vclk_div1, vclk_div2, vclk_div4, vclk_div6, vclk_div12
2324 * vclk2_div1, vclk2_div2, vclk2_div4, vclk2_div6, vclk2_div12,
2325 * cts_tcon
2326 */
2327 .parent_hws = gxbb_cts_hdmi_tx_parent_hws,
2328 .num_parents = ARRAY_SIZE(gxbb_cts_hdmi_tx_parent_hws),
2329 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2330 },
2331 };
2332
2333 static struct clk_regmap gxbb_cts_enci = {
2334 .data = &(struct clk_regmap_gate_data){
2335 .offset = HHI_VID_CLK_CNTL2,
2336 .bit_idx = 0,
2337 },
2338 .hw.init = &(struct clk_init_data) {
2339 .name = "cts_enci",
2340 .ops = &clk_regmap_gate_ops,
2341 .parent_hws = (const struct clk_hw *[]) {
2342 &gxbb_cts_enci_sel.hw
2343 },
2344 .num_parents = 1,
2345 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2346 },
2347 };
2348
2349 static struct clk_regmap gxbb_cts_encp = {
2350 .data = &(struct clk_regmap_gate_data){
2351 .offset = HHI_VID_CLK_CNTL2,
2352 .bit_idx = 2,
2353 },
2354 .hw.init = &(struct clk_init_data) {
2355 .name = "cts_encp",
2356 .ops = &clk_regmap_gate_ops,
2357 .parent_hws = (const struct clk_hw *[]) {
2358 &gxbb_cts_encp_sel.hw
2359 },
2360 .num_parents = 1,
2361 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2362 },
2363 };
2364
2365 static struct clk_regmap gxbb_cts_vdac = {
2366 .data = &(struct clk_regmap_gate_data){
2367 .offset = HHI_VID_CLK_CNTL2,
2368 .bit_idx = 4,
2369 },
2370 .hw.init = &(struct clk_init_data) {
2371 .name = "cts_vdac",
2372 .ops = &clk_regmap_gate_ops,
2373 .parent_hws = (const struct clk_hw *[]) {
2374 &gxbb_cts_vdac_sel.hw
2375 },
2376 .num_parents = 1,
2377 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2378 },
2379 };
2380
2381 static struct clk_regmap gxbb_hdmi_tx = {
2382 .data = &(struct clk_regmap_gate_data){
2383 .offset = HHI_VID_CLK_CNTL2,
2384 .bit_idx = 5,
2385 },
2386 .hw.init = &(struct clk_init_data) {
2387 .name = "hdmi_tx",
2388 .ops = &clk_regmap_gate_ops,
2389 .parent_hws = (const struct clk_hw *[]) {
2390 &gxbb_hdmi_tx_sel.hw
2391 },
2392 .num_parents = 1,
2393 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2394 },
2395 };
2396
2397 /* HDMI Clocks */
2398
2399 static const struct clk_parent_data gxbb_hdmi_parent_data[] = {
2400 { .fw_name = "xtal", },
2401 { .hw = &gxbb_fclk_div4.hw },
2402 { .hw = &gxbb_fclk_div3.hw },
2403 { .hw = &gxbb_fclk_div5.hw },
2404 };
2405
2406 static struct clk_regmap gxbb_hdmi_sel = {
2407 .data = &(struct clk_regmap_mux_data){
2408 .offset = HHI_HDMI_CLK_CNTL,
2409 .mask = 0x3,
2410 .shift = 9,
2411 .flags = CLK_MUX_ROUND_CLOSEST,
2412 },
2413 .hw.init = &(struct clk_init_data){
2414 .name = "hdmi_sel",
2415 .ops = &clk_regmap_mux_ops,
2416 .parent_data = gxbb_hdmi_parent_data,
2417 .num_parents = ARRAY_SIZE(gxbb_hdmi_parent_data),
2418 .flags = CLK_SET_RATE_NO_REPARENT | CLK_GET_RATE_NOCACHE,
2419 },
2420 };
2421
2422 static struct clk_regmap gxbb_hdmi_div = {
2423 .data = &(struct clk_regmap_div_data){
2424 .offset = HHI_HDMI_CLK_CNTL,
2425 .shift = 0,
2426 .width = 7,
2427 },
2428 .hw.init = &(struct clk_init_data){
2429 .name = "hdmi_div",
2430 .ops = &clk_regmap_divider_ops,
2431 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_sel.hw },
2432 .num_parents = 1,
2433 .flags = CLK_GET_RATE_NOCACHE,
2434 },
2435 };
2436
2437 static struct clk_regmap gxbb_hdmi = {
2438 .data = &(struct clk_regmap_gate_data){
2439 .offset = HHI_HDMI_CLK_CNTL,
2440 .bit_idx = 8,
2441 },
2442 .hw.init = &(struct clk_init_data) {
2443 .name = "hdmi",
2444 .ops = &clk_regmap_gate_ops,
2445 .parent_hws = (const struct clk_hw *[]) { &gxbb_hdmi_div.hw },
2446 .num_parents = 1,
2447 .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
2448 },
2449 };
2450
2451 /* VDEC clocks */
2452
2453 static const struct clk_hw *gxbb_vdec_parent_hws[] = {
2454 &gxbb_fclk_div4.hw,
2455 &gxbb_fclk_div3.hw,
2456 &gxbb_fclk_div5.hw,
2457 &gxbb_fclk_div7.hw,
2458 };
2459
2460 static struct clk_regmap gxbb_vdec_1_sel = {
2461 .data = &(struct clk_regmap_mux_data){
2462 .offset = HHI_VDEC_CLK_CNTL,
2463 .mask = 0x3,
2464 .shift = 9,
2465 .flags = CLK_MUX_ROUND_CLOSEST,
2466 },
2467 .hw.init = &(struct clk_init_data){
2468 .name = "vdec_1_sel",
2469 .ops = &clk_regmap_mux_ops,
2470 .parent_hws = gxbb_vdec_parent_hws,
2471 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2472 .flags = CLK_SET_RATE_PARENT,
2473 },
2474 };
2475
2476 static struct clk_regmap gxbb_vdec_1_div = {
2477 .data = &(struct clk_regmap_div_data){
2478 .offset = HHI_VDEC_CLK_CNTL,
2479 .shift = 0,
2480 .width = 7,
2481 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2482 },
2483 .hw.init = &(struct clk_init_data){
2484 .name = "vdec_1_div",
2485 .ops = &clk_regmap_divider_ops,
2486 .parent_hws = (const struct clk_hw *[]) {
2487 &gxbb_vdec_1_sel.hw
2488 },
2489 .num_parents = 1,
2490 .flags = CLK_SET_RATE_PARENT,
2491 },
2492 };
2493
2494 static struct clk_regmap gxbb_vdec_1 = {
2495 .data = &(struct clk_regmap_gate_data){
2496 .offset = HHI_VDEC_CLK_CNTL,
2497 .bit_idx = 8,
2498 },
2499 .hw.init = &(struct clk_init_data) {
2500 .name = "vdec_1",
2501 .ops = &clk_regmap_gate_ops,
2502 .parent_hws = (const struct clk_hw *[]) {
2503 &gxbb_vdec_1_div.hw
2504 },
2505 .num_parents = 1,
2506 .flags = CLK_SET_RATE_PARENT,
2507 },
2508 };
2509
2510 static struct clk_regmap gxbb_vdec_hevc_sel = {
2511 .data = &(struct clk_regmap_mux_data){
2512 .offset = HHI_VDEC2_CLK_CNTL,
2513 .mask = 0x3,
2514 .shift = 25,
2515 .flags = CLK_MUX_ROUND_CLOSEST,
2516 },
2517 .hw.init = &(struct clk_init_data){
2518 .name = "vdec_hevc_sel",
2519 .ops = &clk_regmap_mux_ops,
2520 .parent_hws = gxbb_vdec_parent_hws,
2521 .num_parents = ARRAY_SIZE(gxbb_vdec_parent_hws),
2522 .flags = CLK_SET_RATE_PARENT,
2523 },
2524 };
2525
2526 static struct clk_regmap gxbb_vdec_hevc_div = {
2527 .data = &(struct clk_regmap_div_data){
2528 .offset = HHI_VDEC2_CLK_CNTL,
2529 .shift = 16,
2530 .width = 7,
2531 .flags = CLK_DIVIDER_ROUND_CLOSEST,
2532 },
2533 .hw.init = &(struct clk_init_data){
2534 .name = "vdec_hevc_div",
2535 .ops = &clk_regmap_divider_ops,
2536 .parent_hws = (const struct clk_hw *[]) {
2537 &gxbb_vdec_hevc_sel.hw
2538 },
2539 .num_parents = 1,
2540 .flags = CLK_SET_RATE_PARENT,
2541 },
2542 };
2543
2544 static struct clk_regmap gxbb_vdec_hevc = {
2545 .data = &(struct clk_regmap_gate_data){
2546 .offset = HHI_VDEC2_CLK_CNTL,
2547 .bit_idx = 24,
2548 },
2549 .hw.init = &(struct clk_init_data) {
2550 .name = "vdec_hevc",
2551 .ops = &clk_regmap_gate_ops,
2552 .parent_hws = (const struct clk_hw *[]) {
2553 &gxbb_vdec_hevc_div.hw
2554 },
2555 .num_parents = 1,
2556 .flags = CLK_SET_RATE_PARENT,
2557 },
2558 };
2559
2560 static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
2561 9, 10, 11, 13, 14, };
2562 static const struct clk_parent_data gen_clk_parent_data[] = {
2563 { .fw_name = "xtal", },
2564 { .hw = &gxbb_vdec_1.hw },
2565 { .hw = &gxbb_vdec_hevc.hw },
2566 { .hw = &gxbb_mpll0.hw },
2567 { .hw = &gxbb_mpll1.hw },
2568 { .hw = &gxbb_mpll2.hw },
2569 { .hw = &gxbb_fclk_div4.hw },
2570 { .hw = &gxbb_fclk_div3.hw },
2571 { .hw = &gxbb_fclk_div5.hw },
2572 { .hw = &gxbb_fclk_div7.hw },
2573 { .hw = &gxbb_gp0_pll.hw },
2574 };
2575
2576 static struct clk_regmap gxbb_gen_clk_sel = {
2577 .data = &(struct clk_regmap_mux_data){
2578 .offset = HHI_GEN_CLK_CNTL,
2579 .mask = 0xf,
2580 .shift = 12,
2581 .table = mux_table_gen_clk,
2582 },
2583 .hw.init = &(struct clk_init_data){
2584 .name = "gen_clk_sel",
2585 .ops = &clk_regmap_mux_ops,
2586 /*
2587 * bits 15:12 selects from 14 possible parents:
2588 * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
2589 * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
2590 * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
2591 */
2592 .parent_data = gen_clk_parent_data,
2593 .num_parents = ARRAY_SIZE(gen_clk_parent_data),
2594 },
2595 };
2596
2597 static struct clk_regmap gxbb_gen_clk_div = {
2598 .data = &(struct clk_regmap_div_data){
2599 .offset = HHI_GEN_CLK_CNTL,
2600 .shift = 0,
2601 .width = 11,
2602 },
2603 .hw.init = &(struct clk_init_data){
2604 .name = "gen_clk_div",
2605 .ops = &clk_regmap_divider_ops,
2606 .parent_hws = (const struct clk_hw *[]) {
2607 &gxbb_gen_clk_sel.hw
2608 },
2609 .num_parents = 1,
2610 .flags = CLK_SET_RATE_PARENT,
2611 },
2612 };
2613
2614 static struct clk_regmap gxbb_gen_clk = {
2615 .data = &(struct clk_regmap_gate_data){
2616 .offset = HHI_GEN_CLK_CNTL,
2617 .bit_idx = 7,
2618 },
2619 .hw.init = &(struct clk_init_data){
2620 .name = "gen_clk",
2621 .ops = &clk_regmap_gate_ops,
2622 .parent_hws = (const struct clk_hw *[]) {
2623 &gxbb_gen_clk_div.hw
2624 },
2625 .num_parents = 1,
2626 .flags = CLK_SET_RATE_PARENT,
2627 },
2628 };
2629
2630 #define MESON_GATE(_name, _reg, _bit) \
2631 MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw)
2632
2633 /* Everything Else (EE) domain gates */
2634 static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
2635 static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
2636 static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
2637 static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
2638 static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
2639 static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
2640 static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
2641 static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10);
2642 static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
2643 static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
2644 static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
2645 static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
2646 static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
2647 static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
2648 static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
2649 static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
2650 static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
2651 static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
2652 static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
2653 static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
2654 static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
2655 static MESON_GATE(gxl_acodec, HHI_GCLK_MPEG0, 28);
2656 static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);
2657
2658 static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
2659 static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
2660 static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
2661 static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
2662 static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
2663 static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
2664 static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
2665 static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
2666 static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
2667 static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
2668 static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
2669 static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
2670 static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
2671 static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
2672 static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
2673 static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
2674 static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);
2675
2676 static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
2677 static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
2678 static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
2679 static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
2680 static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
2681 static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
2682 static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
2683 static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
2684 static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
2685 static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22);
2686 static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
2687 static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
2688 static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
2689
2690 static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
2691 static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
2692 static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
2693 static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
2694 static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
2695 static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
2696 static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
2697 static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
2698 static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
2699 static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
2700 static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
2701 static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
2702 static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
2703 static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
2704 static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
2705 static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);
2706
2707 /* Always On (AO) domain gates */
2708
2709 static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
2710 static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
2711 static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
2712 static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
2713 static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);
2714
2715 /* AIU gates */
2716 static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw);
2717 static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw);
2718 static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw);
2719 static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw);
2720 static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw);
2721 static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw);
2722 static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw);
2723 static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw);
2724
2725 /* Array of all clocks provided by this provider */
2726
2727 static struct clk_hw *gxbb_hw_clks[] = {
2728 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
2729 [CLKID_HDMI_PLL] = &gxbb_hdmi_pll.hw,
2730 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
2731 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
2732 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
2733 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
2734 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2735 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
2736 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
2737 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
2738 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
2739 [CLKID_CLK81] = &gxbb_clk81.hw,
2740 [CLKID_MPLL0] = &gxbb_mpll0.hw,
2741 [CLKID_MPLL1] = &gxbb_mpll1.hw,
2742 [CLKID_MPLL2] = &gxbb_mpll2.hw,
2743 [CLKID_DDR] = &gxbb_ddr.hw,
2744 [CLKID_DOS] = &gxbb_dos.hw,
2745 [CLKID_ISA] = &gxbb_isa.hw,
2746 [CLKID_PL301] = &gxbb_pl301.hw,
2747 [CLKID_PERIPHS] = &gxbb_periphs.hw,
2748 [CLKID_SPICC] = &gxbb_spicc.hw,
2749 [CLKID_I2C] = &gxbb_i2c.hw,
2750 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
2751 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
2752 [CLKID_RNG0] = &gxbb_rng0.hw,
2753 [CLKID_UART0] = &gxbb_uart0.hw,
2754 [CLKID_SDHC] = &gxbb_sdhc.hw,
2755 [CLKID_STREAM] = &gxbb_stream.hw,
2756 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
2757 [CLKID_SDIO] = &gxbb_sdio.hw,
2758 [CLKID_ABUF] = &gxbb_abuf.hw,
2759 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
2760 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
2761 [CLKID_SPI] = &gxbb_spi.hw,
2762 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
2763 [CLKID_ETH] = &gxbb_eth.hw,
2764 [CLKID_DEMUX] = &gxbb_demux.hw,
2765 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
2766 [CLKID_IEC958] = &gxbb_iec958.hw,
2767 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
2768 [CLKID_AMCLK] = &gxbb_amclk.hw,
2769 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
2770 [CLKID_MIXER] = &gxbb_mixer.hw,
2771 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
2772 [CLKID_ADC] = &gxbb_adc.hw,
2773 [CLKID_BLKMV] = &gxbb_blkmv.hw,
2774 [CLKID_AIU] = &gxbb_aiu.hw,
2775 [CLKID_UART1] = &gxbb_uart1.hw,
2776 [CLKID_G2D] = &gxbb_g2d.hw,
2777 [CLKID_USB0] = &gxbb_usb0.hw,
2778 [CLKID_USB1] = &gxbb_usb1.hw,
2779 [CLKID_RESET] = &gxbb_reset.hw,
2780 [CLKID_NAND] = &gxbb_nand.hw,
2781 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
2782 [CLKID_USB] = &gxbb_usb.hw,
2783 [CLKID_VDIN1] = &gxbb_vdin1.hw,
2784 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
2785 [CLKID_EFUSE] = &gxbb_efuse.hw,
2786 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
2787 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
2788 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
2789 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
2790 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
2791 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
2792 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
2793 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
2794 [CLKID_DVIN] = &gxbb_dvin.hw,
2795 [CLKID_UART2] = &gxbb_uart2.hw,
2796 [CLKID_SANA] = &gxbb_sana.hw,
2797 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
2798 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
2799 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
2800 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
2801 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
2802 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
2803 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
2804 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
2805 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
2806 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
2807 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
2808 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
2809 [CLKID_ENC480P] = &gxbb_enc480p.hw,
2810 [CLKID_RNG1] = &gxbb_rng1.hw,
2811 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
2812 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
2813 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
2814 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
2815 [CLKID_EDP] = &gxbb_edp.hw,
2816 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
2817 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
2818 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
2819 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
2820 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
2821 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
2822 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
2823 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
2824 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
2825 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
2826 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
2827 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
2828 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
2829 [CLKID_MALI_0] = &gxbb_mali_0.hw,
2830 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
2831 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
2832 [CLKID_MALI_1] = &gxbb_mali_1.hw,
2833 [CLKID_MALI] = &gxbb_mali.hw,
2834 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
2835 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
2836 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
2837 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
2838 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
2839 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
2840 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
2841 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
2842 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
2843 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
2844 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
2845 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
2846 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
2847 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
2848 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
2849 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
2850 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
2851 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
2852 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
2853 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
2854 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
2855 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
2856 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
2857 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
2858 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
2859 [CLKID_VPU] = &gxbb_vpu.hw,
2860 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
2861 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
2862 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
2863 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
2864 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
2865 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
2866 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
2867 [CLKID_VAPB] = &gxbb_vapb.hw,
2868 [CLKID_HDMI_PLL_PRE_MULT] = &gxbb_hdmi_pll_pre_mult.hw,
2869 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
2870 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
2871 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
2872 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
2873 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
2874 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
2875 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
2876 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
2877 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
2878 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
2879 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
2880 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
2881 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
2882 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
2883 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
2884 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
2885 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
2886 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
2887 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
2888 [CLKID_HDMI_PLL_DCO] = &gxbb_hdmi_pll_dco.hw,
2889 [CLKID_HDMI_PLL_OD] = &gxbb_hdmi_pll_od.hw,
2890 [CLKID_HDMI_PLL_OD2] = &gxbb_hdmi_pll_od2.hw,
2891 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
2892 [CLKID_GP0_PLL_DCO] = &gxbb_gp0_pll_dco.hw,
2893 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
2894 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
2895 [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
2896 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
2897 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
2898 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
2899 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
2900 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
2901 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
2902 [CLKID_VCLK] = &gxbb_vclk.hw,
2903 [CLKID_VCLK2] = &gxbb_vclk2.hw,
2904 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
2905 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
2906 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
2907 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
2908 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
2909 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
2910 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
2911 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
2912 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
2913 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
2914 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
2915 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
2916 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
2917 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
2918 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
2919 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
2920 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
2921 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
2922 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
2923 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
2924 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
2925 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
2926 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
2927 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
2928 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
2929 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
2930 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
2931 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
2932 [CLKID_HDMI] = &gxbb_hdmi.hw,
2933 };
2934
2935 static struct clk_hw *gxl_hw_clks[] = {
2936 [CLKID_SYS_PLL] = &gxbb_sys_pll.hw,
2937 [CLKID_HDMI_PLL] = &gxl_hdmi_pll.hw,
2938 [CLKID_FIXED_PLL] = &gxbb_fixed_pll.hw,
2939 [CLKID_FCLK_DIV2] = &gxbb_fclk_div2.hw,
2940 [CLKID_FCLK_DIV3] = &gxbb_fclk_div3.hw,
2941 [CLKID_FCLK_DIV4] = &gxbb_fclk_div4.hw,
2942 [CLKID_FCLK_DIV5] = &gxbb_fclk_div5.hw,
2943 [CLKID_FCLK_DIV7] = &gxbb_fclk_div7.hw,
2944 [CLKID_GP0_PLL] = &gxbb_gp0_pll.hw,
2945 [CLKID_MPEG_SEL] = &gxbb_mpeg_clk_sel.hw,
2946 [CLKID_MPEG_DIV] = &gxbb_mpeg_clk_div.hw,
2947 [CLKID_CLK81] = &gxbb_clk81.hw,
2948 [CLKID_MPLL0] = &gxbb_mpll0.hw,
2949 [CLKID_MPLL1] = &gxbb_mpll1.hw,
2950 [CLKID_MPLL2] = &gxbb_mpll2.hw,
2951 [CLKID_DDR] = &gxbb_ddr.hw,
2952 [CLKID_DOS] = &gxbb_dos.hw,
2953 [CLKID_ISA] = &gxbb_isa.hw,
2954 [CLKID_PL301] = &gxbb_pl301.hw,
2955 [CLKID_PERIPHS] = &gxbb_periphs.hw,
2956 [CLKID_SPICC] = &gxbb_spicc.hw,
2957 [CLKID_I2C] = &gxbb_i2c.hw,
2958 [CLKID_SAR_ADC] = &gxbb_sar_adc.hw,
2959 [CLKID_SMART_CARD] = &gxbb_smart_card.hw,
2960 [CLKID_RNG0] = &gxbb_rng0.hw,
2961 [CLKID_UART0] = &gxbb_uart0.hw,
2962 [CLKID_SDHC] = &gxbb_sdhc.hw,
2963 [CLKID_STREAM] = &gxbb_stream.hw,
2964 [CLKID_ASYNC_FIFO] = &gxbb_async_fifo.hw,
2965 [CLKID_SDIO] = &gxbb_sdio.hw,
2966 [CLKID_ABUF] = &gxbb_abuf.hw,
2967 [CLKID_HIU_IFACE] = &gxbb_hiu_iface.hw,
2968 [CLKID_ASSIST_MISC] = &gxbb_assist_misc.hw,
2969 [CLKID_SPI] = &gxbb_spi.hw,
2970 [CLKID_I2S_SPDIF] = &gxbb_i2s_spdif.hw,
2971 [CLKID_ETH] = &gxbb_eth.hw,
2972 [CLKID_DEMUX] = &gxbb_demux.hw,
2973 [CLKID_AIU_GLUE] = &gxbb_aiu_glue.hw,
2974 [CLKID_IEC958] = &gxbb_iec958.hw,
2975 [CLKID_I2S_OUT] = &gxbb_i2s_out.hw,
2976 [CLKID_AMCLK] = &gxbb_amclk.hw,
2977 [CLKID_AIFIFO2] = &gxbb_aififo2.hw,
2978 [CLKID_MIXER] = &gxbb_mixer.hw,
2979 [CLKID_MIXER_IFACE] = &gxbb_mixer_iface.hw,
2980 [CLKID_ADC] = &gxbb_adc.hw,
2981 [CLKID_BLKMV] = &gxbb_blkmv.hw,
2982 [CLKID_AIU] = &gxbb_aiu.hw,
2983 [CLKID_UART1] = &gxbb_uart1.hw,
2984 [CLKID_G2D] = &gxbb_g2d.hw,
2985 [CLKID_USB0] = &gxbb_usb0.hw,
2986 [CLKID_USB1] = &gxbb_usb1.hw,
2987 [CLKID_RESET] = &gxbb_reset.hw,
2988 [CLKID_NAND] = &gxbb_nand.hw,
2989 [CLKID_DOS_PARSER] = &gxbb_dos_parser.hw,
2990 [CLKID_USB] = &gxbb_usb.hw,
2991 [CLKID_VDIN1] = &gxbb_vdin1.hw,
2992 [CLKID_AHB_ARB0] = &gxbb_ahb_arb0.hw,
2993 [CLKID_EFUSE] = &gxbb_efuse.hw,
2994 [CLKID_BOOT_ROM] = &gxbb_boot_rom.hw,
2995 [CLKID_AHB_DATA_BUS] = &gxbb_ahb_data_bus.hw,
2996 [CLKID_AHB_CTRL_BUS] = &gxbb_ahb_ctrl_bus.hw,
2997 [CLKID_HDMI_INTR_SYNC] = &gxbb_hdmi_intr_sync.hw,
2998 [CLKID_HDMI_PCLK] = &gxbb_hdmi_pclk.hw,
2999 [CLKID_USB1_DDR_BRIDGE] = &gxbb_usb1_ddr_bridge.hw,
3000 [CLKID_USB0_DDR_BRIDGE] = &gxbb_usb0_ddr_bridge.hw,
3001 [CLKID_MMC_PCLK] = &gxbb_mmc_pclk.hw,
3002 [CLKID_DVIN] = &gxbb_dvin.hw,
3003 [CLKID_UART2] = &gxbb_uart2.hw,
3004 [CLKID_SANA] = &gxbb_sana.hw,
3005 [CLKID_VPU_INTR] = &gxbb_vpu_intr.hw,
3006 [CLKID_SEC_AHB_AHB3_BRIDGE] = &gxbb_sec_ahb_ahb3_bridge.hw,
3007 [CLKID_CLK81_A53] = &gxbb_clk81_a53.hw,
3008 [CLKID_VCLK2_VENCI0] = &gxbb_vclk2_venci0.hw,
3009 [CLKID_VCLK2_VENCI1] = &gxbb_vclk2_venci1.hw,
3010 [CLKID_VCLK2_VENCP0] = &gxbb_vclk2_vencp0.hw,
3011 [CLKID_VCLK2_VENCP1] = &gxbb_vclk2_vencp1.hw,
3012 [CLKID_GCLK_VENCI_INT0] = &gxbb_gclk_venci_int0.hw,
3013 [CLKID_GCLK_VENCI_INT] = &gxbb_gclk_vencp_int.hw,
3014 [CLKID_DAC_CLK] = &gxbb_dac_clk.hw,
3015 [CLKID_AOCLK_GATE] = &gxbb_aoclk_gate.hw,
3016 [CLKID_IEC958_GATE] = &gxbb_iec958_gate.hw,
3017 [CLKID_ENC480P] = &gxbb_enc480p.hw,
3018 [CLKID_RNG1] = &gxbb_rng1.hw,
3019 [CLKID_GCLK_VENCI_INT1] = &gxbb_gclk_venci_int1.hw,
3020 [CLKID_VCLK2_VENCLMCC] = &gxbb_vclk2_venclmcc.hw,
3021 [CLKID_VCLK2_VENCL] = &gxbb_vclk2_vencl.hw,
3022 [CLKID_VCLK_OTHER] = &gxbb_vclk_other.hw,
3023 [CLKID_EDP] = &gxbb_edp.hw,
3024 [CLKID_AO_MEDIA_CPU] = &gxbb_ao_media_cpu.hw,
3025 [CLKID_AO_AHB_SRAM] = &gxbb_ao_ahb_sram.hw,
3026 [CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
3027 [CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
3028 [CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
3029 [CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
3030 [CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
3031 [CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
3032 [CLKID_SAR_ADC_CLK] = &gxbb_sar_adc_clk.hw,
3033 [CLKID_SAR_ADC_SEL] = &gxbb_sar_adc_clk_sel.hw,
3034 [CLKID_SAR_ADC_DIV] = &gxbb_sar_adc_clk_div.hw,
3035 [CLKID_MALI_0_SEL] = &gxbb_mali_0_sel.hw,
3036 [CLKID_MALI_0_DIV] = &gxbb_mali_0_div.hw,
3037 [CLKID_MALI_0] = &gxbb_mali_0.hw,
3038 [CLKID_MALI_1_SEL] = &gxbb_mali_1_sel.hw,
3039 [CLKID_MALI_1_DIV] = &gxbb_mali_1_div.hw,
3040 [CLKID_MALI_1] = &gxbb_mali_1.hw,
3041 [CLKID_MALI] = &gxbb_mali.hw,
3042 [CLKID_CTS_AMCLK] = &gxbb_cts_amclk.hw,
3043 [CLKID_CTS_AMCLK_SEL] = &gxbb_cts_amclk_sel.hw,
3044 [CLKID_CTS_AMCLK_DIV] = &gxbb_cts_amclk_div.hw,
3045 [CLKID_CTS_MCLK_I958] = &gxbb_cts_mclk_i958.hw,
3046 [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
3047 [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
3048 [CLKID_CTS_I958] = &gxbb_cts_i958.hw,
3049 [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
3050 [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
3051 [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
3052 [CLKID_SD_EMMC_A_CLK0_SEL] = &gxbb_sd_emmc_a_clk0_sel.hw,
3053 [CLKID_SD_EMMC_A_CLK0_DIV] = &gxbb_sd_emmc_a_clk0_div.hw,
3054 [CLKID_SD_EMMC_A_CLK0] = &gxbb_sd_emmc_a_clk0.hw,
3055 [CLKID_SD_EMMC_B_CLK0_SEL] = &gxbb_sd_emmc_b_clk0_sel.hw,
3056 [CLKID_SD_EMMC_B_CLK0_DIV] = &gxbb_sd_emmc_b_clk0_div.hw,
3057 [CLKID_SD_EMMC_B_CLK0] = &gxbb_sd_emmc_b_clk0.hw,
3058 [CLKID_SD_EMMC_C_CLK0_SEL] = &gxbb_sd_emmc_c_clk0_sel.hw,
3059 [CLKID_SD_EMMC_C_CLK0_DIV] = &gxbb_sd_emmc_c_clk0_div.hw,
3060 [CLKID_SD_EMMC_C_CLK0] = &gxbb_sd_emmc_c_clk0.hw,
3061 [CLKID_VPU_0_SEL] = &gxbb_vpu_0_sel.hw,
3062 [CLKID_VPU_0_DIV] = &gxbb_vpu_0_div.hw,
3063 [CLKID_VPU_0] = &gxbb_vpu_0.hw,
3064 [CLKID_VPU_1_SEL] = &gxbb_vpu_1_sel.hw,
3065 [CLKID_VPU_1_DIV] = &gxbb_vpu_1_div.hw,
3066 [CLKID_VPU_1] = &gxbb_vpu_1.hw,
3067 [CLKID_VPU] = &gxbb_vpu.hw,
3068 [CLKID_VAPB_0_SEL] = &gxbb_vapb_0_sel.hw,
3069 [CLKID_VAPB_0_DIV] = &gxbb_vapb_0_div.hw,
3070 [CLKID_VAPB_0] = &gxbb_vapb_0.hw,
3071 [CLKID_VAPB_1_SEL] = &gxbb_vapb_1_sel.hw,
3072 [CLKID_VAPB_1_DIV] = &gxbb_vapb_1_div.hw,
3073 [CLKID_VAPB_1] = &gxbb_vapb_1.hw,
3074 [CLKID_VAPB_SEL] = &gxbb_vapb_sel.hw,
3075 [CLKID_VAPB] = &gxbb_vapb.hw,
3076 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
3077 [CLKID_MPLL1_DIV] = &gxbb_mpll1_div.hw,
3078 [CLKID_MPLL2_DIV] = &gxbb_mpll2_div.hw,
3079 [CLKID_MPLL_PREDIV] = &gxbb_mpll_prediv.hw,
3080 [CLKID_FCLK_DIV2_DIV] = &gxbb_fclk_div2_div.hw,
3081 [CLKID_FCLK_DIV3_DIV] = &gxbb_fclk_div3_div.hw,
3082 [CLKID_FCLK_DIV4_DIV] = &gxbb_fclk_div4_div.hw,
3083 [CLKID_FCLK_DIV5_DIV] = &gxbb_fclk_div5_div.hw,
3084 [CLKID_FCLK_DIV7_DIV] = &gxbb_fclk_div7_div.hw,
3085 [CLKID_VDEC_1_SEL] = &gxbb_vdec_1_sel.hw,
3086 [CLKID_VDEC_1_DIV] = &gxbb_vdec_1_div.hw,
3087 [CLKID_VDEC_1] = &gxbb_vdec_1.hw,
3088 [CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
3089 [CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
3090 [CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
3091 [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
3092 [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
3093 [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
3094 [CLKID_FIXED_PLL_DCO] = &gxbb_fixed_pll_dco.hw,
3095 [CLKID_HDMI_PLL_DCO] = &gxl_hdmi_pll_dco.hw,
3096 [CLKID_HDMI_PLL_OD] = &gxl_hdmi_pll_od.hw,
3097 [CLKID_HDMI_PLL_OD2] = &gxl_hdmi_pll_od2.hw,
3098 [CLKID_SYS_PLL_DCO] = &gxbb_sys_pll_dco.hw,
3099 [CLKID_GP0_PLL_DCO] = &gxl_gp0_pll_dco.hw,
3100 [CLKID_VID_PLL_DIV] = &gxbb_vid_pll_div.hw,
3101 [CLKID_VID_PLL_SEL] = &gxbb_vid_pll_sel.hw,
3102 [CLKID_VID_PLL] = &gxbb_vid_pll.hw,
3103 [CLKID_VCLK_SEL] = &gxbb_vclk_sel.hw,
3104 [CLKID_VCLK2_SEL] = &gxbb_vclk2_sel.hw,
3105 [CLKID_VCLK_INPUT] = &gxbb_vclk_input.hw,
3106 [CLKID_VCLK2_INPUT] = &gxbb_vclk2_input.hw,
3107 [CLKID_VCLK_DIV] = &gxbb_vclk_div.hw,
3108 [CLKID_VCLK2_DIV] = &gxbb_vclk2_div.hw,
3109 [CLKID_VCLK] = &gxbb_vclk.hw,
3110 [CLKID_VCLK2] = &gxbb_vclk2.hw,
3111 [CLKID_VCLK_DIV1] = &gxbb_vclk_div1.hw,
3112 [CLKID_VCLK_DIV2_EN] = &gxbb_vclk_div2_en.hw,
3113 [CLKID_VCLK_DIV2] = &gxbb_vclk_div2.hw,
3114 [CLKID_VCLK_DIV4_EN] = &gxbb_vclk_div4_en.hw,
3115 [CLKID_VCLK_DIV4] = &gxbb_vclk_div4.hw,
3116 [CLKID_VCLK_DIV6_EN] = &gxbb_vclk_div6_en.hw,
3117 [CLKID_VCLK_DIV6] = &gxbb_vclk_div6.hw,
3118 [CLKID_VCLK_DIV12_EN] = &gxbb_vclk_div12_en.hw,
3119 [CLKID_VCLK_DIV12] = &gxbb_vclk_div12.hw,
3120 [CLKID_VCLK2_DIV1] = &gxbb_vclk2_div1.hw,
3121 [CLKID_VCLK2_DIV2_EN] = &gxbb_vclk2_div2_en.hw,
3122 [CLKID_VCLK2_DIV2] = &gxbb_vclk2_div2.hw,
3123 [CLKID_VCLK2_DIV4_EN] = &gxbb_vclk2_div4_en.hw,
3124 [CLKID_VCLK2_DIV4] = &gxbb_vclk2_div4.hw,
3125 [CLKID_VCLK2_DIV6_EN] = &gxbb_vclk2_div6_en.hw,
3126 [CLKID_VCLK2_DIV6] = &gxbb_vclk2_div6.hw,
3127 [CLKID_VCLK2_DIV12_EN] = &gxbb_vclk2_div12_en.hw,
3128 [CLKID_VCLK2_DIV12] = &gxbb_vclk2_div12.hw,
3129 [CLKID_CTS_ENCI_SEL] = &gxbb_cts_enci_sel.hw,
3130 [CLKID_CTS_ENCP_SEL] = &gxbb_cts_encp_sel.hw,
3131 [CLKID_CTS_VDAC_SEL] = &gxbb_cts_vdac_sel.hw,
3132 [CLKID_HDMI_TX_SEL] = &gxbb_hdmi_tx_sel.hw,
3133 [CLKID_CTS_ENCI] = &gxbb_cts_enci.hw,
3134 [CLKID_CTS_ENCP] = &gxbb_cts_encp.hw,
3135 [CLKID_CTS_VDAC] = &gxbb_cts_vdac.hw,
3136 [CLKID_HDMI_TX] = &gxbb_hdmi_tx.hw,
3137 [CLKID_HDMI_SEL] = &gxbb_hdmi_sel.hw,
3138 [CLKID_HDMI_DIV] = &gxbb_hdmi_div.hw,
3139 [CLKID_HDMI] = &gxbb_hdmi.hw,
3140 [CLKID_ACODEC] = &gxl_acodec.hw,
3141 };
3142
3143 static struct clk_regmap *const gxbb_clk_regmaps[] = {
3144 &gxbb_clk81,
3145 &gxbb_ddr,
3146 &gxbb_dos,
3147 &gxbb_isa,
3148 &gxbb_pl301,
3149 &gxbb_periphs,
3150 &gxbb_spicc,
3151 &gxbb_i2c,
3152 &gxbb_sar_adc,
3153 &gxbb_smart_card,
3154 &gxbb_rng0,
3155 &gxbb_uart0,
3156 &gxbb_sdhc,
3157 &gxbb_stream,
3158 &gxbb_async_fifo,
3159 &gxbb_sdio,
3160 &gxbb_abuf,
3161 &gxbb_hiu_iface,
3162 &gxbb_assist_misc,
3163 &gxbb_spi,
3164 &gxbb_i2s_spdif,
3165 &gxbb_eth,
3166 &gxbb_demux,
3167 &gxbb_aiu_glue,
3168 &gxbb_iec958,
3169 &gxbb_i2s_out,
3170 &gxbb_amclk,
3171 &gxbb_aififo2,
3172 &gxbb_mixer,
3173 &gxbb_mixer_iface,
3174 &gxbb_adc,
3175 &gxbb_blkmv,
3176 &gxbb_aiu,
3177 &gxbb_uart1,
3178 &gxbb_g2d,
3179 &gxbb_usb0,
3180 &gxbb_usb1,
3181 &gxbb_reset,
3182 &gxbb_nand,
3183 &gxbb_dos_parser,
3184 &gxbb_usb,
3185 &gxbb_vdin1,
3186 &gxbb_ahb_arb0,
3187 &gxbb_efuse,
3188 &gxbb_boot_rom,
3189 &gxbb_ahb_data_bus,
3190 &gxbb_ahb_ctrl_bus,
3191 &gxbb_hdmi_intr_sync,
3192 &gxbb_hdmi_pclk,
3193 &gxbb_usb1_ddr_bridge,
3194 &gxbb_usb0_ddr_bridge,
3195 &gxbb_mmc_pclk,
3196 &gxbb_dvin,
3197 &gxbb_uart2,
3198 &gxbb_sana,
3199 &gxbb_vpu_intr,
3200 &gxbb_sec_ahb_ahb3_bridge,
3201 &gxbb_clk81_a53,
3202 &gxbb_vclk2_venci0,
3203 &gxbb_vclk2_venci1,
3204 &gxbb_vclk2_vencp0,
3205 &gxbb_vclk2_vencp1,
3206 &gxbb_gclk_venci_int0,
3207 &gxbb_gclk_vencp_int,
3208 &gxbb_dac_clk,
3209 &gxbb_aoclk_gate,
3210 &gxbb_iec958_gate,
3211 &gxbb_enc480p,
3212 &gxbb_rng1,
3213 &gxbb_gclk_venci_int1,
3214 &gxbb_vclk2_venclmcc,
3215 &gxbb_vclk2_vencl,
3216 &gxbb_vclk_other,
3217 &gxbb_edp,
3218 &gxbb_ao_media_cpu,
3219 &gxbb_ao_ahb_sram,
3220 &gxbb_ao_ahb_bus,
3221 &gxbb_ao_iface,
3222 &gxbb_ao_i2c,
3223 &gxbb_emmc_a,
3224 &gxbb_emmc_b,
3225 &gxbb_emmc_c,
3226 &gxbb_sar_adc_clk,
3227 &gxbb_mali_0,
3228 &gxbb_mali_1,
3229 &gxbb_cts_amclk,
3230 &gxbb_cts_mclk_i958,
3231 &gxbb_32k_clk,
3232 &gxbb_sd_emmc_a_clk0,
3233 &gxbb_sd_emmc_b_clk0,
3234 &gxbb_sd_emmc_c_clk0,
3235 &gxbb_vpu_0,
3236 &gxbb_vpu_1,
3237 &gxbb_vapb_0,
3238 &gxbb_vapb_1,
3239 &gxbb_vapb,
3240 &gxbb_mpeg_clk_div,
3241 &gxbb_sar_adc_clk_div,
3242 &gxbb_mali_0_div,
3243 &gxbb_mali_1_div,
3244 &gxbb_cts_mclk_i958_div,
3245 &gxbb_32k_clk_div,
3246 &gxbb_sd_emmc_a_clk0_div,
3247 &gxbb_sd_emmc_b_clk0_div,
3248 &gxbb_sd_emmc_c_clk0_div,
3249 &gxbb_vpu_0_div,
3250 &gxbb_vpu_1_div,
3251 &gxbb_vapb_0_div,
3252 &gxbb_vapb_1_div,
3253 &gxbb_mpeg_clk_sel,
3254 &gxbb_sar_adc_clk_sel,
3255 &gxbb_mali_0_sel,
3256 &gxbb_mali_1_sel,
3257 &gxbb_mali,
3258 &gxbb_cts_amclk_sel,
3259 &gxbb_cts_mclk_i958_sel,
3260 &gxbb_cts_i958,
3261 &gxbb_32k_clk_sel,
3262 &gxbb_sd_emmc_a_clk0_sel,
3263 &gxbb_sd_emmc_b_clk0_sel,
3264 &gxbb_sd_emmc_c_clk0_sel,
3265 &gxbb_vpu_0_sel,
3266 &gxbb_vpu_1_sel,
3267 &gxbb_vpu,
3268 &gxbb_vapb_0_sel,
3269 &gxbb_vapb_1_sel,
3270 &gxbb_vapb_sel,
3271 &gxbb_mpll0,
3272 &gxbb_mpll1,
3273 &gxbb_mpll2,
3274 &gxbb_mpll0_div,
3275 &gxbb_mpll1_div,
3276 &gxbb_mpll2_div,
3277 &gxbb_cts_amclk_div,
3278 &gxbb_fixed_pll,
3279 &gxbb_sys_pll,
3280 &gxbb_mpll_prediv,
3281 &gxbb_fclk_div2,
3282 &gxbb_fclk_div3,
3283 &gxbb_fclk_div4,
3284 &gxbb_fclk_div5,
3285 &gxbb_fclk_div7,
3286 &gxbb_vdec_1_sel,
3287 &gxbb_vdec_1_div,
3288 &gxbb_vdec_1,
3289 &gxbb_vdec_hevc_sel,
3290 &gxbb_vdec_hevc_div,
3291 &gxbb_vdec_hevc,
3292 &gxbb_gen_clk_sel,
3293 &gxbb_gen_clk_div,
3294 &gxbb_gen_clk,
3295 &gxbb_fixed_pll_dco,
3296 &gxbb_sys_pll_dco,
3297 &gxbb_gp0_pll,
3298 &gxbb_vid_pll,
3299 &gxbb_vid_pll_sel,
3300 &gxbb_vid_pll_div,
3301 &gxbb_vclk,
3302 &gxbb_vclk_sel,
3303 &gxbb_vclk_div,
3304 &gxbb_vclk_input,
3305 &gxbb_vclk_div1,
3306 &gxbb_vclk_div2_en,
3307 &gxbb_vclk_div4_en,
3308 &gxbb_vclk_div6_en,
3309 &gxbb_vclk_div12_en,
3310 &gxbb_vclk2,
3311 &gxbb_vclk2_sel,
3312 &gxbb_vclk2_div,
3313 &gxbb_vclk2_input,
3314 &gxbb_vclk2_div1,
3315 &gxbb_vclk2_div2_en,
3316 &gxbb_vclk2_div4_en,
3317 &gxbb_vclk2_div6_en,
3318 &gxbb_vclk2_div12_en,
3319 &gxbb_cts_enci,
3320 &gxbb_cts_enci_sel,
3321 &gxbb_cts_encp,
3322 &gxbb_cts_encp_sel,
3323 &gxbb_cts_vdac,
3324 &gxbb_cts_vdac_sel,
3325 &gxbb_hdmi_tx,
3326 &gxbb_hdmi_tx_sel,
3327 &gxbb_hdmi_sel,
3328 &gxbb_hdmi_div,
3329 &gxbb_hdmi,
3330 &gxbb_gp0_pll_dco,
3331 &gxbb_hdmi_pll,
3332 &gxbb_hdmi_pll_od,
3333 &gxbb_hdmi_pll_od2,
3334 &gxbb_hdmi_pll_dco,
3335 };
3336
3337 static struct clk_regmap *const gxl_clk_regmaps[] = {
3338 &gxbb_clk81,
3339 &gxbb_ddr,
3340 &gxbb_dos,
3341 &gxbb_isa,
3342 &gxbb_pl301,
3343 &gxbb_periphs,
3344 &gxbb_spicc,
3345 &gxbb_i2c,
3346 &gxbb_sar_adc,
3347 &gxbb_smart_card,
3348 &gxbb_rng0,
3349 &gxbb_uart0,
3350 &gxbb_sdhc,
3351 &gxbb_stream,
3352 &gxbb_async_fifo,
3353 &gxbb_sdio,
3354 &gxbb_abuf,
3355 &gxbb_hiu_iface,
3356 &gxbb_assist_misc,
3357 &gxbb_spi,
3358 &gxbb_i2s_spdif,
3359 &gxbb_eth,
3360 &gxbb_demux,
3361 &gxbb_aiu_glue,
3362 &gxbb_iec958,
3363 &gxbb_i2s_out,
3364 &gxbb_amclk,
3365 &gxbb_aififo2,
3366 &gxbb_mixer,
3367 &gxbb_mixer_iface,
3368 &gxbb_adc,
3369 &gxbb_blkmv,
3370 &gxbb_aiu,
3371 &gxbb_uart1,
3372 &gxbb_g2d,
3373 &gxbb_usb0,
3374 &gxbb_usb1,
3375 &gxbb_reset,
3376 &gxbb_nand,
3377 &gxbb_dos_parser,
3378 &gxbb_usb,
3379 &gxbb_vdin1,
3380 &gxbb_ahb_arb0,
3381 &gxbb_efuse,
3382 &gxbb_boot_rom,
3383 &gxbb_ahb_data_bus,
3384 &gxbb_ahb_ctrl_bus,
3385 &gxbb_hdmi_intr_sync,
3386 &gxbb_hdmi_pclk,
3387 &gxbb_usb1_ddr_bridge,
3388 &gxbb_usb0_ddr_bridge,
3389 &gxbb_mmc_pclk,
3390 &gxbb_dvin,
3391 &gxbb_uart2,
3392 &gxbb_sana,
3393 &gxbb_vpu_intr,
3394 &gxbb_sec_ahb_ahb3_bridge,
3395 &gxbb_clk81_a53,
3396 &gxbb_vclk2_venci0,
3397 &gxbb_vclk2_venci1,
3398 &gxbb_vclk2_vencp0,
3399 &gxbb_vclk2_vencp1,
3400 &gxbb_gclk_venci_int0,
3401 &gxbb_gclk_vencp_int,
3402 &gxbb_dac_clk,
3403 &gxbb_aoclk_gate,
3404 &gxbb_iec958_gate,
3405 &gxbb_enc480p,
3406 &gxbb_rng1,
3407 &gxbb_gclk_venci_int1,
3408 &gxbb_vclk2_venclmcc,
3409 &gxbb_vclk2_vencl,
3410 &gxbb_vclk_other,
3411 &gxbb_edp,
3412 &gxbb_ao_media_cpu,
3413 &gxbb_ao_ahb_sram,
3414 &gxbb_ao_ahb_bus,
3415 &gxbb_ao_iface,
3416 &gxbb_ao_i2c,
3417 &gxbb_emmc_a,
3418 &gxbb_emmc_b,
3419 &gxbb_emmc_c,
3420 &gxbb_sar_adc_clk,
3421 &gxbb_mali_0,
3422 &gxbb_mali_1,
3423 &gxbb_cts_amclk,
3424 &gxbb_cts_mclk_i958,
3425 &gxbb_32k_clk,
3426 &gxbb_sd_emmc_a_clk0,
3427 &gxbb_sd_emmc_b_clk0,
3428 &gxbb_sd_emmc_c_clk0,
3429 &gxbb_vpu_0,
3430 &gxbb_vpu_1,
3431 &gxbb_vapb_0,
3432 &gxbb_vapb_1,
3433 &gxbb_vapb,
3434 &gxbb_mpeg_clk_div,
3435 &gxbb_sar_adc_clk_div,
3436 &gxbb_mali_0_div,
3437 &gxbb_mali_1_div,
3438 &gxbb_cts_mclk_i958_div,
3439 &gxbb_32k_clk_div,
3440 &gxbb_sd_emmc_a_clk0_div,
3441 &gxbb_sd_emmc_b_clk0_div,
3442 &gxbb_sd_emmc_c_clk0_div,
3443 &gxbb_vpu_0_div,
3444 &gxbb_vpu_1_div,
3445 &gxbb_vapb_0_div,
3446 &gxbb_vapb_1_div,
3447 &gxbb_mpeg_clk_sel,
3448 &gxbb_sar_adc_clk_sel,
3449 &gxbb_mali_0_sel,
3450 &gxbb_mali_1_sel,
3451 &gxbb_mali,
3452 &gxbb_cts_amclk_sel,
3453 &gxbb_cts_mclk_i958_sel,
3454 &gxbb_cts_i958,
3455 &gxbb_32k_clk_sel,
3456 &gxbb_sd_emmc_a_clk0_sel,
3457 &gxbb_sd_emmc_b_clk0_sel,
3458 &gxbb_sd_emmc_c_clk0_sel,
3459 &gxbb_vpu_0_sel,
3460 &gxbb_vpu_1_sel,
3461 &gxbb_vpu,
3462 &gxbb_vapb_0_sel,
3463 &gxbb_vapb_1_sel,
3464 &gxbb_vapb_sel,
3465 &gxbb_mpll0,
3466 &gxbb_mpll1,
3467 &gxbb_mpll2,
3468 &gxl_mpll0_div,
3469 &gxbb_mpll1_div,
3470 &gxbb_mpll2_div,
3471 &gxbb_cts_amclk_div,
3472 &gxbb_fixed_pll,
3473 &gxbb_sys_pll,
3474 &gxbb_mpll_prediv,
3475 &gxbb_fclk_div2,
3476 &gxbb_fclk_div3,
3477 &gxbb_fclk_div4,
3478 &gxbb_fclk_div5,
3479 &gxbb_fclk_div7,
3480 &gxbb_vdec_1_sel,
3481 &gxbb_vdec_1_div,
3482 &gxbb_vdec_1,
3483 &gxbb_vdec_hevc_sel,
3484 &gxbb_vdec_hevc_div,
3485 &gxbb_vdec_hevc,
3486 &gxbb_gen_clk_sel,
3487 &gxbb_gen_clk_div,
3488 &gxbb_gen_clk,
3489 &gxbb_fixed_pll_dco,
3490 &gxbb_sys_pll_dco,
3491 &gxbb_gp0_pll,
3492 &gxbb_vid_pll,
3493 &gxbb_vid_pll_sel,
3494 &gxbb_vid_pll_div,
3495 &gxbb_vclk,
3496 &gxbb_vclk_sel,
3497 &gxbb_vclk_div,
3498 &gxbb_vclk_input,
3499 &gxbb_vclk_div1,
3500 &gxbb_vclk_div2_en,
3501 &gxbb_vclk_div4_en,
3502 &gxbb_vclk_div6_en,
3503 &gxbb_vclk_div12_en,
3504 &gxbb_vclk2,
3505 &gxbb_vclk2_sel,
3506 &gxbb_vclk2_div,
3507 &gxbb_vclk2_input,
3508 &gxbb_vclk2_div1,
3509 &gxbb_vclk2_div2_en,
3510 &gxbb_vclk2_div4_en,
3511 &gxbb_vclk2_div6_en,
3512 &gxbb_vclk2_div12_en,
3513 &gxbb_cts_enci,
3514 &gxbb_cts_enci_sel,
3515 &gxbb_cts_encp,
3516 &gxbb_cts_encp_sel,
3517 &gxbb_cts_vdac,
3518 &gxbb_cts_vdac_sel,
3519 &gxbb_hdmi_tx,
3520 &gxbb_hdmi_tx_sel,
3521 &gxbb_hdmi_sel,
3522 &gxbb_hdmi_div,
3523 &gxbb_hdmi,
3524 &gxl_gp0_pll_dco,
3525 &gxl_hdmi_pll,
3526 &gxl_hdmi_pll_od,
3527 &gxl_hdmi_pll_od2,
3528 &gxl_hdmi_pll_dco,
3529 &gxl_acodec,
3530 };
3531
3532 static const struct meson_eeclkc_data gxbb_clkc_data = {
3533 .regmap_clks = gxbb_clk_regmaps,
3534 .regmap_clk_num = ARRAY_SIZE(gxbb_clk_regmaps),
3535 .hw_clks = {
3536 .hws = gxbb_hw_clks,
3537 .num = ARRAY_SIZE(gxbb_hw_clks),
3538 },
3539 };
3540
3541 static const struct meson_eeclkc_data gxl_clkc_data = {
3542 .regmap_clks = gxl_clk_regmaps,
3543 .regmap_clk_num = ARRAY_SIZE(gxl_clk_regmaps),
3544 .hw_clks = {
3545 .hws = gxl_hw_clks,
3546 .num = ARRAY_SIZE(gxl_hw_clks),
3547 },
3548 };
3549
3550 static const struct of_device_id clkc_match_table[] = {
3551 { .compatible = "amlogic,gxbb-clkc", .data = &gxbb_clkc_data },
3552 { .compatible = "amlogic,gxl-clkc", .data = &gxl_clkc_data },
3553 {},
3554 };
3555 MODULE_DEVICE_TABLE(of, clkc_match_table);
3556
3557 static struct platform_driver gxbb_driver = {
3558 .probe = meson_eeclkc_probe,
3559 .driver = {
3560 .name = "gxbb-clkc",
3561 .of_match_table = clkc_match_table,
3562 },
3563 };
3564 module_platform_driver(gxbb_driver);
3565
3566 MODULE_DESCRIPTION("Amlogic GXBB Main Clock Controller driver");
3567 MODULE_LICENSE("GPL");
3568 MODULE_IMPORT_NS("CLK_MESON");
Linux Kernel