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Revert "unicode: Don't special case ignorable code points"
[linux.git] / drivers / crypto / hisilicon / sec2 / sec_main.c
blob8ec5333bb5aa32d044fc47ec4b75f6309db79bcc
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2019 HiSilicon Limited. */
3
4 #include <linux/acpi.h>
5 #include <linux/bitops.h>
6 #include <linux/debugfs.h>
7 #include <linux/init.h>
8 #include <linux/io.h>
9 #include <linux/iommu.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/seq_file.h>
15 #include <linux/topology.h>
16 #include <linux/uacce.h>
17 #include "sec.h"
18
19 #define CAP_FILE_PERMISSION 0444
20 #define SEC_VF_NUM 63
21 #define SEC_QUEUE_NUM_V1 4096
22 #define PCI_DEVICE_ID_HUAWEI_SEC_PF 0xa255
23
24 #define SEC_BD_ERR_CHK_EN0 0xEFFFFFFF
25 #define SEC_BD_ERR_CHK_EN1 0x7ffff7fd
26 #define SEC_BD_ERR_CHK_EN3 0xffffbfff
27
28 #define SEC_SQE_SIZE 128
29 #define SEC_PF_DEF_Q_NUM 256
30 #define SEC_PF_DEF_Q_BASE 0
31 #define SEC_CTX_Q_NUM_DEF 2
32 #define SEC_CTX_Q_NUM_MAX 32
33
34 #define SEC_CTRL_CNT_CLR_CE 0x301120
35 #define SEC_CTRL_CNT_CLR_CE_BIT BIT(0)
36 #define SEC_CORE_INT_SOURCE 0x301010
37 #define SEC_CORE_INT_MASK 0x301000
38 #define SEC_CORE_INT_STATUS 0x301008
39 #define SEC_CORE_SRAM_ECC_ERR_INFO 0x301C14
40 #define SEC_ECC_NUM 16
41 #define SEC_ECC_MASH 0xFF
42 #define SEC_CORE_INT_DISABLE 0x0
43
44 #define SEC_RAS_CE_REG 0x301050
45 #define SEC_RAS_FE_REG 0x301054
46 #define SEC_RAS_NFE_REG 0x301058
47 #define SEC_RAS_FE_ENB_MSK 0x0
48 #define SEC_OOO_SHUTDOWN_SEL 0x301014
49 #define SEC_RAS_DISABLE 0x0
50 #define SEC_MEM_START_INIT_REG 0x301100
51 #define SEC_MEM_INIT_DONE_REG 0x301104
52
53 /* clock gating */
54 #define SEC_CONTROL_REG 0x301200
55 #define SEC_DYNAMIC_GATE_REG 0x30121c
56 #define SEC_CORE_AUTO_GATE 0x30212c
57 #define SEC_DYNAMIC_GATE_EN 0x7fff
58 #define SEC_CORE_AUTO_GATE_EN GENMASK(3, 0)
59 #define SEC_CLK_GATE_ENABLE BIT(3)
60 #define SEC_CLK_GATE_DISABLE (~BIT(3))
61
62 #define SEC_TRNG_EN_SHIFT 8
63 #define SEC_AXI_SHUTDOWN_ENABLE BIT(12)
64 #define SEC_AXI_SHUTDOWN_DISABLE 0xFFFFEFFF
65
66 #define SEC_INTERFACE_USER_CTRL0_REG 0x301220
67 #define SEC_INTERFACE_USER_CTRL1_REG 0x301224
68 #define SEC_SAA_EN_REG 0x301270
69 #define SEC_BD_ERR_CHK_EN_REG0 0x301380
70 #define SEC_BD_ERR_CHK_EN_REG1 0x301384
71 #define SEC_BD_ERR_CHK_EN_REG3 0x30138c
72
73 #define SEC_USER0_SMMU_NORMAL (BIT(23) | BIT(15))
74 #define SEC_USER1_SMMU_NORMAL (BIT(31) | BIT(23) | BIT(15) | BIT(7))
75 #define SEC_USER1_ENABLE_CONTEXT_SSV BIT(24)
76 #define SEC_USER1_ENABLE_DATA_SSV BIT(16)
77 #define SEC_USER1_WB_CONTEXT_SSV BIT(8)
78 #define SEC_USER1_WB_DATA_SSV BIT(0)
79 #define SEC_USER1_SVA_SET (SEC_USER1_ENABLE_CONTEXT_SSV | \
80 SEC_USER1_ENABLE_DATA_SSV | \
81 SEC_USER1_WB_CONTEXT_SSV | \
82 SEC_USER1_WB_DATA_SSV)
83 #define SEC_USER1_SMMU_SVA (SEC_USER1_SMMU_NORMAL | SEC_USER1_SVA_SET)
84 #define SEC_USER1_SMMU_MASK (~SEC_USER1_SVA_SET)
85 #define SEC_INTERFACE_USER_CTRL0_REG_V3 0x302220
86 #define SEC_INTERFACE_USER_CTRL1_REG_V3 0x302224
87 #define SEC_USER1_SMMU_NORMAL_V3 (BIT(23) | BIT(17) | BIT(11) | BIT(5))
88 #define SEC_USER1_SMMU_MASK_V3 0xFF79E79E
89 #define SEC_CORE_INT_STATUS_M_ECC BIT(2)
90
91 #define SEC_PREFETCH_CFG 0x301130
92 #define SEC_SVA_TRANS 0x301EC4
93 #define SEC_PREFETCH_ENABLE (~(BIT(0) | BIT(1) | BIT(11)))
94 #define SEC_PREFETCH_DISABLE BIT(1)
95 #define SEC_SVA_DISABLE_READY (BIT(7) | BIT(11))
96
97 #define SEC_DELAY_10_US 10
98 #define SEC_POLL_TIMEOUT_US 1000
99 #define SEC_DBGFS_VAL_MAX_LEN 20
100 #define SEC_SINGLE_PORT_MAX_TRANS 0x2060
101
102 #define SEC_SQE_MASK_OFFSET 16
103 #define SEC_SQE_MASK_LEN 108
104 #define SEC_SHAPER_TYPE_RATE 400
105
106 #define SEC_DFX_BASE 0x301000
107 #define SEC_DFX_CORE 0x302100
108 #define SEC_DFX_COMMON1 0x301600
109 #define SEC_DFX_COMMON2 0x301C00
110 #define SEC_DFX_BASE_LEN 0x9D
111 #define SEC_DFX_CORE_LEN 0x32B
112 #define SEC_DFX_COMMON1_LEN 0x45
113 #define SEC_DFX_COMMON2_LEN 0xBA
114
115 #define SEC_ALG_BITMAP_SHIFT 32
116
117 #define SEC_CIPHER_BITMAP (GENMASK_ULL(5, 0) | GENMASK_ULL(16, 12) | \
118 GENMASK(24, 21))
119 #define SEC_DIGEST_BITMAP (GENMASK_ULL(11, 8) | GENMASK_ULL(20, 19) | \
120 GENMASK_ULL(42, 25))
121 #define SEC_AEAD_BITMAP (GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \
122 GENMASK_ULL(45, 43))
123
124 struct sec_hw_error {
125 u32 int_msk;
126 const char *msg;
127 };
128
129 struct sec_dfx_item {
130 const char *name;
131 u32 offset;
132 };
133
134 static const char sec_name[] = "hisi_sec2";
135 static struct dentry *sec_debugfs_root;
136
137 static struct hisi_qm_list sec_devices = {
138 .register_to_crypto = sec_register_to_crypto,
139 .unregister_from_crypto = sec_unregister_from_crypto,
140 };
141
142 static const struct hisi_qm_cap_info sec_basic_info[] = {
143 {SEC_QM_NFE_MASK_CAP, 0x3124, 0, GENMASK(31, 0), 0x0, 0x1C77, 0x7C77},
144 {SEC_QM_RESET_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0xC77, 0x6C77},
145 {SEC_QM_OOO_SHUTDOWN_MASK_CAP, 0x3128, 0, GENMASK(31, 0), 0x0, 0x4, 0x6C77},
146 {SEC_QM_CE_MASK_CAP, 0x312C, 0, GENMASK(31, 0), 0x0, 0x8, 0x8},
147 {SEC_NFE_MASK_CAP, 0x3130, 0, GENMASK(31, 0), 0x0, 0x177, 0x60177},
148 {SEC_RESET_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x177, 0x177},
149 {SEC_OOO_SHUTDOWN_MASK_CAP, 0x3134, 0, GENMASK(31, 0), 0x0, 0x4, 0x177},
150 {SEC_CE_MASK_CAP, 0x3138, 0, GENMASK(31, 0), 0x0, 0x88, 0xC088},
151 {SEC_CLUSTER_NUM_CAP, 0x313c, 20, GENMASK(3, 0), 0x1, 0x1, 0x1},
152 {SEC_CORE_TYPE_NUM_CAP, 0x313c, 16, GENMASK(3, 0), 0x1, 0x1, 0x1},
153 {SEC_CORE_NUM_CAP, 0x313c, 8, GENMASK(7, 0), 0x4, 0x4, 0x4},
154 {SEC_CORES_PER_CLUSTER_NUM_CAP, 0x313c, 0, GENMASK(7, 0), 0x4, 0x4, 0x4},
155 {SEC_CORE_ENABLE_BITMAP, 0x3140, 0, GENMASK(31, 0), 0x17F, 0x17F, 0xF},
156 {SEC_DRV_ALG_BITMAP_LOW, 0x3144, 0, GENMASK(31, 0), 0x18050CB, 0x18050CB, 0x18670CF},
157 {SEC_DRV_ALG_BITMAP_HIGH, 0x3148, 0, GENMASK(31, 0), 0x395C, 0x395C, 0x395C},
158 {SEC_DEV_ALG_BITMAP_LOW, 0x314c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
159 {SEC_DEV_ALG_BITMAP_HIGH, 0x3150, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
160 {SEC_CORE1_ALG_BITMAP_LOW, 0x3154, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
161 {SEC_CORE1_ALG_BITMAP_HIGH, 0x3158, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
162 {SEC_CORE2_ALG_BITMAP_LOW, 0x315c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
163 {SEC_CORE2_ALG_BITMAP_HIGH, 0x3160, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
164 {SEC_CORE3_ALG_BITMAP_LOW, 0x3164, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
165 {SEC_CORE3_ALG_BITMAP_HIGH, 0x3168, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
166 {SEC_CORE4_ALG_BITMAP_LOW, 0x316c, 0, GENMASK(31, 0), 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
167 {SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},
168 };
169
170 static const struct hisi_qm_cap_query_info sec_cap_query_info[] = {
171 {QM_RAS_NFE_TYPE, "QM_RAS_NFE_TYPE ", 0x3124, 0x0, 0x1C77, 0x7C77},
172 {QM_RAS_NFE_RESET, "QM_RAS_NFE_RESET ", 0x3128, 0x0, 0xC77, 0x6C77},
173 {QM_RAS_CE_TYPE, "QM_RAS_CE_TYPE ", 0x312C, 0x0, 0x8, 0x8},
174 {SEC_RAS_NFE_TYPE, "SEC_RAS_NFE_TYPE ", 0x3130, 0x0, 0x177, 0x60177},
175 {SEC_RAS_NFE_RESET, "SEC_RAS_NFE_RESET ", 0x3134, 0x0, 0x177, 0x177},
176 {SEC_RAS_CE_TYPE, "SEC_RAS_CE_TYPE ", 0x3138, 0x0, 0x88, 0xC088},
177 {SEC_CORE_INFO, "SEC_CORE_INFO ", 0x313c, 0x110404, 0x110404, 0x110404},
178 {SEC_CORE_EN, "SEC_CORE_EN ", 0x3140, 0x17F, 0x17F, 0xF},
179 {SEC_DRV_ALG_BITMAP_LOW_TB, "SEC_DRV_ALG_BITMAP_LOW ",
180 0x3144, 0x18050CB, 0x18050CB, 0x18670CF},
181 {SEC_DRV_ALG_BITMAP_HIGH_TB, "SEC_DRV_ALG_BITMAP_HIGH ",
182 0x3148, 0x395C, 0x395C, 0x395C},
183 {SEC_ALG_BITMAP_LOW, "SEC_ALG_BITMAP_LOW ",
184 0x314c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
185 {SEC_ALG_BITMAP_HIGH, "SEC_ALG_BITMAP_HIGH ", 0x3150, 0x3FFF, 0x3FFF, 0x3FFF},
186 {SEC_CORE1_BITMAP_LOW, "SEC_CORE1_BITMAP_LOW ",
187 0x3154, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
188 {SEC_CORE1_BITMAP_HIGH, "SEC_CORE1_BITMAP_HIGH ", 0x3158, 0x3FFF, 0x3FFF, 0x3FFF},
189 {SEC_CORE2_BITMAP_LOW, "SEC_CORE2_BITMAP_LOW ",
190 0x315c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
191 {SEC_CORE2_BITMAP_HIGH, "SEC_CORE2_BITMAP_HIGH ", 0x3160, 0x3FFF, 0x3FFF, 0x3FFF},
192 {SEC_CORE3_BITMAP_LOW, "SEC_CORE3_BITMAP_LOW ",
193 0x3164, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
194 {SEC_CORE3_BITMAP_HIGH, "SEC_CORE3_BITMAP_HIGH ", 0x3168, 0x3FFF, 0x3FFF, 0x3FFF},
195 {SEC_CORE4_BITMAP_LOW, "SEC_CORE4_BITMAP_LOW ",
196 0x316c, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF},
197 {SEC_CORE4_BITMAP_HIGH, "SEC_CORE4_BITMAP_HIGH ", 0x3170, 0x3FFF, 0x3FFF, 0x3FFF},
198 };
199
200 static const struct qm_dev_alg sec_dev_algs[] = { {
201 .alg_msk = SEC_CIPHER_BITMAP,
202 .alg = "cipher\n",
203 }, {
204 .alg_msk = SEC_DIGEST_BITMAP,
205 .alg = "digest\n",
206 }, {
207 .alg_msk = SEC_AEAD_BITMAP,
208 .alg = "aead\n",
209 },
210 };
211
212 static const struct sec_hw_error sec_hw_errors[] = {
213 {
214 .int_msk = BIT(0),
215 .msg = "sec_axi_rresp_err_rint"
216 },
217 {
218 .int_msk = BIT(1),
219 .msg = "sec_axi_bresp_err_rint"
220 },
221 {
222 .int_msk = BIT(2),
223 .msg = "sec_ecc_2bit_err_rint"
224 },
225 {
226 .int_msk = BIT(3),
227 .msg = "sec_ecc_1bit_err_rint"
228 },
229 {
230 .int_msk = BIT(4),
231 .msg = "sec_req_trng_timeout_rint"
232 },
233 {
234 .int_msk = BIT(5),
235 .msg = "sec_fsm_hbeat_rint"
236 },
237 {
238 .int_msk = BIT(6),
239 .msg = "sec_channel_req_rng_timeout_rint"
240 },
241 {
242 .int_msk = BIT(7),
243 .msg = "sec_bd_err_rint"
244 },
245 {
246 .int_msk = BIT(8),
247 .msg = "sec_chain_buff_err_rint"
248 },
249 {
250 .int_msk = BIT(14),
251 .msg = "sec_no_secure_access"
252 },
253 {
254 .int_msk = BIT(15),
255 .msg = "sec_wrapping_key_auth_err"
256 },
257 {
258 .int_msk = BIT(16),
259 .msg = "sec_km_key_crc_fail"
260 },
261 {
262 .int_msk = BIT(17),
263 .msg = "sec_axi_poison_err"
264 },
265 {
266 .int_msk = BIT(18),
267 .msg = "sec_sva_err"
268 },
269 {}
270 };
271
272 static const char * const sec_dbg_file_name[] = {
273 [SEC_CLEAR_ENABLE] = "clear_enable",
274 };
275
276 static struct sec_dfx_item sec_dfx_labels[] = {
277 {"send_cnt", offsetof(struct sec_dfx, send_cnt)},
278 {"recv_cnt", offsetof(struct sec_dfx, recv_cnt)},
279 {"send_busy_cnt", offsetof(struct sec_dfx, send_busy_cnt)},
280 {"recv_busy_cnt", offsetof(struct sec_dfx, recv_busy_cnt)},
281 {"err_bd_cnt", offsetof(struct sec_dfx, err_bd_cnt)},
282 {"invalid_req_cnt", offsetof(struct sec_dfx, invalid_req_cnt)},
283 {"done_flag_cnt", offsetof(struct sec_dfx, done_flag_cnt)},
284 };
285
286 static const struct debugfs_reg32 sec_dfx_regs[] = {
287 {"SEC_PF_ABNORMAL_INT_SOURCE ", 0x301010},
288 {"SEC_SAA_EN ", 0x301270},
289 {"SEC_BD_LATENCY_MIN ", 0x301600},
290 {"SEC_BD_LATENCY_MAX ", 0x301608},
291 {"SEC_BD_LATENCY_AVG ", 0x30160C},
292 {"SEC_BD_NUM_IN_SAA0 ", 0x301670},
293 {"SEC_BD_NUM_IN_SAA1 ", 0x301674},
294 {"SEC_BD_NUM_IN_SEC ", 0x301680},
295 {"SEC_ECC_1BIT_CNT ", 0x301C00},
296 {"SEC_ECC_1BIT_INFO ", 0x301C04},
297 {"SEC_ECC_2BIT_CNT ", 0x301C10},
298 {"SEC_ECC_2BIT_INFO ", 0x301C14},
299 {"SEC_BD_SAA0 ", 0x301C20},
300 {"SEC_BD_SAA1 ", 0x301C24},
301 {"SEC_BD_SAA2 ", 0x301C28},
302 {"SEC_BD_SAA3 ", 0x301C2C},
303 {"SEC_BD_SAA4 ", 0x301C30},
304 {"SEC_BD_SAA5 ", 0x301C34},
305 {"SEC_BD_SAA6 ", 0x301C38},
306 {"SEC_BD_SAA7 ", 0x301C3C},
307 {"SEC_BD_SAA8 ", 0x301C40},
308 {"SEC_RAS_CE_ENABLE ", 0x301050},
309 {"SEC_RAS_FE_ENABLE ", 0x301054},
310 {"SEC_RAS_NFE_ENABLE ", 0x301058},
311 {"SEC_REQ_TRNG_TIME_TH ", 0x30112C},
312 {"SEC_CHANNEL_RNG_REQ_THLD ", 0x302110},
313 };
314
315 /* define the SEC's dfx regs region and region length */
316 static struct dfx_diff_registers sec_diff_regs[] = {
317 {
318 .reg_offset = SEC_DFX_BASE,
319 .reg_len = SEC_DFX_BASE_LEN,
320 }, {
321 .reg_offset = SEC_DFX_COMMON1,
322 .reg_len = SEC_DFX_COMMON1_LEN,
323 }, {
324 .reg_offset = SEC_DFX_COMMON2,
325 .reg_len = SEC_DFX_COMMON2_LEN,
326 }, {
327 .reg_offset = SEC_DFX_CORE,
328 .reg_len = SEC_DFX_CORE_LEN,
329 },
330 };
331
332 static int sec_diff_regs_show(struct seq_file *s, void *unused)
333 {
334 struct hisi_qm *qm = s->private;
335
336 hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.acc_diff_regs,
337 ARRAY_SIZE(sec_diff_regs));
338
339 return 0;
340 }
341 DEFINE_SHOW_ATTRIBUTE(sec_diff_regs);
342
343 static bool pf_q_num_flag;
344 static int sec_pf_q_num_set(const char *val, const struct kernel_param *kp)
345 {
346 pf_q_num_flag = true;
347
348 return hisi_qm_q_num_set(val, kp, PCI_DEVICE_ID_HUAWEI_SEC_PF);
349 }
350
351 static const struct kernel_param_ops sec_pf_q_num_ops = {
352 .set = sec_pf_q_num_set,
353 .get = param_get_int,
354 };
355
356 static u32 pf_q_num = SEC_PF_DEF_Q_NUM;
357 module_param_cb(pf_q_num, &sec_pf_q_num_ops, &pf_q_num, 0444);
358 MODULE_PARM_DESC(pf_q_num, "Number of queues in PF(v1 2-4096, v2 2-1024)");
359
360 static int sec_ctx_q_num_set(const char *val, const struct kernel_param *kp)
361 {
362 u32 ctx_q_num;
363 int ret;
364
365 if (!val)
366 return -EINVAL;
367
368 ret = kstrtou32(val, 10, &ctx_q_num);
369 if (ret)
370 return -EINVAL;
371
372 if (!ctx_q_num || ctx_q_num > SEC_CTX_Q_NUM_MAX || ctx_q_num & 0x1) {
373 pr_err("ctx queue num[%u] is invalid!\n", ctx_q_num);
374 return -EINVAL;
375 }
376
377 return param_set_int(val, kp);
378 }
379
380 static const struct kernel_param_ops sec_ctx_q_num_ops = {
381 .set = sec_ctx_q_num_set,
382 .get = param_get_int,
383 };
384 static u32 ctx_q_num = SEC_CTX_Q_NUM_DEF;
385 module_param_cb(ctx_q_num, &sec_ctx_q_num_ops, &ctx_q_num, 0444);
386 MODULE_PARM_DESC(ctx_q_num, "Queue num in ctx (2 default, 2, 4, ..., 32)");
387
388 static const struct kernel_param_ops vfs_num_ops = {
389 .set = vfs_num_set,
390 .get = param_get_int,
391 };
392
393 static u32 vfs_num;
394 module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444);
395 MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)");
396
397 void sec_destroy_qps(struct hisi_qp **qps, int qp_num)
398 {
399 hisi_qm_free_qps(qps, qp_num);
400 kfree(qps);
401 }
402
403 struct hisi_qp **sec_create_qps(void)
404 {
405 int node = cpu_to_node(raw_smp_processor_id());
406 u32 ctx_num = ctx_q_num;
407 struct hisi_qp **qps;
408 int ret;
409
410 qps = kcalloc(ctx_num, sizeof(struct hisi_qp *), GFP_KERNEL);
411 if (!qps)
412 return NULL;
413
414 ret = hisi_qm_alloc_qps_node(&sec_devices, ctx_num, 0, node, qps);
415 if (!ret)
416 return qps;
417
418 kfree(qps);
419 return NULL;
420 }
421
422 u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low)
423 {
424 u32 cap_val_h, cap_val_l;
425
426 cap_val_h = qm->cap_tables.dev_cap_table[high].cap_val;
427 cap_val_l = qm->cap_tables.dev_cap_table[low].cap_val;
428
429 return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l;
430 }
431
432 static const struct kernel_param_ops sec_uacce_mode_ops = {
433 .set = uacce_mode_set,
434 .get = param_get_int,
435 };
436
437 /*
438 * uacce_mode = 0 means sec only register to crypto,
439 * uacce_mode = 1 means sec both register to crypto and uacce.
440 */
441 static u32 uacce_mode = UACCE_MODE_NOUACCE;
442 module_param_cb(uacce_mode, &sec_uacce_mode_ops, &uacce_mode, 0444);
443 MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC);
444
445 static const struct pci_device_id sec_dev_ids[] = {
446 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_PF) },
447 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HUAWEI_SEC_VF) },
448 { 0, }
449 };
450 MODULE_DEVICE_TABLE(pci, sec_dev_ids);
451
452 static void sec_set_endian(struct hisi_qm *qm)
453 {
454 u32 reg;
455
456 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
457 reg &= ~(BIT(1) | BIT(0));
458 if (!IS_ENABLED(CONFIG_64BIT))
459 reg |= BIT(1);
460
461 if (!IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
462 reg |= BIT(0);
463
464 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
465 }
466
467 static void sec_engine_sva_config(struct hisi_qm *qm)
468 {
469 u32 reg;
470
471 if (qm->ver > QM_HW_V2) {
472 reg = readl_relaxed(qm->io_base +
473 SEC_INTERFACE_USER_CTRL0_REG_V3);
474 reg |= SEC_USER0_SMMU_NORMAL;
475 writel_relaxed(reg, qm->io_base +
476 SEC_INTERFACE_USER_CTRL0_REG_V3);
477
478 reg = readl_relaxed(qm->io_base +
479 SEC_INTERFACE_USER_CTRL1_REG_V3);
480 reg &= SEC_USER1_SMMU_MASK_V3;
481 reg |= SEC_USER1_SMMU_NORMAL_V3;
482 writel_relaxed(reg, qm->io_base +
483 SEC_INTERFACE_USER_CTRL1_REG_V3);
484 } else {
485 reg = readl_relaxed(qm->io_base +
486 SEC_INTERFACE_USER_CTRL0_REG);
487 reg |= SEC_USER0_SMMU_NORMAL;
488 writel_relaxed(reg, qm->io_base +
489 SEC_INTERFACE_USER_CTRL0_REG);
490 reg = readl_relaxed(qm->io_base +
491 SEC_INTERFACE_USER_CTRL1_REG);
492 reg &= SEC_USER1_SMMU_MASK;
493 if (qm->use_sva)
494 reg |= SEC_USER1_SMMU_SVA;
495 else
496 reg |= SEC_USER1_SMMU_NORMAL;
497 writel_relaxed(reg, qm->io_base +
498 SEC_INTERFACE_USER_CTRL1_REG);
499 }
500 }
501
502 static void sec_open_sva_prefetch(struct hisi_qm *qm)
503 {
504 u32 val;
505 int ret;
506
507 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
508 return;
509
510 /* Enable prefetch */
511 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
512 val &= SEC_PREFETCH_ENABLE;
513 writel(val, qm->io_base + SEC_PREFETCH_CFG);
514
515 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_PREFETCH_CFG,
516 val, !(val & SEC_PREFETCH_DISABLE),
517 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
518 if (ret)
519 pci_err(qm->pdev, "failed to open sva prefetch\n");
520 }
521
522 static void sec_close_sva_prefetch(struct hisi_qm *qm)
523 {
524 u32 val;
525 int ret;
526
527 if (!test_bit(QM_SUPPORT_SVA_PREFETCH, &qm->caps))
528 return;
529
530 val = readl_relaxed(qm->io_base + SEC_PREFETCH_CFG);
531 val |= SEC_PREFETCH_DISABLE;
532 writel(val, qm->io_base + SEC_PREFETCH_CFG);
533
534 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_SVA_TRANS,
535 val, !(val & SEC_SVA_DISABLE_READY),
536 SEC_DELAY_10_US, SEC_POLL_TIMEOUT_US);
537 if (ret)
538 pci_err(qm->pdev, "failed to close sva prefetch\n");
539 }
540
541 static void sec_enable_clock_gate(struct hisi_qm *qm)
542 {
543 u32 val;
544
545 if (qm->ver < QM_HW_V3)
546 return;
547
548 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
549 val |= SEC_CLK_GATE_ENABLE;
550 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
551
552 val = readl(qm->io_base + SEC_DYNAMIC_GATE_REG);
553 val |= SEC_DYNAMIC_GATE_EN;
554 writel(val, qm->io_base + SEC_DYNAMIC_GATE_REG);
555
556 val = readl(qm->io_base + SEC_CORE_AUTO_GATE);
557 val |= SEC_CORE_AUTO_GATE_EN;
558 writel(val, qm->io_base + SEC_CORE_AUTO_GATE);
559 }
560
561 static void sec_disable_clock_gate(struct hisi_qm *qm)
562 {
563 u32 val;
564
565 /* Kunpeng920 needs to close clock gating */
566 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
567 val &= SEC_CLK_GATE_DISABLE;
568 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG);
569 }
570
571 static int sec_engine_init(struct hisi_qm *qm)
572 {
573 int ret;
574 u32 reg;
575
576 /* disable clock gate control before mem init */
577 sec_disable_clock_gate(qm);
578
579 writel_relaxed(0x1, qm->io_base + SEC_MEM_START_INIT_REG);
580
581 ret = readl_relaxed_poll_timeout(qm->io_base + SEC_MEM_INIT_DONE_REG,
582 reg, reg & 0x1, SEC_DELAY_10_US,
583 SEC_POLL_TIMEOUT_US);
584 if (ret) {
585 pci_err(qm->pdev, "fail to init sec mem\n");
586 return ret;
587 }
588
589 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG);
590 reg |= (0x1 << SEC_TRNG_EN_SHIFT);
591 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG);
592
593 sec_engine_sva_config(qm);
594
595 writel(SEC_SINGLE_PORT_MAX_TRANS,
596 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS);
597
598 reg = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CORE_ENABLE_BITMAP, qm->cap_ver);
599 writel(reg, qm->io_base + SEC_SAA_EN_REG);
600
601 if (qm->ver < QM_HW_V3) {
602 /* HW V2 enable sm4 extra mode, as ctr/ecb */
603 writel_relaxed(SEC_BD_ERR_CHK_EN0,
604 qm->io_base + SEC_BD_ERR_CHK_EN_REG0);
605
606 /* HW V2 enable sm4 xts mode multiple iv */
607 writel_relaxed(SEC_BD_ERR_CHK_EN1,
608 qm->io_base + SEC_BD_ERR_CHK_EN_REG1);
609 writel_relaxed(SEC_BD_ERR_CHK_EN3,
610 qm->io_base + SEC_BD_ERR_CHK_EN_REG3);
611 }
612
613 /* config endian */
614 sec_set_endian(qm);
615
616 sec_enable_clock_gate(qm);
617
618 return 0;
619 }
620
621 static int sec_set_user_domain_and_cache(struct hisi_qm *qm)
622 {
623 /* qm user domain */
624 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1);
625 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE);
626 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1);
627 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE);
628 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE);
629
630 /* qm cache */
631 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG);
632 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE);
633
634 /* disable FLR triggered by BME(bus master enable) */
635 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG);
636 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE);
637
638 /* enable sqc,cqc writeback */
639 writel(SQC_CACHE_ENABLE | CQC_CACHE_ENABLE | SQC_CACHE_WB_ENABLE |
640 CQC_CACHE_WB_ENABLE | FIELD_PREP(SQC_CACHE_WB_THRD, 1) |
641 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL);
642
643 return sec_engine_init(qm);
644 }
645
646 /* sec_debug_regs_clear() - clear the sec debug regs */
647 static void sec_debug_regs_clear(struct hisi_qm *qm)
648 {
649 int i;
650
651 /* clear sec dfx regs */
652 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE);
653 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++)
654 readl(qm->io_base + sec_dfx_regs[i].offset);
655
656 /* clear rdclr_en */
657 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE);
658
659 hisi_qm_debug_regs_clear(qm);
660 }
661
662 static void sec_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
663 {
664 u32 val1, val2;
665
666 val1 = readl(qm->io_base + SEC_CONTROL_REG);
667 if (enable) {
668 val1 |= SEC_AXI_SHUTDOWN_ENABLE;
669 val2 = hisi_qm_get_hw_info(qm, sec_basic_info,
670 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
671 } else {
672 val1 &= SEC_AXI_SHUTDOWN_DISABLE;
673 val2 = 0x0;
674 }
675
676 if (qm->ver > QM_HW_V2)
677 writel(val2, qm->io_base + SEC_OOO_SHUTDOWN_SEL);
678
679 writel(val1, qm->io_base + SEC_CONTROL_REG);
680 }
681
682 static void sec_hw_error_enable(struct hisi_qm *qm)
683 {
684 u32 ce, nfe;
685
686 if (qm->ver == QM_HW_V1) {
687 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
688 pci_info(qm->pdev, "V1 not support hw error handle\n");
689 return;
690 }
691
692 ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_CE_MASK_CAP, qm->cap_ver);
693 nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);
694
695 /* clear SEC hw error source if having */
696 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_SOURCE);
697
698 /* enable RAS int */
699 writel(ce, qm->io_base + SEC_RAS_CE_REG);
700 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG);
701 writel(nfe, qm->io_base + SEC_RAS_NFE_REG);
702
703 /* enable SEC block master OOO when nfe occurs on Kunpeng930 */
704 sec_master_ooo_ctrl(qm, true);
705
706 /* enable SEC hw error interrupts */
707 writel(ce | nfe | SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_CORE_INT_MASK);
708 }
709
710 static void sec_hw_error_disable(struct hisi_qm *qm)
711 {
712 /* disable SEC hw error interrupts */
713 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK);
714
715 /* disable SEC block master OOO when nfe occurs on Kunpeng930 */
716 sec_master_ooo_ctrl(qm, false);
717
718 /* disable RAS int */
719 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG);
720 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG);
721 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG);
722 }
723
724 static u32 sec_clear_enable_read(struct hisi_qm *qm)
725 {
726 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
727 SEC_CTRL_CNT_CLR_CE_BIT;
728 }
729
730 static int sec_clear_enable_write(struct hisi_qm *qm, u32 val)
731 {
732 u32 tmp;
733
734 if (val != 1 && val)
735 return -EINVAL;
736
737 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) &
738 ~SEC_CTRL_CNT_CLR_CE_BIT) | val;
739 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE);
740
741 return 0;
742 }
743
744 static ssize_t sec_debug_read(struct file *filp, char __user *buf,
745 size_t count, loff_t *pos)
746 {
747 struct sec_debug_file *file = filp->private_data;
748 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
749 struct hisi_qm *qm = file->qm;
750 u32 val;
751 int ret;
752
753 ret = hisi_qm_get_dfx_access(qm);
754 if (ret)
755 return ret;
756
757 spin_lock_irq(&file->lock);
758
759 switch (file->index) {
760 case SEC_CLEAR_ENABLE:
761 val = sec_clear_enable_read(qm);
762 break;
763 default:
764 goto err_input;
765 }
766
767 spin_unlock_irq(&file->lock);
768
769 hisi_qm_put_dfx_access(qm);
770 ret = snprintf(tbuf, SEC_DBGFS_VAL_MAX_LEN, "%u\n", val);
771 return simple_read_from_buffer(buf, count, pos, tbuf, ret);
772
773 err_input:
774 spin_unlock_irq(&file->lock);
775 hisi_qm_put_dfx_access(qm);
776 return -EINVAL;
777 }
778
779 static ssize_t sec_debug_write(struct file *filp, const char __user *buf,
780 size_t count, loff_t *pos)
781 {
782 struct sec_debug_file *file = filp->private_data;
783 char tbuf[SEC_DBGFS_VAL_MAX_LEN];
784 struct hisi_qm *qm = file->qm;
785 unsigned long val;
786 int len, ret;
787
788 if (*pos != 0)
789 return 0;
790
791 if (count >= SEC_DBGFS_VAL_MAX_LEN)
792 return -ENOSPC;
793
794 len = simple_write_to_buffer(tbuf, SEC_DBGFS_VAL_MAX_LEN - 1,
795 pos, buf, count);
796 if (len < 0)
797 return len;
798
799 tbuf[len] = '\0';
800 if (kstrtoul(tbuf, 0, &val))
801 return -EFAULT;
802
803 ret = hisi_qm_get_dfx_access(qm);
804 if (ret)
805 return ret;
806
807 spin_lock_irq(&file->lock);
808
809 switch (file->index) {
810 case SEC_CLEAR_ENABLE:
811 ret = sec_clear_enable_write(qm, val);
812 if (ret)
813 goto err_input;
814 break;
815 default:
816 ret = -EINVAL;
817 goto err_input;
818 }
819
820 ret = count;
821
822 err_input:
823 spin_unlock_irq(&file->lock);
824 hisi_qm_put_dfx_access(qm);
825 return ret;
826 }
827
828 static const struct file_operations sec_dbg_fops = {
829 .owner = THIS_MODULE,
830 .open = simple_open,
831 .read = sec_debug_read,
832 .write = sec_debug_write,
833 };
834
835 static int sec_debugfs_atomic64_get(void *data, u64 *val)
836 {
837 *val = atomic64_read((atomic64_t *)data);
838
839 return 0;
840 }
841
842 static int sec_debugfs_atomic64_set(void *data, u64 val)
843 {
844 if (val)
845 return -EINVAL;
846
847 atomic64_set((atomic64_t *)data, 0);
848
849 return 0;
850 }
851
852 DEFINE_DEBUGFS_ATTRIBUTE(sec_atomic64_ops, sec_debugfs_atomic64_get,
853 sec_debugfs_atomic64_set, "%lld\n");
854
855 static int sec_regs_show(struct seq_file *s, void *unused)
856 {
857 hisi_qm_regs_dump(s, s->private);
858
859 return 0;
860 }
861
862 DEFINE_SHOW_ATTRIBUTE(sec_regs);
863
864 static int sec_cap_regs_show(struct seq_file *s, void *unused)
865 {
866 struct hisi_qm *qm = s->private;
867 u32 i, size;
868
869 size = qm->cap_tables.qm_cap_size;
870 for (i = 0; i < size; i++)
871 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.qm_cap_table[i].name,
872 qm->cap_tables.qm_cap_table[i].cap_val);
873
874 size = qm->cap_tables.dev_cap_size;
875 for (i = 0; i < size; i++)
876 seq_printf(s, "%s= 0x%08x\n", qm->cap_tables.dev_cap_table[i].name,
877 qm->cap_tables.dev_cap_table[i].cap_val);
878
879 return 0;
880 }
881
882 DEFINE_SHOW_ATTRIBUTE(sec_cap_regs);
883
884 static int sec_core_debug_init(struct hisi_qm *qm)
885 {
886 struct dfx_diff_registers *sec_regs = qm->debug.acc_diff_regs;
887 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
888 struct device *dev = &qm->pdev->dev;
889 struct sec_dfx *dfx = &sec->debug.dfx;
890 struct debugfs_regset32 *regset;
891 struct dentry *tmp_d;
892 int i;
893
894 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root);
895
896 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
897 if (!regset)
898 return -ENOMEM;
899
900 regset->regs = sec_dfx_regs;
901 regset->nregs = ARRAY_SIZE(sec_dfx_regs);
902 regset->base = qm->io_base;
903 regset->dev = dev;
904
905 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF)
906 debugfs_create_file("regs", 0444, tmp_d, regset, &sec_regs_fops);
907 if (qm->fun_type == QM_HW_PF && sec_regs)
908 debugfs_create_file("diff_regs", 0444, tmp_d,
909 qm, &sec_diff_regs_fops);
910
911 for (i = 0; i < ARRAY_SIZE(sec_dfx_labels); i++) {
912 atomic64_t *data = (atomic64_t *)((uintptr_t)dfx +
913 sec_dfx_labels[i].offset);
914 debugfs_create_file(sec_dfx_labels[i].name, 0644,
915 tmp_d, data, &sec_atomic64_ops);
916 }
917
918 debugfs_create_file("cap_regs", CAP_FILE_PERMISSION,
919 qm->debug.debug_root, qm, &sec_cap_regs_fops);
920
921 return 0;
922 }
923
924 static int sec_debug_init(struct hisi_qm *qm)
925 {
926 struct sec_dev *sec = container_of(qm, struct sec_dev, qm);
927 int i;
928
929 if (qm->pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) {
930 for (i = SEC_CLEAR_ENABLE; i < SEC_DEBUG_FILE_NUM; i++) {
931 spin_lock_init(&sec->debug.files[i].lock);
932 sec->debug.files[i].index = i;
933 sec->debug.files[i].qm = qm;
934
935 debugfs_create_file(sec_dbg_file_name[i], 0600,
936 qm->debug.debug_root,
937 sec->debug.files + i,
938 &sec_dbg_fops);
939 }
940 }
941
942 return sec_core_debug_init(qm);
943 }
944
945 static int sec_debugfs_init(struct hisi_qm *qm)
946 {
947 struct device *dev = &qm->pdev->dev;
948 int ret;
949
950 ret = hisi_qm_regs_debugfs_init(qm, sec_diff_regs, ARRAY_SIZE(sec_diff_regs));
951 if (ret) {
952 dev_warn(dev, "Failed to init SEC diff regs!\n");
953 return ret;
954 }
955
956 qm->debug.debug_root = debugfs_create_dir(dev_name(dev),
957 sec_debugfs_root);
958 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET;
959 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN;
960
961 hisi_qm_debug_init(qm);
962
963 ret = sec_debug_init(qm);
964 if (ret)
965 goto debugfs_remove;
966
967 return 0;
968
969 debugfs_remove:
970 debugfs_remove_recursive(qm->debug.debug_root);
971 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs));
972 return ret;
973 }
974
975 static void sec_debugfs_exit(struct hisi_qm *qm)
976 {
977 debugfs_remove_recursive(qm->debug.debug_root);
978
979 hisi_qm_regs_debugfs_uninit(qm, ARRAY_SIZE(sec_diff_regs));
980 }
981
982 static int sec_show_last_regs_init(struct hisi_qm *qm)
983 {
984 struct qm_debug *debug = &qm->debug;
985 int i;
986
987 debug->last_words = kcalloc(ARRAY_SIZE(sec_dfx_regs),
988 sizeof(unsigned int), GFP_KERNEL);
989 if (!debug->last_words)
990 return -ENOMEM;
991
992 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++)
993 debug->last_words[i] = readl_relaxed(qm->io_base +
994 sec_dfx_regs[i].offset);
995
996 return 0;
997 }
998
999 static void sec_show_last_regs_uninit(struct hisi_qm *qm)
1000 {
1001 struct qm_debug *debug = &qm->debug;
1002
1003 if (qm->fun_type == QM_HW_VF || !debug->last_words)
1004 return;
1005
1006 kfree(debug->last_words);
1007 debug->last_words = NULL;
1008 }
1009
1010 static void sec_show_last_dfx_regs(struct hisi_qm *qm)
1011 {
1012 struct qm_debug *debug = &qm->debug;
1013 struct pci_dev *pdev = qm->pdev;
1014 u32 val;
1015 int i;
1016
1017 if (qm->fun_type == QM_HW_VF || !debug->last_words)
1018 return;
1019
1020 /* dumps last word of the debugging registers during controller reset */
1021 for (i = 0; i < ARRAY_SIZE(sec_dfx_regs); i++) {
1022 val = readl_relaxed(qm->io_base + sec_dfx_regs[i].offset);
1023 if (val != debug->last_words[i])
1024 pci_info(pdev, "%s \t= 0x%08x => 0x%08x\n",
1025 sec_dfx_regs[i].name, debug->last_words[i], val);
1026 }
1027 }
1028
1029 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts)
1030 {
1031 const struct sec_hw_error *errs = sec_hw_errors;
1032 struct device *dev = &qm->pdev->dev;
1033 u32 err_val;
1034
1035 while (errs->msg) {
1036 if (errs->int_msk & err_sts) {
1037 dev_err(dev, "%s [error status=0x%x] found\n",
1038 errs->msg, errs->int_msk);
1039
1040 if (SEC_CORE_INT_STATUS_M_ECC & errs->int_msk) {
1041 err_val = readl(qm->io_base +
1042 SEC_CORE_SRAM_ECC_ERR_INFO);
1043 dev_err(dev, "multi ecc sram num=0x%x\n",
1044 ((err_val) >> SEC_ECC_NUM) &
1045 SEC_ECC_MASH);
1046 }
1047 }
1048 errs++;
1049 }
1050 }
1051
1052 static u32 sec_get_hw_err_status(struct hisi_qm *qm)
1053 {
1054 return readl(qm->io_base + SEC_CORE_INT_STATUS);
1055 }
1056
1057 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
1058 {
1059 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE);
1060 }
1061
1062 static void sec_disable_error_report(struct hisi_qm *qm, u32 err_type)
1063 {
1064 u32 nfe_mask;
1065
1066 nfe_mask = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_NFE_MASK_CAP, qm->cap_ver);
1067 writel(nfe_mask & (~err_type), qm->io_base + SEC_RAS_NFE_REG);
1068 }
1069
1070 static void sec_open_axi_master_ooo(struct hisi_qm *qm)
1071 {
1072 u32 val;
1073
1074 val = readl(qm->io_base + SEC_CONTROL_REG);
1075 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG);
1076 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG);
1077 }
1078
1079 static enum acc_err_result sec_get_err_result(struct hisi_qm *qm)
1080 {
1081 u32 err_status;
1082
1083 err_status = sec_get_hw_err_status(qm);
1084 if (err_status) {
1085 if (err_status & qm->err_info.ecc_2bits_mask)
1086 qm->err_status.is_dev_ecc_mbit = true;
1087 sec_log_hw_error(qm, err_status);
1088
1089 if (err_status & qm->err_info.dev_reset_mask) {
1090 /* Disable the same error reporting until device is recovered. */
1091 sec_disable_error_report(qm, err_status);
1092 return ACC_ERR_NEED_RESET;
1093 }
1094 sec_clear_hw_err_status(qm, err_status);
1095 }
1096
1097 return ACC_ERR_RECOVERED;
1098 }
1099
1100 static void sec_err_info_init(struct hisi_qm *qm)
1101 {
1102 struct hisi_qm_err_info *err_info = &qm->err_info;
1103
1104 err_info->fe = SEC_RAS_FE_ENB_MSK;
1105 err_info->ce = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_CE_MASK_CAP, qm->cap_ver);
1106 err_info->nfe = hisi_qm_get_hw_info(qm, sec_basic_info, SEC_QM_NFE_MASK_CAP, qm->cap_ver);
1107 err_info->ecc_2bits_mask = SEC_CORE_INT_STATUS_M_ECC;
1108 err_info->qm_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1109 SEC_QM_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1110 err_info->dev_shutdown_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1111 SEC_OOO_SHUTDOWN_MASK_CAP, qm->cap_ver);
1112 err_info->qm_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1113 SEC_QM_RESET_MASK_CAP, qm->cap_ver);
1114 err_info->dev_reset_mask = hisi_qm_get_hw_info(qm, sec_basic_info,
1115 SEC_RESET_MASK_CAP, qm->cap_ver);
1116 err_info->msi_wr_port = BIT(0);
1117 err_info->acpi_rst = "SRST";
1118 }
1119
1120 static const struct hisi_qm_err_ini sec_err_ini = {
1121 .hw_init = sec_set_user_domain_and_cache,
1122 .hw_err_enable = sec_hw_error_enable,
1123 .hw_err_disable = sec_hw_error_disable,
1124 .get_dev_hw_err_status = sec_get_hw_err_status,
1125 .clear_dev_hw_err_status = sec_clear_hw_err_status,
1126 .open_axi_master_ooo = sec_open_axi_master_ooo,
1127 .open_sva_prefetch = sec_open_sva_prefetch,
1128 .close_sva_prefetch = sec_close_sva_prefetch,
1129 .show_last_dfx_regs = sec_show_last_dfx_regs,
1130 .err_info_init = sec_err_info_init,
1131 .get_err_result = sec_get_err_result,
1132 };
1133
1134 static int sec_pf_probe_init(struct sec_dev *sec)
1135 {
1136 struct hisi_qm *qm = &sec->qm;
1137 int ret;
1138
1139 ret = sec_set_user_domain_and_cache(qm);
1140 if (ret)
1141 return ret;
1142
1143 sec_open_sva_prefetch(qm);
1144 hisi_qm_dev_err_init(qm);
1145 sec_debug_regs_clear(qm);
1146 ret = sec_show_last_regs_init(qm);
1147 if (ret)
1148 pci_err(qm->pdev, "Failed to init last word regs!\n");
1149
1150 return ret;
1151 }
1152
1153 static int sec_pre_store_cap_reg(struct hisi_qm *qm)
1154 {
1155 struct hisi_qm_cap_record *sec_cap;
1156 struct pci_dev *pdev = qm->pdev;
1157 size_t i, size;
1158
1159 size = ARRAY_SIZE(sec_cap_query_info);
1160 sec_cap = devm_kzalloc(&pdev->dev, sizeof(*sec_cap) * size, GFP_KERNEL);
1161 if (!sec_cap)
1162 return -ENOMEM;
1163
1164 for (i = 0; i < size; i++) {
1165 sec_cap[i].type = sec_cap_query_info[i].type;
1166 sec_cap[i].name = sec_cap_query_info[i].name;
1167 sec_cap[i].cap_val = hisi_qm_get_cap_value(qm, sec_cap_query_info,
1168 i, qm->cap_ver);
1169 }
1170
1171 qm->cap_tables.dev_cap_table = sec_cap;
1172 qm->cap_tables.dev_cap_size = size;
1173
1174 return 0;
1175 }
1176
1177 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
1178 {
1179 u64 alg_msk;
1180 int ret;
1181
1182 qm->pdev = pdev;
1183 qm->ver = pdev->revision;
1184 qm->mode = uacce_mode;
1185 qm->sqe_size = SEC_SQE_SIZE;
1186 qm->dev_name = sec_name;
1187
1188 qm->fun_type = (pdev->device == PCI_DEVICE_ID_HUAWEI_SEC_PF) ?
1189 QM_HW_PF : QM_HW_VF;
1190 if (qm->fun_type == QM_HW_PF) {
1191 qm->qp_base = SEC_PF_DEF_Q_BASE;
1192 qm->qp_num = pf_q_num;
1193 qm->debug.curr_qm_qp_num = pf_q_num;
1194 qm->qm_list = &sec_devices;
1195 qm->err_ini = &sec_err_ini;
1196 if (pf_q_num_flag)
1197 set_bit(QM_MODULE_PARAM, &qm->misc_ctl);
1198 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
1199 /*
1200 * have no way to get qm configure in VM in v1 hardware,
1201 * so currently force PF to uses SEC_PF_DEF_Q_NUM, and force
1202 * to trigger only one VF in v1 hardware.
1203 * v2 hardware has no such problem.
1204 */
1205 qm->qp_base = SEC_PF_DEF_Q_NUM;
1206 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM;
1207 }
1208
1209 ret = hisi_qm_init(qm);
1210 if (ret) {
1211 pci_err(qm->pdev, "Failed to init sec qm configures!\n");
1212 return ret;
1213 }
1214
1215 /* Fetch and save the value of capability registers */
1216 ret = sec_pre_store_cap_reg(qm);
1217 if (ret) {
1218 pci_err(qm->pdev, "Failed to pre-store capability registers!\n");
1219 hisi_qm_uninit(qm);
1220 return ret;
1221 }
1222 alg_msk = sec_get_alg_bitmap(qm, SEC_ALG_BITMAP_HIGH, SEC_ALG_BITMAP_LOW);
1223 ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs));
1224 if (ret) {
1225 pci_err(qm->pdev, "Failed to set sec algs!\n");
1226 hisi_qm_uninit(qm);
1227 }
1228
1229 return ret;
1230 }
1231
1232 static void sec_qm_uninit(struct hisi_qm *qm)
1233 {
1234 hisi_qm_uninit(qm);
1235 }
1236
1237 static int sec_probe_init(struct sec_dev *sec)
1238 {
1239 u32 type_rate = SEC_SHAPER_TYPE_RATE;
1240 struct hisi_qm *qm = &sec->qm;
1241 int ret;
1242
1243 if (qm->fun_type == QM_HW_PF) {
1244 ret = sec_pf_probe_init(sec);
1245 if (ret)
1246 return ret;
1247 /* enable shaper type 0 */
1248 if (qm->ver >= QM_HW_V3) {
1249 type_rate |= QM_SHAPER_ENABLE;
1250 qm->type_rate = type_rate;
1251 }
1252 }
1253
1254 return 0;
1255 }
1256
1257 static void sec_probe_uninit(struct hisi_qm *qm)
1258 {
1259 if (qm->fun_type == QM_HW_VF)
1260 return;
1261
1262 sec_debug_regs_clear(qm);
1263 sec_show_last_regs_uninit(qm);
1264 sec_close_sva_prefetch(qm);
1265 hisi_qm_dev_err_uninit(qm);
1266 }
1267
1268 static void sec_iommu_used_check(struct sec_dev *sec)
1269 {
1270 struct iommu_domain *domain;
1271 struct device *dev = &sec->qm.pdev->dev;
1272
1273 domain = iommu_get_domain_for_dev(dev);
1274
1275 /* Check if iommu is used */
1276 sec->iommu_used = false;
1277 if (domain) {
1278 if (domain->type & __IOMMU_DOMAIN_PAGING)
1279 sec->iommu_used = true;
1280 dev_info(dev, "SMMU Opened, the iommu type = %u\n",
1281 domain->type);
1282 }
1283 }
1284
1285 static int sec_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1286 {
1287 struct sec_dev *sec;
1288 struct hisi_qm *qm;
1289 int ret;
1290
1291 sec = devm_kzalloc(&pdev->dev, sizeof(*sec), GFP_KERNEL);
1292 if (!sec)
1293 return -ENOMEM;
1294
1295 qm = &sec->qm;
1296 ret = sec_qm_init(qm, pdev);
1297 if (ret) {
1298 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret);
1299 return ret;
1300 }
1301
1302 sec->ctx_q_num = ctx_q_num;
1303 sec_iommu_used_check(sec);
1304
1305 ret = sec_probe_init(sec);
1306 if (ret) {
1307 pci_err(pdev, "Failed to probe!\n");
1308 goto err_qm_uninit;
1309 }
1310
1311 ret = hisi_qm_start(qm);
1312 if (ret) {
1313 pci_err(pdev, "Failed to start sec qm!\n");
1314 goto err_probe_uninit;
1315 }
1316
1317 ret = sec_debugfs_init(qm);
1318 if (ret)
1319 pci_warn(pdev, "Failed to init debugfs!\n");
1320
1321 hisi_qm_add_list(qm, &sec_devices);
1322 ret = hisi_qm_alg_register(qm, &sec_devices, ctx_q_num);
1323 if (ret < 0) {
1324 pr_err("Failed to register driver to crypto.\n");
1325 goto err_qm_del_list;
1326 }
1327
1328 if (qm->uacce) {
1329 ret = uacce_register(qm->uacce);
1330 if (ret) {
1331 pci_err(pdev, "failed to register uacce (%d)!\n", ret);
1332 goto err_alg_unregister;
1333 }
1334 }
1335
1336 if (qm->fun_type == QM_HW_PF && vfs_num) {
1337 ret = hisi_qm_sriov_enable(pdev, vfs_num);
1338 if (ret < 0)
1339 goto err_alg_unregister;
1340 }
1341
1342 hisi_qm_pm_init(qm);
1343
1344 return 0;
1345
1346 err_alg_unregister:
1347 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num);
1348 err_qm_del_list:
1349 hisi_qm_del_list(qm, &sec_devices);
1350 sec_debugfs_exit(qm);
1351 hisi_qm_stop(qm, QM_NORMAL);
1352 err_probe_uninit:
1353 sec_probe_uninit(qm);
1354 err_qm_uninit:
1355 sec_qm_uninit(qm);
1356 return ret;
1357 }
1358
1359 static void sec_remove(struct pci_dev *pdev)
1360 {
1361 struct hisi_qm *qm = pci_get_drvdata(pdev);
1362
1363 hisi_qm_pm_uninit(qm);
1364 hisi_qm_wait_task_finish(qm, &sec_devices);
1365 hisi_qm_alg_unregister(qm, &sec_devices, ctx_q_num);
1366 hisi_qm_del_list(qm, &sec_devices);
1367
1368 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
1369 hisi_qm_sriov_disable(pdev, true);
1370
1371 sec_debugfs_exit(qm);
1372
1373 (void)hisi_qm_stop(qm, QM_NORMAL);
1374 sec_probe_uninit(qm);
1375
1376 sec_qm_uninit(qm);
1377 }
1378
1379 static const struct dev_pm_ops sec_pm_ops = {
1380 SET_RUNTIME_PM_OPS(hisi_qm_suspend, hisi_qm_resume, NULL)
1381 };
1382
1383 static const struct pci_error_handlers sec_err_handler = {
1384 .error_detected = hisi_qm_dev_err_detected,
1385 .slot_reset = hisi_qm_dev_slot_reset,
1386 .reset_prepare = hisi_qm_reset_prepare,
1387 .reset_done = hisi_qm_reset_done,
1388 };
1389
1390 static struct pci_driver sec_pci_driver = {
1391 .name = "hisi_sec2",
1392 .id_table = sec_dev_ids,
1393 .probe = sec_probe,
1394 .remove = sec_remove,
1395 .err_handler = &sec_err_handler,
1396 .sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ?
1397 hisi_qm_sriov_configure : NULL,
1398 .shutdown = hisi_qm_dev_shutdown,
1399 .driver.pm = &sec_pm_ops,
1400 };
1401
1402 struct pci_driver *hisi_sec_get_pf_driver(void)
1403 {
1404 return &sec_pci_driver;
1405 }
1406 EXPORT_SYMBOL_GPL(hisi_sec_get_pf_driver);
1407
1408 static void sec_register_debugfs(void)
1409 {
1410 if (!debugfs_initialized())
1411 return;
1412
1413 sec_debugfs_root = debugfs_create_dir("hisi_sec2", NULL);
1414 }
1415
1416 static void sec_unregister_debugfs(void)
1417 {
1418 debugfs_remove_recursive(sec_debugfs_root);
1419 }
1420
1421 static int __init sec_init(void)
1422 {
1423 int ret;
1424
1425 hisi_qm_init_list(&sec_devices);
1426 sec_register_debugfs();
1427
1428 ret = pci_register_driver(&sec_pci_driver);
1429 if (ret < 0) {
1430 sec_unregister_debugfs();
1431 pr_err("Failed to register pci driver.\n");
1432 return ret;
1433 }
1434
1435 return 0;
1436 }
1437
1438 static void __exit sec_exit(void)
1439 {
1440 pci_unregister_driver(&sec_pci_driver);
1441 sec_unregister_debugfs();
1442 }
1443
1444 module_init(sec_init);
1445 module_exit(sec_exit);
1446
1447 MODULE_LICENSE("GPL v2");
1448 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>");
1449 MODULE_AUTHOR("Longfang Liu <liulongfang@huawei.com>");
1450 MODULE_AUTHOR("Kai Ye <yekai13@huawei.com>");
1451 MODULE_AUTHOR("Wei Zhang <zhangwei375@huawei.com>");
1452 MODULE_DESCRIPTION("Driver for HiSilicon SEC accelerator");
Linux Kernel