drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c

   1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
   2 /* Copyright(c) 2014 - 2021 Intel Corporation */
   3 #include <adf_accel_devices.h>
   4 #include <adf_admin.h>
   5 #include <adf_clock.h>
   6 #include <adf_common_drv.h>
   7 #include <adf_gen2_config.h>
   8 #include <adf_gen2_dc.h>
   9 #include <adf_gen2_hw_csr_data.h>
  10 #include <adf_gen2_hw_data.h>
  11 #include <adf_gen2_pfvf.h>
  12 #include "adf_c62x_hw_data.h"
  13 #include "adf_heartbeat.h"
  14 #include "icp_qat_hw.h"
  15
  16 /* Worker thread to service arbiter mappings */
  17 static const u32 thrd_to_arb_map[ADF_C62X_MAX_ACCELENGINES] = {
  18         0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
  19         0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
  20 };
  21
  22 static struct adf_hw_device_class c62x_class = {
  23         .name = ADF_C62X_DEVICE_NAME,
  24         .type = DEV_C62X,
  25         .instances = 0
  26 };
  27
  28 static u32 get_accel_mask(struct adf_hw_device_data *self)
  29 {
  30         u32 straps = self->straps;
  31         u32 fuses = self->fuses;
  32         u32 accel;
  33
  34         accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET;
  35         accel &= ADF_C62X_ACCELERATORS_MASK;
  36
  37         return accel;
  38 }
  39
  40 static u32 get_ae_mask(struct adf_hw_device_data *self)
  41 {
  42         u32 straps = self->straps;
  43         u32 fuses = self->fuses;
  44         unsigned long disabled;
  45         u32 ae_disable;
  46         int accel;
  47
  48         /* If an accel is disabled, then disable the corresponding two AEs */
  49         disabled = ~get_accel_mask(self) & ADF_C62X_ACCELERATORS_MASK;
  50         ae_disable = BIT(1) | BIT(0);
  51         for_each_set_bit(accel, &disabled, ADF_C62X_MAX_ACCELERATORS)
  52                 straps |= ae_disable << (accel << 1);
  53
  54         return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK;
  55 }
  56
  57 static u32 get_ts_clock(struct adf_hw_device_data *self)
  58 {
  59         /*
  60          * Timestamp update interval is 16 AE clock ticks for c62x.
  61          */
  62         return self->clock_frequency / 16;
  63 }
  64
  65 static int measure_clock(struct adf_accel_dev *accel_dev)
  66 {
  67         u32 frequency;
  68         int ret;
  69
  70         ret = adf_dev_measure_clock(accel_dev, &frequency, ADF_C62X_MIN_AE_FREQ,
  71                                     ADF_C62X_MAX_AE_FREQ);
  72         if (ret)
  73                 return ret;
  74
  75         accel_dev->hw_device->clock_frequency = frequency;
  76         return 0;
  77 }
  78
  79 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
  80 {
  81         return ADF_C62X_PMISC_BAR;
  82 }
  83
  84 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
  85 {
  86         return ADF_C62X_ETR_BAR;
  87 }
  88
  89 static u32 get_sram_bar_id(struct adf_hw_device_data *self)
  90 {
  91         return ADF_C62X_SRAM_BAR;
  92 }
  93
  94 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
  95 {
  96         int aes = self->get_num_aes(self);
  97
  98         if (aes == 8)
  99                 return DEV_SKU_2;
 100         else if (aes == 10)
 101                 return DEV_SKU_4;
 102
 103         return DEV_SKU_UNKNOWN;
 104 }
 105
 106 static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)
 107 {
 108         return thrd_to_arb_map;
 109 }
 110
 111 static void configure_iov_threads(struct adf_accel_dev *accel_dev, bool enable)
 112 {
 113         adf_gen2_cfg_iov_thds(accel_dev, enable,
 114                               ADF_C62X_AE2FUNC_MAP_GRP_A_NUM_REGS,
 115                               ADF_C62X_AE2FUNC_MAP_GRP_B_NUM_REGS);
 116 }
 117
 118 void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
 119 {
 120         hw_data->dev_class = &c62x_class;
 121         hw_data->instance_id = c62x_class.instances++;
 122         hw_data->num_banks = ADF_C62X_ETR_MAX_BANKS;
 123         hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
 124         hw_data->num_accel = ADF_C62X_MAX_ACCELERATORS;
 125         hw_data->num_logical_accel = 1;
 126         hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES;
 127         hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
 128         hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
 129         hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
 130         hw_data->alloc_irq = adf_isr_resource_alloc;
 131         hw_data->free_irq = adf_isr_resource_free;
 132         hw_data->enable_error_correction = adf_gen2_enable_error_correction;
 133         hw_data->get_accel_mask = get_accel_mask;
 134         hw_data->get_ae_mask = get_ae_mask;
 135         hw_data->get_accel_cap = adf_gen2_get_accel_cap;
 136         hw_data->get_num_accels = adf_gen2_get_num_accels;
 137         hw_data->get_num_aes = adf_gen2_get_num_aes;
 138         hw_data->get_sram_bar_id = get_sram_bar_id;
 139         hw_data->get_etr_bar_id = get_etr_bar_id;
 140         hw_data->get_misc_bar_id = get_misc_bar_id;
 141         hw_data->get_admin_info = adf_gen2_get_admin_info;
 142         hw_data->get_arb_info = adf_gen2_get_arb_info;
 143         hw_data->get_sku = get_sku;
 144         hw_data->fw_name = ADF_C62X_FW;
 145         hw_data->fw_mmp_name = ADF_C62X_MMP;
 146         hw_data->init_admin_comms = adf_init_admin_comms;
 147         hw_data->exit_admin_comms = adf_exit_admin_comms;
 148         hw_data->configure_iov_threads = configure_iov_threads;
 149         hw_data->send_admin_init = adf_send_admin_init;
 150         hw_data->init_arb = adf_init_arb;
 151         hw_data->exit_arb = adf_exit_arb;
 152         hw_data->get_arb_mapping = adf_get_arbiter_mapping;
 153         hw_data->enable_ints = adf_gen2_enable_ints;
 154         hw_data->reset_device = adf_reset_flr;
 155         hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
 156         hw_data->disable_iov = adf_disable_sriov;
 157         hw_data->dev_config = adf_gen2_dev_config;
 158         hw_data->measure_clock = measure_clock;
 159         hw_data->get_hb_clock = get_ts_clock;
 160         hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;
 161         hw_data->check_hb_ctrs = adf_heartbeat_check_ctrs;
 162
 163         adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
 164         adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
 165         adf_gen2_init_dc_ops(&hw_data->dc_ops);
 166 }
 167
 168 void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data)
 169 {
 170         hw_data->dev_class->instances--;
 171 }