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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux.git] / drivers / iio / adc / ad7124.c
blob7314fb32bdecb407f234d6553c54117133c981f7
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/kfifo.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/property.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spi/spi.h>
21
22 #include <linux/iio/iio.h>
23 #include <linux/iio/adc/ad_sigma_delta.h>
24 #include <linux/iio/sysfs.h>
25
26 /* AD7124 registers */
27 #define AD7124_COMMS 0x00
28 #define AD7124_STATUS 0x00
29 #define AD7124_ADC_CONTROL 0x01
30 #define AD7124_DATA 0x02
31 #define AD7124_IO_CONTROL_1 0x03
32 #define AD7124_IO_CONTROL_2 0x04
33 #define AD7124_ID 0x05
34 #define AD7124_ERROR 0x06
35 #define AD7124_ERROR_EN 0x07
36 #define AD7124_MCLK_COUNT 0x08
37 #define AD7124_CHANNEL(x) (0x09 + (x))
38 #define AD7124_CONFIG(x) (0x19 + (x))
39 #define AD7124_FILTER(x) (0x21 + (x))
40 #define AD7124_OFFSET(x) (0x29 + (x))
41 #define AD7124_GAIN(x) (0x31 + (x))
42
43 /* AD7124_STATUS */
44 #define AD7124_STATUS_POR_FLAG_MSK BIT(4)
45
46 /* AD7124_ADC_CONTROL */
47 #define AD7124_ADC_STATUS_EN_MSK BIT(10)
48 #define AD7124_ADC_STATUS_EN(x) FIELD_PREP(AD7124_ADC_STATUS_EN_MSK, x)
49 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8)
50 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
51 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
52 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
53 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2)
54 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
55
56 /* AD7124 ID */
57 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4)
58 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x)
59 #define AD7124_SILICON_REV_MSK GENMASK(3, 0)
60 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x)
61
62 #define CHIPID_AD7124_4 0x0
63 #define CHIPID_AD7124_8 0x1
64
65 /* AD7124_CHANNEL_X */
66 #define AD7124_CHANNEL_EN_MSK BIT(15)
67 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
68 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12)
69 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
70 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
71 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
72 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
73 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
74
75 /* AD7124_CONFIG_X */
76 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11)
77 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
78 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3)
79 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
80 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0)
81 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
82 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5)
83 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
84
85 /* AD7124_FILTER_X */
86 #define AD7124_FILTER_FS_MSK GENMASK(10, 0)
87 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x)
88 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21)
89 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
90
91 #define AD7124_SINC3_FILTER 2
92 #define AD7124_SINC4_FILTER 0
93
94 #define AD7124_CONF_ADDR_OFFSET 20
95 #define AD7124_MAX_CONFIGS 8
96 #define AD7124_MAX_CHANNELS 16
97
98 enum ad7124_ids {
99 ID_AD7124_4,
100 ID_AD7124_8,
101 };
102
103 enum ad7124_ref_sel {
104 AD7124_REFIN1,
105 AD7124_REFIN2,
106 AD7124_INT_REF,
107 AD7124_AVDD_REF,
108 };
109
110 enum ad7124_power_mode {
111 AD7124_LOW_POWER,
112 AD7124_MID_POWER,
113 AD7124_FULL_POWER,
114 };
115
116 static const unsigned int ad7124_gain[8] = {
117 1, 2, 4, 8, 16, 32, 64, 128
118 };
119
120 static const unsigned int ad7124_reg_size[] = {
121 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
122 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
123 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
124 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
125 3, 3, 3, 3, 3
126 };
127
128 static const int ad7124_master_clk_freq_hz[3] = {
129 [AD7124_LOW_POWER] = 76800,
130 [AD7124_MID_POWER] = 153600,
131 [AD7124_FULL_POWER] = 614400,
132 };
133
134 static const char * const ad7124_ref_names[] = {
135 [AD7124_REFIN1] = "refin1",
136 [AD7124_REFIN2] = "refin2",
137 [AD7124_INT_REF] = "int",
138 [AD7124_AVDD_REF] = "avdd",
139 };
140
141 struct ad7124_chip_info {
142 const char *name;
143 unsigned int chip_id;
144 unsigned int num_inputs;
145 };
146
147 struct ad7124_channel_config {
148 bool live;
149 unsigned int cfg_slot;
150 /* Following fields are used to compare equality. */
151 struct_group(config_props,
152 enum ad7124_ref_sel refsel;
153 bool bipolar;
154 bool buf_positive;
155 bool buf_negative;
156 unsigned int vref_mv;
157 unsigned int pga_bits;
158 unsigned int odr;
159 unsigned int odr_sel_bits;
160 unsigned int filter_type;
161 );
162 };
163
164 struct ad7124_channel {
165 unsigned int nr;
166 struct ad7124_channel_config cfg;
167 unsigned int ain;
168 unsigned int slot;
169 };
170
171 struct ad7124_state {
172 const struct ad7124_chip_info *chip_info;
173 struct ad_sigma_delta sd;
174 struct ad7124_channel *channels;
175 struct regulator *vref[4];
176 struct clk *mclk;
177 unsigned int adc_control;
178 unsigned int num_channels;
179 struct mutex cfgs_lock; /* lock for configs access */
180 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
181 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
182 };
183
184 static const struct iio_chan_spec ad7124_channel_template = {
185 .type = IIO_VOLTAGE,
186 .indexed = 1,
187 .differential = 1,
188 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
189 BIT(IIO_CHAN_INFO_SCALE) |
190 BIT(IIO_CHAN_INFO_OFFSET) |
191 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
192 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
193 .scan_type = {
194 .sign = 'u',
195 .realbits = 24,
196 .storagebits = 32,
197 .endianness = IIO_BE,
198 },
199 };
200
201 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
202 [ID_AD7124_4] = {
203 .name = "ad7124-4",
204 .chip_id = CHIPID_AD7124_4,
205 .num_inputs = 8,
206 },
207 [ID_AD7124_8] = {
208 .name = "ad7124-8",
209 .chip_id = CHIPID_AD7124_8,
210 .num_inputs = 16,
211 },
212 };
213
214 static int ad7124_find_closest_match(const int *array,
215 unsigned int size, int val)
216 {
217 int i, idx;
218 unsigned int diff_new, diff_old;
219
220 diff_old = U32_MAX;
221 idx = 0;
222
223 for (i = 0; i < size; i++) {
224 diff_new = abs(val - array[i]);
225 if (diff_new < diff_old) {
226 diff_old = diff_new;
227 idx = i;
228 }
229 }
230
231 return idx;
232 }
233
234 static int ad7124_spi_write_mask(struct ad7124_state *st,
235 unsigned int addr,
236 unsigned long mask,
237 unsigned int val,
238 unsigned int bytes)
239 {
240 unsigned int readval;
241 int ret;
242
243 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
244 if (ret < 0)
245 return ret;
246
247 readval &= ~mask;
248 readval |= val;
249
250 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
251 }
252
253 static int ad7124_set_mode(struct ad_sigma_delta *sd,
254 enum ad_sigma_delta_mode mode)
255 {
256 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
257
258 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
259 st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
260
261 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
262 }
263
264 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
265 {
266 unsigned int fclk, odr_sel_bits;
267
268 fclk = clk_get_rate(st->mclk);
269 /*
270 * FS[10:0] = fCLK / (fADC x 32) where:
271 * fADC is the output data rate
272 * fCLK is the master clock frequency
273 * FS[10:0] are the bits in the filter register
274 * FS[10:0] can have a value from 1 to 2047
275 */
276 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
277 if (odr_sel_bits < 1)
278 odr_sel_bits = 1;
279 else if (odr_sel_bits > 2047)
280 odr_sel_bits = 2047;
281
282 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
283 st->channels[channel].cfg.live = false;
284
285 /* fADC = fCLK / (FS[10:0] x 32) */
286 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
287 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
288 }
289
290 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
291 unsigned int channel)
292 {
293 unsigned int fadc;
294
295 fadc = st->channels[channel].cfg.odr;
296
297 switch (st->channels[channel].cfg.filter_type) {
298 case AD7124_SINC3_FILTER:
299 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
300 case AD7124_SINC4_FILTER:
301 return DIV_ROUND_CLOSEST(fadc * 262, 1000);
302 default:
303 return -EINVAL;
304 }
305 }
306
307 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
308 unsigned int freq)
309 {
310 unsigned int sinc4_3db_odr;
311 unsigned int sinc3_3db_odr;
312 unsigned int new_filter;
313 unsigned int new_odr;
314
315 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
316 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
317
318 if (sinc4_3db_odr > sinc3_3db_odr) {
319 new_filter = AD7124_SINC3_FILTER;
320 new_odr = sinc4_3db_odr;
321 } else {
322 new_filter = AD7124_SINC4_FILTER;
323 new_odr = sinc3_3db_odr;
324 }
325
326 if (new_odr != st->channels[channel].cfg.odr)
327 st->channels[channel].cfg.live = false;
328
329 st->channels[channel].cfg.filter_type = new_filter;
330 st->channels[channel].cfg.odr = new_odr;
331 }
332
333 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
334 struct ad7124_channel_config *cfg)
335 {
336 struct ad7124_channel_config *cfg_aux;
337 ptrdiff_t cmp_size;
338 int i;
339
340 cmp_size = sizeof_field(struct ad7124_channel_config, config_props);
341 for (i = 0; i < st->num_channels; i++) {
342 cfg_aux = &st->channels[i].cfg;
343
344 if (cfg_aux->live &&
345 !memcmp(&cfg->config_props, &cfg_aux->config_props, cmp_size))
346 return cfg_aux;
347 }
348
349 return NULL;
350 }
351
352 static int ad7124_find_free_config_slot(struct ad7124_state *st)
353 {
354 unsigned int free_cfg_slot;
355
356 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS);
357 if (free_cfg_slot == AD7124_MAX_CONFIGS)
358 return -1;
359
360 return free_cfg_slot;
361 }
362
363 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
364 {
365 unsigned int refsel = cfg->refsel;
366
367 switch (refsel) {
368 case AD7124_REFIN1:
369 case AD7124_REFIN2:
370 case AD7124_AVDD_REF:
371 if (IS_ERR(st->vref[refsel])) {
372 dev_err(&st->sd.spi->dev,
373 "Error, trying to use external voltage reference without a %s regulator.\n",
374 ad7124_ref_names[refsel]);
375 return PTR_ERR(st->vref[refsel]);
376 }
377 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
378 /* Conversion from uV to mV */
379 cfg->vref_mv /= 1000;
380 return 0;
381 case AD7124_INT_REF:
382 cfg->vref_mv = 2500;
383 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
384 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
385 return 0;
386 default:
387 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
388 return -EINVAL;
389 }
390 }
391
392 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
393 unsigned int cfg_slot)
394 {
395 unsigned int tmp;
396 unsigned int val;
397 int ret;
398
399 cfg->cfg_slot = cfg_slot;
400
401 tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
402 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
403 AD7124_CONFIG_IN_BUFF(tmp) | AD7124_CONFIG_PGA(cfg->pga_bits);
404
405 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
406 if (ret < 0)
407 return ret;
408
409 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type) |
410 AD7124_FILTER_FS(cfg->odr_sel_bits);
411 return ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot),
412 AD7124_FILTER_TYPE_MSK | AD7124_FILTER_FS_MSK,
413 tmp, 3);
414 }
415
416 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
417 {
418 struct ad7124_channel_config *lru_cfg;
419 struct ad7124_channel_config *cfg;
420 int ret;
421 int i;
422
423 /*
424 * Pop least recently used config from the fifo
425 * in order to make room for the new one
426 */
427 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
428 if (ret <= 0)
429 return NULL;
430
431 lru_cfg->live = false;
432
433 /* mark slot as free */
434 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
435
436 /* invalidate all other configs that pointed to this one */
437 for (i = 0; i < st->num_channels; i++) {
438 cfg = &st->channels[i].cfg;
439
440 if (cfg->cfg_slot == lru_cfg->cfg_slot)
441 cfg->live = false;
442 }
443
444 return lru_cfg;
445 }
446
447 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
448 {
449 struct ad7124_channel_config *lru_cfg;
450 int free_cfg_slot;
451
452 free_cfg_slot = ad7124_find_free_config_slot(st);
453 if (free_cfg_slot >= 0) {
454 /* push the new config in configs queue */
455 kfifo_put(&st->live_cfgs_fifo, cfg);
456 } else {
457 /* pop one config to make room for the new one */
458 lru_cfg = ad7124_pop_config(st);
459 if (!lru_cfg)
460 return -EINVAL;
461
462 /* push the new config in configs queue */
463 free_cfg_slot = lru_cfg->cfg_slot;
464 kfifo_put(&st->live_cfgs_fifo, cfg);
465 }
466
467 /* mark slot as used */
468 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
469
470 return ad7124_write_config(st, cfg, free_cfg_slot);
471 }
472
473 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
474 {
475 ch->cfg.live = true;
476 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
477 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
478 }
479
480 static int ad7124_prepare_read(struct ad7124_state *st, int address)
481 {
482 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
483 struct ad7124_channel_config *live_cfg;
484
485 /*
486 * Before doing any reads assign the channel a configuration.
487 * Check if channel's config is on the device
488 */
489 if (!cfg->live) {
490 /* check if config matches another one */
491 live_cfg = ad7124_find_similar_live_cfg(st, cfg);
492 if (!live_cfg)
493 ad7124_push_config(st, cfg);
494 else
495 cfg->cfg_slot = live_cfg->cfg_slot;
496 }
497
498 /* point channel to the config slot and enable */
499 return ad7124_enable_channel(st, &st->channels[address]);
500 }
501
502 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
503 {
504 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
505
506 return ad7124_prepare_read(st, channel);
507 }
508
509 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
510 {
511 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
512 int ret;
513
514 mutex_lock(&st->cfgs_lock);
515 ret = __ad7124_set_channel(sd, channel);
516 mutex_unlock(&st->cfgs_lock);
517
518 return ret;
519 }
520
521 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append)
522 {
523 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
524 unsigned int adc_control = st->adc_control;
525 int ret;
526
527 adc_control &= ~AD7124_ADC_STATUS_EN_MSK;
528 adc_control |= AD7124_ADC_STATUS_EN(append);
529
530 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
531 if (ret < 0)
532 return ret;
533
534 st->adc_control = adc_control;
535
536 return 0;
537 }
538
539 static int ad7124_disable_all(struct ad_sigma_delta *sd)
540 {
541 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
542 int ret;
543 int i;
544
545 for (i = 0; i < st->num_channels; i++) {
546 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 0, 2);
547 if (ret < 0)
548 return ret;
549 }
550
551 return 0;
552 }
553
554 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
555 {
556 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
557
558 return ad7124_spi_write_mask(st, AD7124_CHANNEL(chan), AD7124_CHANNEL_EN_MSK, 0, 2);
559 }
560
561 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
562 .set_channel = ad7124_set_channel,
563 .append_status = ad7124_append_status,
564 .disable_all = ad7124_disable_all,
565 .disable_one = ad7124_disable_one,
566 .set_mode = ad7124_set_mode,
567 .has_registers = true,
568 .addr_shift = 0,
569 .read_mask = BIT(6),
570 .status_ch_mask = GENMASK(3, 0),
571 .data_reg = AD7124_DATA,
572 .num_slots = 8,
573 .irq_flags = IRQF_TRIGGER_FALLING,
574 };
575
576 static int ad7124_read_raw(struct iio_dev *indio_dev,
577 struct iio_chan_spec const *chan,
578 int *val, int *val2, long info)
579 {
580 struct ad7124_state *st = iio_priv(indio_dev);
581 int idx, ret;
582
583 switch (info) {
584 case IIO_CHAN_INFO_RAW:
585 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
586 if (ret < 0)
587 return ret;
588
589 return IIO_VAL_INT;
590 case IIO_CHAN_INFO_SCALE:
591 mutex_lock(&st->cfgs_lock);
592
593 idx = st->channels[chan->address].cfg.pga_bits;
594 *val = st->channels[chan->address].cfg.vref_mv;
595 if (st->channels[chan->address].cfg.bipolar)
596 *val2 = chan->scan_type.realbits - 1 + idx;
597 else
598 *val2 = chan->scan_type.realbits + idx;
599
600 mutex_unlock(&st->cfgs_lock);
601 return IIO_VAL_FRACTIONAL_LOG2;
602 case IIO_CHAN_INFO_OFFSET:
603 mutex_lock(&st->cfgs_lock);
604 if (st->channels[chan->address].cfg.bipolar)
605 *val = -(1 << (chan->scan_type.realbits - 1));
606 else
607 *val = 0;
608
609 mutex_unlock(&st->cfgs_lock);
610 return IIO_VAL_INT;
611 case IIO_CHAN_INFO_SAMP_FREQ:
612 mutex_lock(&st->cfgs_lock);
613 *val = st->channels[chan->address].cfg.odr;
614 mutex_unlock(&st->cfgs_lock);
615
616 return IIO_VAL_INT;
617 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
618 mutex_lock(&st->cfgs_lock);
619 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
620 mutex_unlock(&st->cfgs_lock);
621
622 return IIO_VAL_INT;
623 default:
624 return -EINVAL;
625 }
626 }
627
628 static int ad7124_write_raw(struct iio_dev *indio_dev,
629 struct iio_chan_spec const *chan,
630 int val, int val2, long info)
631 {
632 struct ad7124_state *st = iio_priv(indio_dev);
633 unsigned int res, gain, full_scale, vref;
634 int ret = 0;
635
636 mutex_lock(&st->cfgs_lock);
637
638 switch (info) {
639 case IIO_CHAN_INFO_SAMP_FREQ:
640 if (val2 != 0 || val == 0) {
641 ret = -EINVAL;
642 break;
643 }
644
645 ad7124_set_channel_odr(st, chan->address, val);
646 break;
647 case IIO_CHAN_INFO_SCALE:
648 if (val != 0) {
649 ret = -EINVAL;
650 break;
651 }
652
653 if (st->channels[chan->address].cfg.bipolar)
654 full_scale = 1 << (chan->scan_type.realbits - 1);
655 else
656 full_scale = 1 << chan->scan_type.realbits;
657
658 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
659 res = DIV_ROUND_CLOSEST(vref, full_scale);
660 gain = DIV_ROUND_CLOSEST(res, val2);
661 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
662
663 if (st->channels[chan->address].cfg.pga_bits != res)
664 st->channels[chan->address].cfg.live = false;
665
666 st->channels[chan->address].cfg.pga_bits = res;
667 break;
668 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
669 if (val2 != 0) {
670 ret = -EINVAL;
671 break;
672 }
673
674 ad7124_set_3db_filter_freq(st, chan->address, val);
675 break;
676 default:
677 ret = -EINVAL;
678 }
679
680 mutex_unlock(&st->cfgs_lock);
681 return ret;
682 }
683
684 static int ad7124_reg_access(struct iio_dev *indio_dev,
685 unsigned int reg,
686 unsigned int writeval,
687 unsigned int *readval)
688 {
689 struct ad7124_state *st = iio_priv(indio_dev);
690 int ret;
691
692 if (reg >= ARRAY_SIZE(ad7124_reg_size))
693 return -EINVAL;
694
695 if (readval)
696 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
697 readval);
698 else
699 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
700 writeval);
701
702 return ret;
703 }
704
705 static IIO_CONST_ATTR(in_voltage_scale_available,
706 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
707
708 static struct attribute *ad7124_attributes[] = {
709 &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
710 NULL,
711 };
712
713 static const struct attribute_group ad7124_attrs_group = {
714 .attrs = ad7124_attributes,
715 };
716
717 static int ad7124_update_scan_mode(struct iio_dev *indio_dev,
718 const unsigned long *scan_mask)
719 {
720 struct ad7124_state *st = iio_priv(indio_dev);
721 bool bit_set;
722 int ret;
723 int i;
724
725 mutex_lock(&st->cfgs_lock);
726 for (i = 0; i < st->num_channels; i++) {
727 bit_set = test_bit(i, scan_mask);
728 if (bit_set)
729 ret = __ad7124_set_channel(&st->sd, i);
730 else
731 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK,
732 0, 2);
733 if (ret < 0) {
734 mutex_unlock(&st->cfgs_lock);
735
736 return ret;
737 }
738 }
739
740 mutex_unlock(&st->cfgs_lock);
741
742 return 0;
743 }
744
745 static const struct iio_info ad7124_info = {
746 .read_raw = ad7124_read_raw,
747 .write_raw = ad7124_write_raw,
748 .debugfs_reg_access = &ad7124_reg_access,
749 .validate_trigger = ad_sd_validate_trigger,
750 .update_scan_mode = ad7124_update_scan_mode,
751 .attrs = &ad7124_attrs_group,
752 };
753
754 static int ad7124_soft_reset(struct ad7124_state *st)
755 {
756 unsigned int readval, timeout;
757 int ret;
758
759 ret = ad_sd_reset(&st->sd, 64);
760 if (ret < 0)
761 return ret;
762
763 fsleep(200);
764 timeout = 100;
765 do {
766 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
767 if (ret < 0)
768 return ret;
769
770 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
771 return 0;
772
773 /* The AD7124 requires typically 2ms to power up and settle */
774 usleep_range(100, 2000);
775 } while (--timeout);
776
777 dev_err(&st->sd.spi->dev, "Soft reset failed\n");
778
779 return -EIO;
780 }
781
782 static int ad7124_check_chip_id(struct ad7124_state *st)
783 {
784 unsigned int readval, chip_id, silicon_rev;
785 int ret;
786
787 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
788 if (ret < 0)
789 return ret;
790
791 chip_id = AD7124_DEVICE_ID_GET(readval);
792 silicon_rev = AD7124_SILICON_REV_GET(readval);
793
794 if (chip_id != st->chip_info->chip_id) {
795 dev_err(&st->sd.spi->dev,
796 "Chip ID mismatch: expected %u, got %u\n",
797 st->chip_info->chip_id, chip_id);
798 return -ENODEV;
799 }
800
801 if (silicon_rev == 0) {
802 dev_err(&st->sd.spi->dev,
803 "Silicon revision empty. Chip may not be present\n");
804 return -ENODEV;
805 }
806
807 return 0;
808 }
809
810 static int ad7124_parse_channel_config(struct iio_dev *indio_dev,
811 struct device *dev)
812 {
813 struct ad7124_state *st = iio_priv(indio_dev);
814 struct ad7124_channel_config *cfg;
815 struct ad7124_channel *channels;
816 struct iio_chan_spec *chan;
817 unsigned int ain[2], channel = 0, tmp;
818 int ret;
819
820 st->num_channels = device_get_child_node_count(dev);
821 if (!st->num_channels)
822 return dev_err_probe(dev, -ENODEV, "no channel children\n");
823
824 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
825 sizeof(*chan), GFP_KERNEL);
826 if (!chan)
827 return -ENOMEM;
828
829 channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
830 GFP_KERNEL);
831 if (!channels)
832 return -ENOMEM;
833
834 indio_dev->channels = chan;
835 indio_dev->num_channels = st->num_channels;
836 st->channels = channels;
837
838 device_for_each_child_node_scoped(dev, child) {
839 ret = fwnode_property_read_u32(child, "reg", &channel);
840 if (ret)
841 return ret;
842
843 if (channel >= indio_dev->num_channels)
844 return dev_err_probe(dev, -EINVAL,
845 "Channel index >= number of channels\n");
846
847 ret = fwnode_property_read_u32_array(child, "diff-channels",
848 ain, 2);
849 if (ret)
850 return ret;
851
852 st->channels[channel].nr = channel;
853 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
854 AD7124_CHANNEL_AINM(ain[1]);
855
856 cfg = &st->channels[channel].cfg;
857 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
858
859 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
860 if (ret)
861 cfg->refsel = AD7124_INT_REF;
862 else
863 cfg->refsel = tmp;
864
865 cfg->buf_positive =
866 fwnode_property_read_bool(child, "adi,buffered-positive");
867 cfg->buf_negative =
868 fwnode_property_read_bool(child, "adi,buffered-negative");
869
870 chan[channel] = ad7124_channel_template;
871 chan[channel].address = channel;
872 chan[channel].scan_index = channel;
873 chan[channel].channel = ain[0];
874 chan[channel].channel2 = ain[1];
875 }
876
877 return 0;
878 }
879
880 static int ad7124_setup(struct ad7124_state *st)
881 {
882 unsigned int fclk, power_mode;
883 int i, ret;
884
885 fclk = clk_get_rate(st->mclk);
886 if (!fclk)
887 return -EINVAL;
888
889 /* The power mode changes the master clock frequency */
890 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
891 ARRAY_SIZE(ad7124_master_clk_freq_hz),
892 fclk);
893 if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
894 ret = clk_set_rate(st->mclk, fclk);
895 if (ret)
896 return ret;
897 }
898
899 /* Set the power mode */
900 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
901 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
902
903 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
904 st->adc_control |= AD7124_ADC_CTRL_MODE(AD_SD_MODE_IDLE);
905
906 mutex_init(&st->cfgs_lock);
907 INIT_KFIFO(st->live_cfgs_fifo);
908 for (i = 0; i < st->num_channels; i++) {
909
910 ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
911 if (ret < 0)
912 return ret;
913
914 /*
915 * 9.38 SPS is the minimum output data rate supported
916 * regardless of the selected power mode. Round it up to 10 and
917 * set all channels to this default value.
918 */
919 ad7124_set_channel_odr(st, i, 10);
920 }
921
922 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
923 if (ret < 0)
924 return ret;
925
926 return ret;
927 }
928
929 static void ad7124_reg_disable(void *r)
930 {
931 regulator_disable(r);
932 }
933
934 static int ad7124_probe(struct spi_device *spi)
935 {
936 const struct ad7124_chip_info *info;
937 struct ad7124_state *st;
938 struct iio_dev *indio_dev;
939 int i, ret;
940
941 info = spi_get_device_match_data(spi);
942 if (!info)
943 return -ENODEV;
944
945 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
946 if (!indio_dev)
947 return -ENOMEM;
948
949 st = iio_priv(indio_dev);
950
951 st->chip_info = info;
952
953 indio_dev->name = st->chip_info->name;
954 indio_dev->modes = INDIO_DIRECT_MODE;
955 indio_dev->info = &ad7124_info;
956
957 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
958 if (ret < 0)
959 return ret;
960
961 ret = ad7124_parse_channel_config(indio_dev, &spi->dev);
962 if (ret < 0)
963 return ret;
964
965 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
966 if (i == AD7124_INT_REF)
967 continue;
968
969 st->vref[i] = devm_regulator_get_optional(&spi->dev,
970 ad7124_ref_names[i]);
971 if (PTR_ERR(st->vref[i]) == -ENODEV)
972 continue;
973 else if (IS_ERR(st->vref[i]))
974 return PTR_ERR(st->vref[i]);
975
976 ret = regulator_enable(st->vref[i]);
977 if (ret)
978 return ret;
979
980 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
981 st->vref[i]);
982 if (ret)
983 return ret;
984 }
985
986 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk");
987 if (IS_ERR(st->mclk))
988 return PTR_ERR(st->mclk);
989
990 ret = ad7124_soft_reset(st);
991 if (ret < 0)
992 return ret;
993
994 ret = ad7124_check_chip_id(st);
995 if (ret)
996 return ret;
997
998 ret = ad7124_setup(st);
999 if (ret < 0)
1000 return ret;
1001
1002 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1003 if (ret < 0)
1004 return ret;
1005
1006 return devm_iio_device_register(&spi->dev, indio_dev);
1007
1008 }
1009
1010 static const struct of_device_id ad7124_of_match[] = {
1011 { .compatible = "adi,ad7124-4",
1012 .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
1013 { .compatible = "adi,ad7124-8",
1014 .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
1015 { }
1016 };
1017 MODULE_DEVICE_TABLE(of, ad7124_of_match);
1018
1019 static const struct spi_device_id ad71124_ids[] = {
1020 { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] },
1021 { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] },
1022 { }
1023 };
1024 MODULE_DEVICE_TABLE(spi, ad71124_ids);
1025
1026 static struct spi_driver ad71124_driver = {
1027 .driver = {
1028 .name = "ad7124",
1029 .of_match_table = ad7124_of_match,
1030 },
1031 .probe = ad7124_probe,
1032 .id_table = ad71124_ids,
1033 };
1034 module_spi_driver(ad71124_driver);
1035
1036 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1037 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
1038 MODULE_LICENSE("GPL");
1039 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
Linux Kernel