drivers/iio/adc/ad7606_spi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * AD7606 SPI ADC driver
   4  *
   5  * Copyright 2011 Analog Devices Inc.
   6  */
   7
   8 #include <linux/err.h>
   9 #include <linux/module.h>
  10 #include <linux/spi/spi.h>
  11 #include <linux/types.h>
  12
  13 #include <linux/iio/iio.h>
  14 #include "ad7606.h"
  15
  16 #define MAX_SPI_FREQ_HZ         23500000        /* VDRIVE above 4.75 V */
  17
  18 #define AD7616_CONFIGURATION_REGISTER   0x02
  19 #define AD7616_OS_MASK                  GENMASK(4, 2)
  20 #define AD7616_BURST_MODE               BIT(6)
  21 #define AD7616_SEQEN_MODE               BIT(5)
  22 #define AD7616_RANGE_CH_A_ADDR_OFF      0x04
  23 #define AD7616_RANGE_CH_B_ADDR_OFF      0x06
  24 /*
  25  * Range of channels from a group are stored in 2 registers.
  26  * 0, 1, 2, 3 in a register followed by 4, 5, 6, 7 in second register.
  27  * For channels from second group(8-15) the order is the same, only with
  28  * an offset of 2 for register address.
  29  */
  30 #define AD7616_RANGE_CH_ADDR(ch)        ((ch) >> 2)
  31 /* The range of the channel is stored in 2 bits */
  32 #define AD7616_RANGE_CH_MSK(ch)         (0b11 << (((ch) & 0b11) * 2))
  33 #define AD7616_RANGE_CH_MODE(ch, mode)  ((mode) << ((((ch) & 0b11)) * 2))
  34
  35 #define AD7606_CONFIGURATION_REGISTER   0x02
  36 #define AD7606_SINGLE_DOUT              0x00
  37
  38 /*
  39  * Range for AD7606B channels are stored in registers starting with address 0x3.
  40  * Each register stores range for 2 channels(4 bits per channel).
  41  */
  42 #define AD7606_RANGE_CH_MSK(ch)         (GENMASK(3, 0) << (4 * ((ch) & 0x1)))
  43 #define AD7606_RANGE_CH_MODE(ch, mode)  \
  44         ((GENMASK(3, 0) & mode) << (4 * ((ch) & 0x1)))
  45 #define AD7606_RANGE_CH_ADDR(ch)        (0x03 + ((ch) >> 1))
  46 #define AD7606_OS_MODE                  0x08
  47
  48 static const struct iio_chan_spec ad7616_sw_channels[] = {
  49         IIO_CHAN_SOFT_TIMESTAMP(16),
  50         AD7616_CHANNEL(0),
  51         AD7616_CHANNEL(1),
  52         AD7616_CHANNEL(2),
  53         AD7616_CHANNEL(3),
  54         AD7616_CHANNEL(4),
  55         AD7616_CHANNEL(5),
  56         AD7616_CHANNEL(6),
  57         AD7616_CHANNEL(7),
  58         AD7616_CHANNEL(8),
  59         AD7616_CHANNEL(9),
  60         AD7616_CHANNEL(10),
  61         AD7616_CHANNEL(11),
  62         AD7616_CHANNEL(12),
  63         AD7616_CHANNEL(13),
  64         AD7616_CHANNEL(14),
  65         AD7616_CHANNEL(15),
  66 };
  67
  68 static const struct iio_chan_spec ad7606b_sw_channels[] = {
  69         IIO_CHAN_SOFT_TIMESTAMP(8),
  70         AD7606_SW_CHANNEL(0, 16),
  71         AD7606_SW_CHANNEL(1, 16),
  72         AD7606_SW_CHANNEL(2, 16),
  73         AD7606_SW_CHANNEL(3, 16),
  74         AD7606_SW_CHANNEL(4, 16),
  75         AD7606_SW_CHANNEL(5, 16),
  76         AD7606_SW_CHANNEL(6, 16),
  77         AD7606_SW_CHANNEL(7, 16),
  78 };
  79
  80 static const struct iio_chan_spec ad7606c_18_sw_channels[] = {
  81         IIO_CHAN_SOFT_TIMESTAMP(8),
  82         AD7606_SW_CHANNEL(0, 18),
  83         AD7606_SW_CHANNEL(1, 18),
  84         AD7606_SW_CHANNEL(2, 18),
  85         AD7606_SW_CHANNEL(3, 18),
  86         AD7606_SW_CHANNEL(4, 18),
  87         AD7606_SW_CHANNEL(5, 18),
  88         AD7606_SW_CHANNEL(6, 18),
  89         AD7606_SW_CHANNEL(7, 18),
  90 };
  91
  92 static const unsigned int ad7606B_oversampling_avail[9] = {
  93         1, 2, 4, 8, 16, 32, 64, 128, 256
  94 };
  95
  96 static u16 ad7616_spi_rd_wr_cmd(int addr, char isWriteOp)
  97 {
  98         /*
  99          * The address of register consist of one w/r bit
 100          * 6 bits of address followed by one reserved bit.
 101          */
 102         return ((addr & 0x7F) << 1) | ((isWriteOp & 0x1) << 7);
 103 }
 104
 105 static u16 ad7606B_spi_rd_wr_cmd(int addr, char is_write_op)
 106 {
 107         /*
 108          * The address of register consists of one bit which
 109          * specifies a read command placed in bit 6, followed by
 110          * 6 bits of address.
 111          */
 112         return (addr & 0x3F) | (((~is_write_op) & 0x1) << 6);
 113 }
 114
 115 static int ad7606_spi_read_block(struct device *dev,
 116                                  int count, void *buf)
 117 {
 118         struct spi_device *spi = to_spi_device(dev);
 119         int i, ret;
 120         unsigned short *data = buf;
 121         __be16 *bdata = buf;
 122
 123         ret = spi_read(spi, buf, count * 2);
 124         if (ret < 0) {
 125                 dev_err(&spi->dev, "SPI read error\n");
 126                 return ret;
 127         }
 128
 129         for (i = 0; i < count; i++)
 130                 data[i] = be16_to_cpu(bdata[i]);
 131
 132         return 0;
 133 }
 134
 135 static int ad7606_spi_read_block14to16(struct device *dev,
 136                                        int count, void *buf)
 137 {
 138         struct spi_device *spi = to_spi_device(dev);
 139         struct spi_transfer xfer = {
 140                 .bits_per_word = 14,
 141                 .len = count * sizeof(u16),
 142                 .rx_buf = buf,
 143         };
 144
 145         return spi_sync_transfer(spi, &xfer, 1);
 146 }
 147
 148 static int ad7606_spi_read_block18to32(struct device *dev,
 149                                        int count, void *buf)
 150 {
 151         struct spi_device *spi = to_spi_device(dev);
 152         struct spi_transfer xfer = {
 153                 .bits_per_word = 18,
 154                 .len = count * sizeof(u32),
 155                 .rx_buf = buf,
 156         };
 157
 158         return spi_sync_transfer(spi, &xfer, 1);
 159 }
 160
 161 static int ad7606_spi_reg_read(struct ad7606_state *st, unsigned int addr)
 162 {
 163         struct spi_device *spi = to_spi_device(st->dev);
 164         struct spi_transfer t[] = {
 165                 {
 166                         .tx_buf = &st->d16[0],
 167                         .len = 2,
 168                         .cs_change = 0,
 169                 }, {
 170                         .rx_buf = &st->d16[1],
 171                         .len = 2,
 172                 },
 173         };
 174         int ret;
 175
 176         st->d16[0] = cpu_to_be16(st->bops->rd_wr_cmd(addr, 0) << 8);
 177
 178         ret = spi_sync_transfer(spi, t, ARRAY_SIZE(t));
 179         if (ret < 0)
 180                 return ret;
 181
 182         return be16_to_cpu(st->d16[1]);
 183 }
 184
 185 static int ad7606_spi_reg_write(struct ad7606_state *st,
 186                                 unsigned int addr,
 187                                 unsigned int val)
 188 {
 189         struct spi_device *spi = to_spi_device(st->dev);
 190
 191         st->d16[0] = cpu_to_be16((st->bops->rd_wr_cmd(addr, 1) << 8) |
 192                                   (val & 0x1FF));
 193
 194         return spi_write(spi, &st->d16[0], sizeof(st->d16[0]));
 195 }
 196
 197 static int ad7606_spi_write_mask(struct ad7606_state *st,
 198                                  unsigned int addr,
 199                                  unsigned long mask,
 200                                  unsigned int val)
 201 {
 202         int readval;
 203
 204         readval = st->bops->reg_read(st, addr);
 205         if (readval < 0)
 206                 return readval;
 207
 208         readval &= ~mask;
 209         readval |= val;
 210
 211         return st->bops->reg_write(st, addr, readval);
 212 }
 213
 214 static int ad7616_write_scale_sw(struct iio_dev *indio_dev, int ch, int val)
 215 {
 216         struct ad7606_state *st = iio_priv(indio_dev);
 217         unsigned int ch_addr, mode, ch_index;
 218
 219
 220         /*
 221          * Ad7616 has 16 channels divided in group A and group B.
 222          * The range of channels from A are stored in registers with address 4
 223          * while channels from B are stored in register with address 6.
 224          * The last bit from channels determines if it is from group A or B
 225          * because the order of channels in iio is 0A, 0B, 1A, 1B...
 226          */
 227         ch_index = ch >> 1;
 228
 229         ch_addr = AD7616_RANGE_CH_ADDR(ch_index);
 230
 231         if ((ch & 0x1) == 0) /* channel A */
 232                 ch_addr += AD7616_RANGE_CH_A_ADDR_OFF;
 233         else    /* channel B */
 234                 ch_addr += AD7616_RANGE_CH_B_ADDR_OFF;
 235
 236         /* 0b01 for 2.5v, 0b10 for 5v and 0b11 for 10v */
 237         mode = AD7616_RANGE_CH_MODE(ch_index, ((val + 1) & 0b11));
 238         return st->bops->write_mask(st, ch_addr, AD7616_RANGE_CH_MSK(ch_index),
 239                                      mode);
 240 }
 241
 242 static int ad7616_write_os_sw(struct iio_dev *indio_dev, int val)
 243 {
 244         struct ad7606_state *st = iio_priv(indio_dev);
 245
 246         return st->bops->write_mask(st, AD7616_CONFIGURATION_REGISTER,
 247                                      AD7616_OS_MASK, val << 2);
 248 }
 249
 250 static int ad7606_write_scale_sw(struct iio_dev *indio_dev, int ch, int val)
 251 {
 252         struct ad7606_state *st = iio_priv(indio_dev);
 253
 254         return ad7606_spi_write_mask(st,
 255                                      AD7606_RANGE_CH_ADDR(ch),
 256                                      AD7606_RANGE_CH_MSK(ch),
 257                                      AD7606_RANGE_CH_MODE(ch, val));
 258 }
 259
 260 static int ad7606_write_os_sw(struct iio_dev *indio_dev, int val)
 261 {
 262         struct ad7606_state *st = iio_priv(indio_dev);
 263
 264         return ad7606_spi_reg_write(st, AD7606_OS_MODE, val);
 265 }
 266
 267 static int ad7616_sw_mode_config(struct iio_dev *indio_dev)
 268 {
 269         struct ad7606_state *st = iio_priv(indio_dev);
 270
 271         /*
 272          * Scale can be configured individually for each channel
 273          * in software mode.
 274          */
 275         indio_dev->channels = ad7616_sw_channels;
 276
 277         st->write_scale = ad7616_write_scale_sw;
 278         st->write_os = &ad7616_write_os_sw;
 279
 280         /* Activate Burst mode and SEQEN MODE */
 281         return st->bops->write_mask(st,
 282                               AD7616_CONFIGURATION_REGISTER,
 283                               AD7616_BURST_MODE | AD7616_SEQEN_MODE,
 284                               AD7616_BURST_MODE | AD7616_SEQEN_MODE);
 285 }
 286
 287 static int ad7606B_sw_mode_config(struct iio_dev *indio_dev)
 288 {
 289         struct ad7606_state *st = iio_priv(indio_dev);
 290         DECLARE_BITMAP(os, 3);
 291
 292         bitmap_fill(os, 3);
 293         /*
 294          * Software mode is enabled when all three oversampling
 295          * pins are set to high. If oversampling gpios are defined
 296          * in the device tree, then they need to be set to high,
 297          * otherwise, they must be hardwired to VDD
 298          */
 299         if (st->gpio_os) {
 300                 gpiod_set_array_value(st->gpio_os->ndescs,
 301                                       st->gpio_os->desc, st->gpio_os->info, os);
 302         }
 303         /* OS of 128 and 256 are available only in software mode */
 304         st->oversampling_avail = ad7606B_oversampling_avail;
 305         st->num_os_ratios = ARRAY_SIZE(ad7606B_oversampling_avail);
 306
 307         st->write_scale = ad7606_write_scale_sw;
 308         st->write_os = &ad7606_write_os_sw;
 309
 310         /* Configure device spi to output on a single channel */
 311         st->bops->reg_write(st,
 312                             AD7606_CONFIGURATION_REGISTER,
 313                             AD7606_SINGLE_DOUT);
 314
 315         /*
 316          * Scale can be configured individually for each channel
 317          * in software mode.
 318          */
 319         indio_dev->channels = ad7606b_sw_channels;
 320
 321         return 0;
 322 }
 323
 324 static int ad7606c_18_sw_mode_config(struct iio_dev *indio_dev)
 325 {
 326         int ret;
 327
 328         ret = ad7606B_sw_mode_config(indio_dev);
 329         if (ret)
 330                 return ret;
 331
 332         indio_dev->channels = ad7606c_18_sw_channels;
 333
 334         return 0;
 335 }
 336
 337 static const struct ad7606_bus_ops ad7606_spi_bops = {
 338         .read_block = ad7606_spi_read_block,
 339 };
 340
 341 static const struct ad7606_bus_ops ad7607_spi_bops = {
 342         .read_block = ad7606_spi_read_block14to16,
 343 };
 344
 345 static const struct ad7606_bus_ops ad7608_spi_bops = {
 346         .read_block = ad7606_spi_read_block18to32,
 347 };
 348
 349 static const struct ad7606_bus_ops ad7616_spi_bops = {
 350         .read_block = ad7606_spi_read_block,
 351         .reg_read = ad7606_spi_reg_read,
 352         .reg_write = ad7606_spi_reg_write,
 353         .write_mask = ad7606_spi_write_mask,
 354         .rd_wr_cmd = ad7616_spi_rd_wr_cmd,
 355         .sw_mode_config = ad7616_sw_mode_config,
 356 };
 357
 358 static const struct ad7606_bus_ops ad7606b_spi_bops = {
 359         .read_block = ad7606_spi_read_block,
 360         .reg_read = ad7606_spi_reg_read,
 361         .reg_write = ad7606_spi_reg_write,
 362         .write_mask = ad7606_spi_write_mask,
 363         .rd_wr_cmd = ad7606B_spi_rd_wr_cmd,
 364         .sw_mode_config = ad7606B_sw_mode_config,
 365 };
 366
 367 static const struct ad7606_bus_ops ad7606c_18_spi_bops = {
 368         .read_block = ad7606_spi_read_block18to32,
 369         .reg_read = ad7606_spi_reg_read,
 370         .reg_write = ad7606_spi_reg_write,
 371         .write_mask = ad7606_spi_write_mask,
 372         .rd_wr_cmd = ad7606B_spi_rd_wr_cmd,
 373         .sw_mode_config = ad7606c_18_sw_mode_config,
 374 };
 375
 376 static const struct ad7606_bus_info ad7605_4_bus_info = {
 377         .chip_info = &ad7605_4_info,
 378         .bops = &ad7606_spi_bops,
 379 };
 380
 381 static const struct ad7606_bus_info ad7606_8_bus_info = {
 382         .chip_info = &ad7606_8_info,
 383         .bops = &ad7606_spi_bops,
 384 };
 385
 386 static const struct ad7606_bus_info ad7606_6_bus_info = {
 387         .chip_info = &ad7606_6_info,
 388         .bops = &ad7606_spi_bops,
 389 };
 390
 391 static const struct ad7606_bus_info ad7606_4_bus_info = {
 392         .chip_info = &ad7606_4_info,
 393         .bops = &ad7606_spi_bops,
 394 };
 395
 396 static const struct ad7606_bus_info ad7606b_bus_info = {
 397         .chip_info = &ad7606b_info,
 398         .bops = &ad7606b_spi_bops,
 399 };
 400
 401 static const struct ad7606_bus_info ad7606c_16_bus_info = {
 402         .chip_info = &ad7606c_16_info,
 403         .bops = &ad7606b_spi_bops,
 404 };
 405
 406 static const struct ad7606_bus_info ad7606c_18_bus_info = {
 407         .chip_info = &ad7606c_18_info,
 408         .bops = &ad7606c_18_spi_bops,
 409 };
 410
 411 static const struct ad7606_bus_info ad7607_bus_info = {
 412         .chip_info = &ad7607_info,
 413         .bops = &ad7607_spi_bops,
 414 };
 415
 416 static const struct ad7606_bus_info ad7608_bus_info = {
 417         .chip_info = &ad7608_info,
 418         .bops = &ad7608_spi_bops,
 419 };
 420
 421 static const struct ad7606_bus_info ad7609_bus_info = {
 422         .chip_info = &ad7609_info,
 423         .bops = &ad7608_spi_bops,
 424 };
 425
 426 static const struct ad7606_bus_info ad7616_bus_info = {
 427         .chip_info = &ad7616_info,
 428         .bops = &ad7616_spi_bops,
 429 };
 430
 431 static int ad7606_spi_probe(struct spi_device *spi)
 432 {
 433         const struct ad7606_bus_info *bus_info = spi_get_device_match_data(spi);
 434
 435         return ad7606_probe(&spi->dev, spi->irq, NULL,
 436                             bus_info->chip_info, bus_info->bops);
 437 }
 438
 439 static const struct spi_device_id ad7606_id_table[] = {
 440         { "ad7605-4", (kernel_ulong_t)&ad7605_4_bus_info },
 441         { "ad7606-4", (kernel_ulong_t)&ad7606_4_bus_info },
 442         { "ad7606-6", (kernel_ulong_t)&ad7606_6_bus_info },
 443         { "ad7606-8", (kernel_ulong_t)&ad7606_8_bus_info },
 444         { "ad7606b",  (kernel_ulong_t)&ad7606b_bus_info },
 445         { "ad7606c-16", (kernel_ulong_t)&ad7606c_16_bus_info },
 446         { "ad7606c-18", (kernel_ulong_t)&ad7606c_18_bus_info },
 447         { "ad7607",   (kernel_ulong_t)&ad7607_bus_info },
 448         { "ad7608",   (kernel_ulong_t)&ad7608_bus_info },
 449         { "ad7609",   (kernel_ulong_t)&ad7609_bus_info },
 450         { "ad7616",   (kernel_ulong_t)&ad7616_bus_info },
 451         { }
 452 };
 453 MODULE_DEVICE_TABLE(spi, ad7606_id_table);
 454
 455 static const struct of_device_id ad7606_of_match[] = {
 456         { .compatible = "adi,ad7605-4", .data = &ad7605_4_bus_info },
 457         { .compatible = "adi,ad7606-4", .data = &ad7606_4_bus_info },
 458         { .compatible = "adi,ad7606-6", .data = &ad7606_6_bus_info },
 459         { .compatible = "adi,ad7606-8", .data = &ad7606_8_bus_info },
 460         { .compatible = "adi,ad7606b", .data = &ad7606b_bus_info },
 461         { .compatible = "adi,ad7606c-16", .data = &ad7606c_16_bus_info },
 462         { .compatible = "adi,ad7606c-18", .data = &ad7606c_18_bus_info },
 463         { .compatible = "adi,ad7607", .data = &ad7607_bus_info },
 464         { .compatible = "adi,ad7608", .data = &ad7608_bus_info },
 465         { .compatible = "adi,ad7609", .data = &ad7609_bus_info },
 466         { .compatible = "adi,ad7616", .data = &ad7616_bus_info },
 467         { }
 468 };
 469 MODULE_DEVICE_TABLE(of, ad7606_of_match);
 470
 471 static struct spi_driver ad7606_driver = {
 472         .driver = {
 473                 .name = "ad7606",
 474                 .of_match_table = ad7606_of_match,
 475                 .pm = AD7606_PM_OPS,
 476         },
 477         .probe = ad7606_spi_probe,
 478         .id_table = ad7606_id_table,
 479 };
 480 module_spi_driver(ad7606_driver);
 481
 482 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
 483 MODULE_DESCRIPTION("Analog Devices AD7606 ADC");
 484 MODULE_LICENSE("GPL v2");
 485 MODULE_IMPORT_NS("IIO_AD7606");