drivers/iio/dac/ad9739a.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Analog Devices AD9739a SPI DAC driver
   4  *
   5  * Copyright 2015-2024 Analog Devices Inc.
   6  */
   7 #include <linux/bitfield.h>
   8 #include <linux/bits.h>
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/device.h>
  12 #include <linux/err.h>
  13 #include <linux/errno.h>
  14 #include <linux/gpio/consumer.h>
  15 #include <linux/minmax.h>
  16 #include <linux/module.h>
  17 #include <linux/mod_devicetable.h>
  18 #include <linux/property.h>
  19 #include <linux/regmap.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/units.h>
  22
  23 #include <linux/iio/backend.h>
  24 #include <linux/iio/iio.h>
  25 #include <linux/iio/types.h>
  26
  27 #define AD9739A_REG_MODE                0
  28 #define   AD9739A_RESET_MASK            BIT(5)
  29 #define AD9739A_REG_FSC_1               0x06
  30 #define AD9739A_REG_FSC_2               0x07
  31 #define   AD9739A_FSC_MSB               GENMASK(1, 0)
  32 #define AD9739A_REG_DEC_CNT             0x8
  33 #define   AD9739A_NORMAL_MODE           0
  34 #define   AD9739A_MIXED_MODE            2
  35 #define   AD9739A_DAC_DEC               GENMASK(1, 0)
  36 #define AD9739A_REG_LVDS_REC_CNT1       0x10
  37 #define   AD9739A_RCVR_LOOP_EN_MASK     GENMASK(1, 0)
  38 #define AD9739A_REG_LVDS_REC_CNT4       0x13
  39 #define   AD9739A_FINE_DEL_SKW_MASK     GENMASK(3, 0)
  40 #define AD9739A_REG_LVDS_REC_STAT9      0x21
  41 #define   AD9739A_RCVR_TRACK_AND_LOCK   (BIT(3) | BIT(0))
  42 #define AD9739A_REG_CROSS_CNT1          0x22
  43 #define AD9739A_REG_CROSS_CNT2          0x23
  44 #define AD9739A_REG_PHS_DET             0x24
  45 #define AD9739A_REG_MU_DUTY             0x25
  46 #define AD9739A_REG_MU_CNT1             0x26
  47 #define   AD9739A_MU_EN_MASK            BIT(0)
  48 #define   AD9739A_MU_GAIN_MASK          BIT(1)
  49 #define AD9739A_REG_MU_CNT2             0x27
  50 #define AD9739A_REG_MU_CNT3             0x28
  51 #define AD9739A_REG_MU_CNT4             0x29
  52 #define   AD9739A_MU_CNT4_DEFAULT       0xcb
  53 #define AD9739A_REG_MU_STAT1            0x2A
  54 #define   AD9739A_MU_LOCK_MASK          BIT(0)
  55 #define AD9739A_REG_ANA_CNT_1           0x32
  56 #define AD9739A_REG_ID                  0x35
  57
  58 #define AD9739A_ID                      0x24
  59 #define AD9739A_REG_IS_RESERVED(reg)    \
  60         ((reg) == 0x5 || (reg) == 0x9 || (reg) == 0x0E || (reg) == 0x0D || \
  61          (reg) == 0x2B || (reg) == 0x2C || (reg) == 0x34)
  62
  63 #define AD9739A_FSC_MIN         8580
  64 #define AD9739A_FSC_MAX         31700
  65 #define AD9739A_FSC_RANGE       (AD9739A_FSC_MAX - AD9739A_FSC_MIN + 1)
  66
  67 #define AD9739A_MIN_DAC_CLK     (1600 * MEGA)
  68 #define AD9739A_MAX_DAC_CLK     (2500 * MEGA)
  69 #define AD9739A_DAC_CLK_RANGE   (AD9739A_MAX_DAC_CLK - AD9739A_MIN_DAC_CLK + 1)
  70 /* as recommended by the datasheet */
  71 #define AD9739A_LOCK_N_TRIES    3
  72
  73 struct ad9739a_state {
  74         struct iio_backend *back;
  75         struct regmap *regmap;
  76         unsigned long sample_rate;
  77 };
  78
  79 static int ad9739a_oper_mode_get(struct iio_dev *indio_dev,
  80                                  const struct iio_chan_spec *chan)
  81 {
  82         struct ad9739a_state *st = iio_priv(indio_dev);
  83         u32 mode;
  84         int ret;
  85
  86         ret = regmap_read(st->regmap, AD9739A_REG_DEC_CNT, &mode);
  87         if (ret)
  88                 return ret;
  89
  90         mode = FIELD_GET(AD9739A_DAC_DEC, mode);
  91         /* sanity check we get valid values from the HW */
  92         if (mode != AD9739A_NORMAL_MODE && mode != AD9739A_MIXED_MODE)
  93                 return -EIO;
  94         if (!mode)
  95                 return AD9739A_NORMAL_MODE;
  96
  97         /*
  98          * We get 2 from the device but for IIO modes, that means 1. Hence the
  99          * minus 1.
 100          */
 101         return AD9739A_MIXED_MODE - 1;
 102 }
 103
 104 static int ad9739a_oper_mode_set(struct iio_dev *indio_dev,
 105                                  const struct iio_chan_spec *chan, u32 mode)
 106 {
 107         struct ad9739a_state *st = iio_priv(indio_dev);
 108
 109         /*
 110          * On the IIO interface we have 0 and 1 for mode. But for mixed_mode, we
 111          * need to write 2 in the device. That's what the below check is about.
 112          */
 113         if (mode == AD9739A_MIXED_MODE - 1)
 114                 mode = AD9739A_MIXED_MODE;
 115
 116         return regmap_update_bits(st->regmap, AD9739A_REG_DEC_CNT,
 117                                   AD9739A_DAC_DEC, mode);
 118 }
 119
 120 static int ad9739a_read_raw(struct iio_dev *indio_dev,
 121                             struct iio_chan_spec const *chan,
 122                             int *val, int *val2, long mask)
 123 {
 124         struct ad9739a_state *st = iio_priv(indio_dev);
 125
 126         switch (mask) {
 127         case IIO_CHAN_INFO_SAMP_FREQ:
 128                 *val = st->sample_rate;
 129                 *val2 = 0;
 130                 return IIO_VAL_INT_64;
 131         default:
 132                 return -EINVAL;
 133         }
 134 }
 135
 136 static int ad9739a_buffer_preenable(struct iio_dev *indio_dev)
 137 {
 138         struct ad9739a_state *st = iio_priv(indio_dev);
 139
 140         return iio_backend_data_source_set(st->back, 0, IIO_BACKEND_EXTERNAL);
 141 }
 142
 143 static int ad9739a_buffer_postdisable(struct iio_dev *indio_dev)
 144 {
 145         struct ad9739a_state *st = iio_priv(indio_dev);
 146
 147         return iio_backend_data_source_set(st->back, 0,
 148                                            IIO_BACKEND_INTERNAL_CONTINUOUS_WAVE);
 149 }
 150
 151 static bool ad9739a_reg_accessible(struct device *dev, unsigned int reg)
 152 {
 153         if (AD9739A_REG_IS_RESERVED(reg))
 154                 return false;
 155         if (reg > AD9739A_REG_MU_STAT1 && reg < AD9739A_REG_ANA_CNT_1)
 156                 return false;
 157
 158         return true;
 159 }
 160
 161 static int ad9739a_reset(struct device *dev, const struct ad9739a_state *st)
 162 {
 163         struct gpio_desc *gpio;
 164         int ret;
 165
 166         gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
 167         if (IS_ERR(gpio))
 168                 return PTR_ERR(gpio);
 169         if (gpio) {
 170                 /* minimum pulse width of 40ns */
 171                 ndelay(40);
 172                 gpiod_set_value_cansleep(gpio, 0);
 173                 return 0;
 174         }
 175
 176         /* bring all registers to their default state */
 177         ret = regmap_set_bits(st->regmap, AD9739A_REG_MODE, AD9739A_RESET_MASK);
 178         if (ret)
 179                 return ret;
 180
 181         ndelay(40);
 182
 183         return regmap_clear_bits(st->regmap, AD9739A_REG_MODE,
 184                                  AD9739A_RESET_MASK);
 185 }
 186
 187 /*
 188  * Recommended values (as per datasheet) for the dac clk common mode voltage
 189  * and Mu controller. Look at table 29.
 190  */
 191 static const struct reg_sequence ad9739a_clk_mu_ctrl[] = {
 192         /* DAC clk common mode voltage */
 193         { AD9739A_REG_CROSS_CNT1, 0x0f },
 194         { AD9739A_REG_CROSS_CNT2, 0x0f },
 195         /* Mu controller configuration */
 196         { AD9739A_REG_PHS_DET, 0x30 },
 197         { AD9739A_REG_MU_DUTY, 0x80 },
 198         { AD9739A_REG_MU_CNT2, 0x44 },
 199         { AD9739A_REG_MU_CNT3, 0x6c },
 200 };
 201
 202 static int ad9739a_init(struct device *dev, const struct ad9739a_state *st)
 203 {
 204         unsigned int i = 0, lock, fsc;
 205         u32 fsc_raw;
 206         int ret;
 207
 208         ret = regmap_multi_reg_write(st->regmap, ad9739a_clk_mu_ctrl,
 209                                      ARRAY_SIZE(ad9739a_clk_mu_ctrl));
 210         if (ret)
 211                 return ret;
 212
 213         /*
 214          * Try to get the Mu lock. Repeat the below steps AD9739A_LOCK_N_TRIES
 215          * (as specified by the datasheet) until we get the lock.
 216          */
 217         do {
 218                 ret = regmap_write(st->regmap, AD9739A_REG_MU_CNT4,
 219                                    AD9739A_MU_CNT4_DEFAULT);
 220                 if (ret)
 221                         return ret;
 222
 223                 /* Enable the Mu controller search and track mode. */
 224                 ret = regmap_write(st->regmap, AD9739A_REG_MU_CNT1,
 225                                    AD9739A_MU_EN_MASK | AD9739A_MU_GAIN_MASK);
 226                 if (ret)
 227                         return ret;
 228
 229                 /* Ensure the DLL loop is locked */
 230                 ret = regmap_read_poll_timeout(st->regmap, AD9739A_REG_MU_STAT1,
 231                                                lock, lock & AD9739A_MU_LOCK_MASK,
 232                                                0, 1000);
 233                 if (ret && ret != -ETIMEDOUT)
 234                         return ret;
 235         } while (ret && ++i < AD9739A_LOCK_N_TRIES);
 236
 237         if (i == AD9739A_LOCK_N_TRIES)
 238                 return dev_err_probe(dev, ret, "Mu lock timeout\n");
 239
 240         /* Receiver tracking and lock. Same deal as the Mu controller */
 241         i = 0;
 242         do {
 243                 ret = regmap_update_bits(st->regmap, AD9739A_REG_LVDS_REC_CNT4,
 244                                          AD9739A_FINE_DEL_SKW_MASK,
 245                                          FIELD_PREP(AD9739A_FINE_DEL_SKW_MASK, 2));
 246                 if (ret)
 247                         return ret;
 248
 249                 /* Disable the receiver and the loop. */
 250                 ret = regmap_write(st->regmap, AD9739A_REG_LVDS_REC_CNT1, 0);
 251                 if (ret)
 252                         return ret;
 253
 254                 /*
 255                  * Re-enable the loop so it falls out of lock and begins the
 256                  * search/track routine again.
 257                  */
 258                 ret = regmap_set_bits(st->regmap, AD9739A_REG_LVDS_REC_CNT1,
 259                                       AD9739A_RCVR_LOOP_EN_MASK);
 260                 if (ret)
 261                         return ret;
 262
 263                 /* Ensure the DLL loop is locked */
 264                 ret = regmap_read_poll_timeout(st->regmap,
 265                                                AD9739A_REG_LVDS_REC_STAT9, lock,
 266                                                lock == AD9739A_RCVR_TRACK_AND_LOCK,
 267                                                0, 1000);
 268                 if (ret && ret != -ETIMEDOUT)
 269                         return ret;
 270         } while (ret && ++i < AD9739A_LOCK_N_TRIES);
 271
 272         if (i == AD9739A_LOCK_N_TRIES)
 273                 return dev_err_probe(dev, ret, "Receiver lock timeout\n");
 274
 275         ret = device_property_read_u32(dev, "adi,full-scale-microamp", &fsc);
 276         if (ret && ret == -EINVAL)
 277                 return 0;
 278         if (ret)
 279                 return ret;
 280         if (!in_range(fsc, AD9739A_FSC_MIN, AD9739A_FSC_RANGE))
 281                 return dev_err_probe(dev, -EINVAL,
 282                                      "Invalid full scale current(%u) [%u %u]\n",
 283                                      fsc, AD9739A_FSC_MIN, AD9739A_FSC_MAX);
 284         /*
 285          * IOUTFS is given by
 286          *      Ioutfs = 0.0226 * FSC + 8.58
 287          * and is given in mA. Hence we'll have to multiply by 10 * MILLI in
 288          * order to get rid of the fractional.
 289          */
 290         fsc_raw = DIV_ROUND_CLOSEST(fsc * 10 - 85800, 226);
 291
 292         ret = regmap_write(st->regmap, AD9739A_REG_FSC_1, fsc_raw & 0xff);
 293         if (ret)
 294                 return ret;
 295
 296         return regmap_update_bits(st->regmap, AD9739A_REG_FSC_2,
 297                                   AD9739A_FSC_MSB, fsc_raw >> 8);
 298 }
 299
 300 static const char * const ad9739a_modes_avail[] = { "normal", "mixed-mode" };
 301
 302 static const struct iio_enum ad9739a_modes = {
 303         .items = ad9739a_modes_avail,
 304         .num_items = ARRAY_SIZE(ad9739a_modes_avail),
 305         .get = ad9739a_oper_mode_get,
 306         .set = ad9739a_oper_mode_set,
 307 };
 308
 309 static const struct iio_chan_spec_ext_info ad9739a_ext_info[] = {
 310         IIO_ENUM_AVAILABLE("operating_mode", IIO_SEPARATE, &ad9739a_modes),
 311         IIO_ENUM("operating_mode", IIO_SEPARATE, &ad9739a_modes),
 312         { }
 313 };
 314
 315 /*
 316  * The reason for having two different channels is because we have, in reality,
 317  * two sources of data:
 318  *   ALTVOLTAGE: It's a Continuous Wave that's internally generated by the
 319  *               backend device.
 320  *   VOLTAGE: It's the typical data we can have in a DAC device and the source
 321  *            of it has nothing to do with the backend. The backend will only
 322  *            forward it into our data interface to be sent out.
 323  */
 324 static struct iio_chan_spec ad9739a_channels[] = {
 325         {
 326                 .type = IIO_ALTVOLTAGE,
 327                 .indexed = 1,
 328                 .output = 1,
 329                 .scan_index = -1,
 330         },
 331         {
 332                 .type = IIO_VOLTAGE,
 333                 .indexed = 1,
 334                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 335                 .output = 1,
 336                 .ext_info = ad9739a_ext_info,
 337                 .scan_type = {
 338                         .sign = 's',
 339                         .storagebits = 16,
 340                         .realbits = 16,
 341                 },
 342         }
 343 };
 344
 345 static const struct iio_info ad9739a_info = {
 346         .read_raw = ad9739a_read_raw,
 347 };
 348
 349 static const struct iio_buffer_setup_ops ad9739a_buffer_setup_ops = {
 350         .preenable = &ad9739a_buffer_preenable,
 351         .postdisable = &ad9739a_buffer_postdisable,
 352 };
 353
 354 static const struct regmap_config ad9739a_regmap_config = {
 355         .reg_bits = 8,
 356         .val_bits = 8,
 357         .readable_reg = ad9739a_reg_accessible,
 358         .writeable_reg = ad9739a_reg_accessible,
 359         .max_register = AD9739A_REG_ID,
 360 };
 361
 362 static int ad9739a_probe(struct spi_device *spi)
 363 {
 364         struct device *dev = &spi->dev;
 365         struct iio_dev *indio_dev;
 366         struct ad9739a_state *st;
 367         unsigned int id;
 368         struct clk *clk;
 369         int ret;
 370
 371         indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
 372         if (!indio_dev)
 373                 return -ENOMEM;
 374
 375         st = iio_priv(indio_dev);
 376
 377         clk = devm_clk_get_enabled(dev, NULL);
 378         if (IS_ERR(clk))
 379                 return dev_err_probe(dev, PTR_ERR(clk), "Could not get clkin\n");
 380
 381         st->sample_rate = clk_get_rate(clk);
 382         if (!in_range(st->sample_rate, AD9739A_MIN_DAC_CLK,
 383                       AD9739A_DAC_CLK_RANGE))
 384                 return dev_err_probe(dev, -EINVAL,
 385                                      "Invalid dac clk range(%lu) [%lu %lu]\n",
 386                                      st->sample_rate, AD9739A_MIN_DAC_CLK,
 387                                      AD9739A_MAX_DAC_CLK);
 388
 389         st->regmap = devm_regmap_init_spi(spi, &ad9739a_regmap_config);
 390         if (IS_ERR(st->regmap))
 391                 return PTR_ERR(st->regmap);
 392
 393         ret = regmap_read(st->regmap, AD9739A_REG_ID, &id);
 394         if (ret)
 395                 return ret;
 396
 397         if (id != AD9739A_ID)
 398                 dev_warn(dev, "Unrecognized CHIP_ID 0x%X", id);
 399
 400         ret = ad9739a_reset(dev, st);
 401         if (ret)
 402                 return ret;
 403
 404         ret = ad9739a_init(dev, st);
 405         if (ret)
 406                 return ret;
 407
 408         st->back = devm_iio_backend_get(dev, NULL);
 409         if (IS_ERR(st->back))
 410                 return PTR_ERR(st->back);
 411
 412         ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev);
 413         if (ret)
 414                 return ret;
 415
 416         ret = iio_backend_extend_chan_spec(st->back, &ad9739a_channels[0]);
 417         if (ret)
 418                 return ret;
 419
 420         ret = iio_backend_set_sampling_freq(st->back, 0, st->sample_rate);
 421         if (ret)
 422                 return ret;
 423
 424         ret = devm_iio_backend_enable(dev, st->back);
 425         if (ret)
 426                 return ret;
 427
 428         indio_dev->name = "ad9739a";
 429         indio_dev->info = &ad9739a_info;
 430         indio_dev->channels = ad9739a_channels;
 431         indio_dev->num_channels = ARRAY_SIZE(ad9739a_channels);
 432         indio_dev->setup_ops = &ad9739a_buffer_setup_ops;
 433
 434         ret = devm_iio_device_register(&spi->dev, indio_dev);
 435         if (ret)
 436                 return ret;
 437
 438         iio_backend_debugfs_add(st->back, indio_dev);
 439
 440         return 0;
 441 }
 442
 443 static const struct of_device_id ad9739a_of_match[] = {
 444         { .compatible = "adi,ad9739a" },
 445         {}
 446 };
 447 MODULE_DEVICE_TABLE(of, ad9739a_of_match);
 448
 449 static const struct spi_device_id ad9739a_id[] = {
 450         {"ad9739a"},
 451         {}
 452 };
 453 MODULE_DEVICE_TABLE(spi, ad9739a_id);
 454
 455 static struct spi_driver ad9739a_driver = {
 456         .driver = {
 457                 .name = "ad9739a",
 458                 .of_match_table = ad9739a_of_match,
 459         },
 460         .probe = ad9739a_probe,
 461         .id_table = ad9739a_id,
 462 };
 463 module_spi_driver(ad9739a_driver);
 464
 465 MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>");
 466 MODULE_AUTHOR("Nuno Sa <nuno.sa@analog.com>");
 467 MODULE_DESCRIPTION("Analog Devices AD9739 DAC");
 468 MODULE_LICENSE("GPL");
 469 MODULE_IMPORT_NS("IIO_BACKEND");