drivers/mfd/intel_soc_pmic_mrfld.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Device access for Basin Cove PMIC
   4  *
   5  * Copyright (c) 2019, Intel Corporation.
   6  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
   7  */
   8
   9 #include <linux/acpi.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/mfd/core.h>
  12 #include <linux/mfd/intel_soc_pmic.h>
  13 #include <linux/mfd/intel_soc_pmic_mrfld.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_data/x86/intel_scu_ipc.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/regmap.h>
  18
  19 /*
  20  * Level 2 IRQs
  21  *
  22  * Firmware on the systems with Basin Cove PMIC services Level 1 IRQs
  23  * without an assistance. Thus, each of the Level 1 IRQ is represented
  24  * as a separate RTE in IOAPIC.
  25  */
  26 static struct resource irq_level2_resources[] = {
  27         DEFINE_RES_IRQ(0), /* power button */
  28         DEFINE_RES_IRQ(0), /* TMU */
  29         DEFINE_RES_IRQ(0), /* thermal */
  30         DEFINE_RES_IRQ(0), /* BCU */
  31         DEFINE_RES_IRQ(0), /* ADC */
  32         DEFINE_RES_IRQ(0), /* charger */
  33         DEFINE_RES_IRQ(0), /* GPIO */
  34 };
  35
  36 static const struct mfd_cell bcove_dev[] = {
  37         {
  38                 .name = "mrfld_bcove_pwrbtn",
  39                 .num_resources = 1,
  40                 .resources = &irq_level2_resources[0],
  41         }, {
  42                 .name = "mrfld_bcove_tmu",
  43                 .num_resources = 1,
  44                 .resources = &irq_level2_resources[1],
  45         }, {
  46                 .name = "mrfld_bcove_thermal",
  47                 .num_resources = 1,
  48                 .resources = &irq_level2_resources[2],
  49         }, {
  50                 .name = "mrfld_bcove_bcu",
  51                 .num_resources = 1,
  52                 .resources = &irq_level2_resources[3],
  53         }, {
  54                 .name = "mrfld_bcove_adc",
  55                 .num_resources = 1,
  56                 .resources = &irq_level2_resources[4],
  57         }, {
  58                 .name = "mrfld_bcove_charger",
  59                 .num_resources = 1,
  60                 .resources = &irq_level2_resources[5],
  61         }, {
  62                 .name = "mrfld_bcove_pwrsrc",
  63                 .num_resources = 1,
  64                 .resources = &irq_level2_resources[5],
  65         }, {
  66                 .name = "mrfld_bcove_gpio",
  67                 .num_resources = 1,
  68                 .resources = &irq_level2_resources[6],
  69         },
  70         {       .name = "mrfld_bcove_region", },
  71 };
  72
  73 static int bcove_ipc_byte_reg_read(void *context, unsigned int reg,
  74                                     unsigned int *val)
  75 {
  76         struct intel_soc_pmic *pmic = context;
  77         u8 ipc_out;
  78         int ret;
  79
  80         ret = intel_scu_ipc_dev_ioread8(pmic->scu, reg, &ipc_out);
  81         if (ret)
  82                 return ret;
  83
  84         *val = ipc_out;
  85         return 0;
  86 }
  87
  88 static int bcove_ipc_byte_reg_write(void *context, unsigned int reg,
  89                                      unsigned int val)
  90 {
  91         struct intel_soc_pmic *pmic = context;
  92         u8 ipc_in = val;
  93
  94         return intel_scu_ipc_dev_iowrite8(pmic->scu, reg, ipc_in);
  95 }
  96
  97 static const struct regmap_config bcove_regmap_config = {
  98         .reg_bits = 16,
  99         .val_bits = 8,
 100         .max_register = 0xff,
 101         .reg_write = bcove_ipc_byte_reg_write,
 102         .reg_read = bcove_ipc_byte_reg_read,
 103 };
 104
 105 static int bcove_probe(struct platform_device *pdev)
 106 {
 107         struct device *dev = &pdev->dev;
 108         struct intel_soc_pmic *pmic;
 109         unsigned int i;
 110         int ret;
 111
 112         pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
 113         if (!pmic)
 114                 return -ENOMEM;
 115
 116         pmic->scu = devm_intel_scu_ipc_dev_get(dev);
 117         if (!pmic->scu)
 118                 return -ENOMEM;
 119
 120         platform_set_drvdata(pdev, pmic);
 121         pmic->dev = &pdev->dev;
 122
 123         pmic->regmap = devm_regmap_init(dev, NULL, pmic, &bcove_regmap_config);
 124         if (IS_ERR(pmic->regmap))
 125                 return PTR_ERR(pmic->regmap);
 126
 127         for (i = 0; i < ARRAY_SIZE(irq_level2_resources); i++) {
 128                 ret = platform_get_irq(pdev, i);
 129                 if (ret < 0)
 130                         return ret;
 131
 132                 irq_level2_resources[i].start = ret;
 133                 irq_level2_resources[i].end = ret;
 134         }
 135
 136         return devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
 137                                     bcove_dev, ARRAY_SIZE(bcove_dev),
 138                                     NULL, 0, NULL);
 139 }
 140
 141 static const struct acpi_device_id bcove_acpi_ids[] = {
 142         { "INTC100E" },
 143         {}
 144 };
 145 MODULE_DEVICE_TABLE(acpi, bcove_acpi_ids);
 146
 147 static struct platform_driver bcove_driver = {
 148         .driver = {
 149                 .name = "intel_soc_pmic_mrfld",
 150                 .acpi_match_table = bcove_acpi_ids,
 151         },
 152         .probe = bcove_probe,
 153 };
 154 module_platform_driver(bcove_driver);
 155
 156 MODULE_DESCRIPTION("IPC driver for Intel SoC Basin Cove PMIC");
 157 MODULE_LICENSE("GPL v2");