drivers/mfd/stm32-timers.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2016
   4  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
   5  */
   6
   7 #include <linux/bitfield.h>
   8 #include <linux/mfd/stm32-timers.h>
   9 #include <linux/module.h>
  10 #include <linux/of_platform.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/reset.h>
  13
  14 #define STM32_TIMERS_MAX_REGISTERS      0x3fc
  15
  16 /* DIER register DMA enable bits */
  17 static const u32 stm32_timers_dier_dmaen[STM32_TIMERS_MAX_DMAS] = {
  18         TIM_DIER_CC1DE,
  19         TIM_DIER_CC2DE,
  20         TIM_DIER_CC3DE,
  21         TIM_DIER_CC4DE,
  22         TIM_DIER_UIE,
  23         TIM_DIER_TDE,
  24         TIM_DIER_COMDE
  25 };
  26
  27 static void stm32_timers_dma_done(void *p)
  28 {
  29         struct stm32_timers_dma *dma = p;
  30         struct dma_tx_state state;
  31         enum dma_status status;
  32
  33         status = dmaengine_tx_status(dma->chan, dma->chan->cookie, &state);
  34         if (status == DMA_COMPLETE)
  35                 complete(&dma->completion);
  36 }
  37
  38 /**
  39  * stm32_timers_dma_burst_read - Read from timers registers using DMA.
  40  *
  41  * Read from STM32 timers registers using DMA on a single event.
  42  * @dev: reference to stm32_timers MFD device
  43  * @buf: DMA'able destination buffer
  44  * @id: stm32_timers_dmas event identifier (ch[1..4], up, trig or com)
  45  * @reg: registers start offset for DMA to read from (like CCRx for capture)
  46  * @num_reg: number of registers to read upon each DMA request, starting @reg.
  47  * @bursts: number of bursts to read (e.g. like two for pwm period capture)
  48  * @tmo_ms: timeout (milliseconds)
  49  */
  50 int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
  51                                 enum stm32_timers_dmas id, u32 reg,
  52                                 unsigned int num_reg, unsigned int bursts,
  53                                 unsigned long tmo_ms)
  54 {
  55         struct stm32_timers *ddata = dev_get_drvdata(dev);
  56         unsigned long timeout = msecs_to_jiffies(tmo_ms);
  57         struct regmap *regmap = ddata->regmap;
  58         struct stm32_timers_dma *dma = &ddata->dma;
  59         size_t len = num_reg * bursts * sizeof(u32);
  60         struct dma_async_tx_descriptor *desc;
  61         struct dma_slave_config config;
  62         dma_cookie_t cookie;
  63         dma_addr_t dma_buf;
  64         u32 dbl, dba;
  65         long err;
  66         int ret;
  67
  68         /* Sanity check */
  69         if (id < STM32_TIMERS_DMA_CH1 || id >= STM32_TIMERS_MAX_DMAS)
  70                 return -EINVAL;
  71
  72         if (!num_reg || !bursts || reg > STM32_TIMERS_MAX_REGISTERS ||
  73             (reg + num_reg * sizeof(u32)) > STM32_TIMERS_MAX_REGISTERS)
  74                 return -EINVAL;
  75
  76         if (!dma->chans[id])
  77                 return -ENODEV;
  78         mutex_lock(&dma->lock);
  79
  80         /* Select DMA channel in use */
  81         dma->chan = dma->chans[id];
  82         dma_buf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE);
  83         if (dma_mapping_error(dev, dma_buf)) {
  84                 ret = -ENOMEM;
  85                 goto unlock;
  86         }
  87
  88         /* Prepare DMA read from timer registers, using DMA burst mode */
  89         memset(&config, 0, sizeof(config));
  90         config.src_addr = (dma_addr_t)dma->phys_base + TIM_DMAR;
  91         config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
  92         ret = dmaengine_slave_config(dma->chan, &config);
  93         if (ret)
  94                 goto unmap;
  95
  96         desc = dmaengine_prep_slave_single(dma->chan, dma_buf, len,
  97                                            DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
  98         if (!desc) {
  99                 ret = -EBUSY;
 100                 goto unmap;
 101         }
 102
 103         desc->callback = stm32_timers_dma_done;
 104         desc->callback_param = dma;
 105         cookie = dmaengine_submit(desc);
 106         ret = dma_submit_error(cookie);
 107         if (ret)
 108                 goto dma_term;
 109
 110         reinit_completion(&dma->completion);
 111         dma_async_issue_pending(dma->chan);
 112
 113         /* Setup and enable timer DMA burst mode */
 114         dbl = FIELD_PREP(TIM_DCR_DBL, bursts - 1);
 115         dba = FIELD_PREP(TIM_DCR_DBA, reg >> 2);
 116         ret = regmap_write(regmap, TIM_DCR, dbl | dba);
 117         if (ret)
 118                 goto dma_term;
 119
 120         /* Clear pending flags before enabling DMA request */
 121         ret = regmap_write(regmap, TIM_SR, 0);
 122         if (ret)
 123                 goto dcr_clr;
 124
 125         ret = regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id],
 126                                  stm32_timers_dier_dmaen[id]);
 127         if (ret)
 128                 goto dcr_clr;
 129
 130         err = wait_for_completion_interruptible_timeout(&dma->completion,
 131                                                         timeout);
 132         if (err == 0)
 133                 ret = -ETIMEDOUT;
 134         else if (err < 0)
 135                 ret = err;
 136
 137         regmap_update_bits(regmap, TIM_DIER, stm32_timers_dier_dmaen[id], 0);
 138         regmap_write(regmap, TIM_SR, 0);
 139 dcr_clr:
 140         regmap_write(regmap, TIM_DCR, 0);
 141 dma_term:
 142         dmaengine_terminate_all(dma->chan);
 143 unmap:
 144         dma_unmap_single(dev, dma_buf, len, DMA_FROM_DEVICE);
 145 unlock:
 146         dma->chan = NULL;
 147         mutex_unlock(&dma->lock);
 148
 149         return ret;
 150 }
 151 EXPORT_SYMBOL_GPL(stm32_timers_dma_burst_read);
 152
 153 static const struct regmap_config stm32_timers_regmap_cfg = {
 154         .reg_bits = 32,
 155         .val_bits = 32,
 156         .reg_stride = sizeof(u32),
 157         .max_register = STM32_TIMERS_MAX_REGISTERS,
 158 };
 159
 160 static void stm32_timers_get_arr_size(struct stm32_timers *ddata)
 161 {
 162         u32 arr;
 163
 164         /* Backup ARR to restore it after getting the maximum value */
 165         regmap_read(ddata->regmap, TIM_ARR, &arr);
 166
 167         /*
 168          * Only the available bits will be written so when readback
 169          * we get the maximum value of auto reload register
 170          */
 171         regmap_write(ddata->regmap, TIM_ARR, ~0L);
 172         regmap_read(ddata->regmap, TIM_ARR, &ddata->max_arr);
 173         regmap_write(ddata->regmap, TIM_ARR, arr);
 174 }
 175
 176 static int stm32_timers_dma_probe(struct device *dev,
 177                                    struct stm32_timers *ddata)
 178 {
 179         int i;
 180         int ret = 0;
 181         char name[4];
 182
 183         init_completion(&ddata->dma.completion);
 184         mutex_init(&ddata->dma.lock);
 185
 186         /* Optional DMA support: get valid DMA channel(s) or NULL */
 187         for (i = STM32_TIMERS_DMA_CH1; i <= STM32_TIMERS_DMA_CH4; i++) {
 188                 snprintf(name, ARRAY_SIZE(name), "ch%1d", i + 1);
 189                 ddata->dma.chans[i] = dma_request_chan(dev, name);
 190         }
 191         ddata->dma.chans[STM32_TIMERS_DMA_UP] = dma_request_chan(dev, "up");
 192         ddata->dma.chans[STM32_TIMERS_DMA_TRIG] = dma_request_chan(dev, "trig");
 193         ddata->dma.chans[STM32_TIMERS_DMA_COM] = dma_request_chan(dev, "com");
 194
 195         for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++) {
 196                 if (IS_ERR(ddata->dma.chans[i])) {
 197                         /* Save the first error code to return */
 198                         if (PTR_ERR(ddata->dma.chans[i]) != -ENODEV && !ret)
 199                                 ret = PTR_ERR(ddata->dma.chans[i]);
 200
 201                         ddata->dma.chans[i] = NULL;
 202                 }
 203         }
 204
 205         return ret;
 206 }
 207
 208 static void stm32_timers_dma_remove(struct device *dev,
 209                                     struct stm32_timers *ddata)
 210 {
 211         int i;
 212
 213         for (i = STM32_TIMERS_DMA_CH1; i < STM32_TIMERS_MAX_DMAS; i++)
 214                 if (ddata->dma.chans[i])
 215                         dma_release_channel(ddata->dma.chans[i]);
 216 }
 217
 218 static const char * const stm32_timers_irq_name[STM32_TIMERS_MAX_IRQS] = {
 219         "brk", "up", "trg-com", "cc"
 220 };
 221
 222 static int stm32_timers_irq_probe(struct platform_device *pdev,
 223                                   struct stm32_timers *ddata)
 224 {
 225         int i, ret;
 226
 227         /*
 228          * STM32 Timer may have either:
 229          * - a unique global interrupt line
 230          * - four dedicated interrupt lines that may be handled separately.
 231          * Optionally get them here, to be used by child devices.
 232          */
 233         ret = platform_get_irq_byname_optional(pdev, "global");
 234         if (ret < 0 && ret != -ENXIO) {
 235                 return ret;
 236         } else if (ret != -ENXIO) {
 237                 ddata->irq[STM32_TIMERS_IRQ_GLOBAL_BRK] = ret;
 238                 ddata->nr_irqs = 1;
 239                 return 0;
 240         }
 241
 242         for (i = 0; i < STM32_TIMERS_MAX_IRQS; i++) {
 243                 ret = platform_get_irq_byname_optional(pdev, stm32_timers_irq_name[i]);
 244                 if (ret < 0 && ret != -ENXIO) {
 245                         return ret;
 246                 } else if (ret != -ENXIO) {
 247                         ddata->irq[i] = ret;
 248                         ddata->nr_irqs++;
 249                 }
 250         }
 251
 252         if (ddata->nr_irqs && ddata->nr_irqs != STM32_TIMERS_MAX_IRQS) {
 253                 dev_err(&pdev->dev, "Invalid number of IRQs %d\n", ddata->nr_irqs);
 254                 return -EINVAL;
 255         }
 256
 257         return 0;
 258 }
 259
 260 static int stm32_timers_probe(struct platform_device *pdev)
 261 {
 262         struct device *dev = &pdev->dev;
 263         struct stm32_timers *ddata;
 264         struct resource *res;
 265         void __iomem *mmio;
 266         int ret;
 267
 268         ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
 269         if (!ddata)
 270                 return -ENOMEM;
 271
 272         mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
 273         if (IS_ERR(mmio))
 274                 return PTR_ERR(mmio);
 275
 276         /* Timer physical addr for DMA */
 277         ddata->dma.phys_base = res->start;
 278
 279         ddata->regmap = devm_regmap_init_mmio_clk(dev, "int", mmio,
 280                                                   &stm32_timers_regmap_cfg);
 281         if (IS_ERR(ddata->regmap))
 282                 return PTR_ERR(ddata->regmap);
 283
 284         ddata->clk = devm_clk_get(dev, NULL);
 285         if (IS_ERR(ddata->clk))
 286                 return PTR_ERR(ddata->clk);
 287
 288         stm32_timers_get_arr_size(ddata);
 289
 290         ret = stm32_timers_irq_probe(pdev, ddata);
 291         if (ret)
 292                 return ret;
 293
 294         ret = stm32_timers_dma_probe(dev, ddata);
 295         if (ret) {
 296                 stm32_timers_dma_remove(dev, ddata);
 297                 return ret;
 298         }
 299
 300         platform_set_drvdata(pdev, ddata);
 301
 302         ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
 303         if (ret)
 304                 stm32_timers_dma_remove(dev, ddata);
 305
 306         return ret;
 307 }
 308
 309 static void stm32_timers_remove(struct platform_device *pdev)
 310 {
 311         struct stm32_timers *ddata = platform_get_drvdata(pdev);
 312
 313         /*
 314          * Don't use devm_ here: enfore of_platform_depopulate() happens before
 315          * DMA are released, to avoid race on DMA.
 316          */
 317         of_platform_depopulate(&pdev->dev);
 318         stm32_timers_dma_remove(&pdev->dev, ddata);
 319 }
 320
 321 static const struct of_device_id stm32_timers_of_match[] = {
 322         { .compatible = "st,stm32-timers", },
 323         { /* end node */ },
 324 };
 325 MODULE_DEVICE_TABLE(of, stm32_timers_of_match);
 326
 327 static struct platform_driver stm32_timers_driver = {
 328         .probe = stm32_timers_probe,
 329         .remove = stm32_timers_remove,
 330         .driver = {
 331                 .name = "stm32-timers",
 332                 .of_match_table = stm32_timers_of_match,
 333         },
 334 };
 335 module_platform_driver(stm32_timers_driver);
 336
 337 MODULE_DESCRIPTION("STMicroelectronics STM32 Timers");
 338 MODULE_LICENSE("GPL v2");