drivers/mfd/tps6594-core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Core functions for TI TPS65224/TPS6594/TPS6593/LP8764 PMICs
   4  *
   5  * Copyright (C) 2023 BayLibre Incorporated - https://www.baylibre.com/
   6  */
   7
   8 #include <linux/completion.h>
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13
  14 #include <linux/mfd/core.h>
  15 #include <linux/mfd/tps6594.h>
  16
  17 #define TPS6594_CRC_SYNC_TIMEOUT_MS 150
  18
  19 /* Completion to synchronize CRC feature enabling on all PMICs */
  20 static DECLARE_COMPLETION(tps6594_crc_comp);
  21
  22 static const struct resource tps6594_regulator_resources[] = {
  23         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_OV, TPS6594_IRQ_NAME_BUCK1_OV),
  24         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_UV, TPS6594_IRQ_NAME_BUCK1_UV),
  25         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_SC, TPS6594_IRQ_NAME_BUCK1_SC),
  26         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK1_ILIM, TPS6594_IRQ_NAME_BUCK1_ILIM),
  27         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_OV, TPS6594_IRQ_NAME_BUCK2_OV),
  28         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_UV, TPS6594_IRQ_NAME_BUCK2_UV),
  29         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_SC, TPS6594_IRQ_NAME_BUCK2_SC),
  30         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK2_ILIM, TPS6594_IRQ_NAME_BUCK2_ILIM),
  31         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_OV, TPS6594_IRQ_NAME_BUCK3_OV),
  32         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_UV, TPS6594_IRQ_NAME_BUCK3_UV),
  33         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_SC, TPS6594_IRQ_NAME_BUCK3_SC),
  34         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK3_ILIM, TPS6594_IRQ_NAME_BUCK3_ILIM),
  35         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_OV, TPS6594_IRQ_NAME_BUCK4_OV),
  36         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_UV, TPS6594_IRQ_NAME_BUCK4_UV),
  37         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_SC, TPS6594_IRQ_NAME_BUCK4_SC),
  38         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK4_ILIM, TPS6594_IRQ_NAME_BUCK4_ILIM),
  39         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_OV, TPS6594_IRQ_NAME_BUCK5_OV),
  40         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_UV, TPS6594_IRQ_NAME_BUCK5_UV),
  41         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_SC, TPS6594_IRQ_NAME_BUCK5_SC),
  42         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BUCK5_ILIM, TPS6594_IRQ_NAME_BUCK5_ILIM),
  43         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_OV, TPS6594_IRQ_NAME_LDO1_OV),
  44         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_UV, TPS6594_IRQ_NAME_LDO1_UV),
  45         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_SC, TPS6594_IRQ_NAME_LDO1_SC),
  46         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO1_ILIM, TPS6594_IRQ_NAME_LDO1_ILIM),
  47         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_OV, TPS6594_IRQ_NAME_LDO2_OV),
  48         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_UV, TPS6594_IRQ_NAME_LDO2_UV),
  49         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_SC, TPS6594_IRQ_NAME_LDO2_SC),
  50         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO2_ILIM, TPS6594_IRQ_NAME_LDO2_ILIM),
  51         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_OV, TPS6594_IRQ_NAME_LDO3_OV),
  52         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_UV, TPS6594_IRQ_NAME_LDO3_UV),
  53         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_SC, TPS6594_IRQ_NAME_LDO3_SC),
  54         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO3_ILIM, TPS6594_IRQ_NAME_LDO3_ILIM),
  55         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_OV, TPS6594_IRQ_NAME_LDO4_OV),
  56         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_UV, TPS6594_IRQ_NAME_LDO4_UV),
  57         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_SC, TPS6594_IRQ_NAME_LDO4_SC),
  58         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_LDO4_ILIM, TPS6594_IRQ_NAME_LDO4_ILIM),
  59         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_OV, TPS6594_IRQ_NAME_VCCA_OV),
  60         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_UV, TPS6594_IRQ_NAME_VCCA_UV),
  61         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_OV, TPS6594_IRQ_NAME_VMON1_OV),
  62         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_UV, TPS6594_IRQ_NAME_VMON1_UV),
  63         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON1_RV, TPS6594_IRQ_NAME_VMON1_RV),
  64         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_OV, TPS6594_IRQ_NAME_VMON2_OV),
  65         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_UV, TPS6594_IRQ_NAME_VMON2_UV),
  66         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VMON2_RV, TPS6594_IRQ_NAME_VMON2_RV),
  67 };
  68
  69 static const struct resource tps6594_pinctrl_resources[] = {
  70         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO9, TPS6594_IRQ_NAME_GPIO9),
  71         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO10, TPS6594_IRQ_NAME_GPIO10),
  72         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO11, TPS6594_IRQ_NAME_GPIO11),
  73         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO1, TPS6594_IRQ_NAME_GPIO1),
  74         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO2, TPS6594_IRQ_NAME_GPIO2),
  75         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO3, TPS6594_IRQ_NAME_GPIO3),
  76         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO4, TPS6594_IRQ_NAME_GPIO4),
  77         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO5, TPS6594_IRQ_NAME_GPIO5),
  78         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO6, TPS6594_IRQ_NAME_GPIO6),
  79         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO7, TPS6594_IRQ_NAME_GPIO7),
  80         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_GPIO8, TPS6594_IRQ_NAME_GPIO8),
  81 };
  82
  83 static const struct resource tps6594_pfsm_resources[] = {
  84         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NPWRON_START, TPS6594_IRQ_NAME_NPWRON_START),
  85         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ENABLE, TPS6594_IRQ_NAME_ENABLE),
  86         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_FSD, TPS6594_IRQ_NAME_FSD),
  87         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SOFT_REBOOT, TPS6594_IRQ_NAME_SOFT_REBOOT),
  88         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BIST_PASS, TPS6594_IRQ_NAME_BIST_PASS),
  89         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_EXT_CLK, TPS6594_IRQ_NAME_EXT_CLK),
  90         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TWARN, TPS6594_IRQ_NAME_TWARN),
  91         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TSD_ORD, TPS6594_IRQ_NAME_TSD_ORD),
  92         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_BIST_FAIL, TPS6594_IRQ_NAME_BIST_FAIL),
  93         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_REG_CRC_ERR, TPS6594_IRQ_NAME_REG_CRC_ERR),
  94         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_RECOV_CNT, TPS6594_IRQ_NAME_RECOV_CNT),
  95         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SPMI_ERR, TPS6594_IRQ_NAME_SPMI_ERR),
  96         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NPWRON_LONG, TPS6594_IRQ_NAME_NPWRON_LONG),
  97         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NINT_READBACK, TPS6594_IRQ_NAME_NINT_READBACK),
  98         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NRSTOUT_READBACK, TPS6594_IRQ_NAME_NRSTOUT_READBACK),
  99         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TSD_IMM, TPS6594_IRQ_NAME_TSD_IMM),
 100         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_VCCA_OVP, TPS6594_IRQ_NAME_VCCA_OVP),
 101         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_PFSM_ERR, TPS6594_IRQ_NAME_PFSM_ERR),
 102         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_IMM_SHUTDOWN, TPS6594_IRQ_NAME_IMM_SHUTDOWN),
 103         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ORD_SHUTDOWN, TPS6594_IRQ_NAME_ORD_SHUTDOWN),
 104         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_MCU_PWR_ERR, TPS6594_IRQ_NAME_MCU_PWR_ERR),
 105         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_SOC_PWR_ERR, TPS6594_IRQ_NAME_SOC_PWR_ERR),
 106         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_FRM_ERR, TPS6594_IRQ_NAME_COMM_FRM_ERR),
 107         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_CRC_ERR, TPS6594_IRQ_NAME_COMM_CRC_ERR),
 108         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_COMM_ADR_ERR, TPS6594_IRQ_NAME_COMM_ADR_ERR),
 109         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_EN_DRV_READBACK, TPS6594_IRQ_NAME_EN_DRV_READBACK),
 110         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_NRSTOUT_SOC_READBACK,
 111                              TPS6594_IRQ_NAME_NRSTOUT_SOC_READBACK),
 112 };
 113
 114 static const struct resource tps6594_esm_resources[] = {
 115         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_PIN, TPS6594_IRQ_NAME_ESM_SOC_PIN),
 116         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_FAIL, TPS6594_IRQ_NAME_ESM_SOC_FAIL),
 117         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ESM_SOC_RST, TPS6594_IRQ_NAME_ESM_SOC_RST),
 118 };
 119
 120 static const struct resource tps6594_rtc_resources[] = {
 121         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_TIMER, TPS6594_IRQ_NAME_TIMER),
 122         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_ALARM, TPS6594_IRQ_NAME_ALARM),
 123         DEFINE_RES_IRQ_NAMED(TPS6594_IRQ_POWER_UP, TPS6594_IRQ_NAME_POWERUP),
 124 };
 125
 126 static const struct mfd_cell tps6594_common_cells[] = {
 127         MFD_CELL_RES("tps6594-regulator", tps6594_regulator_resources),
 128         MFD_CELL_RES("tps6594-pinctrl", tps6594_pinctrl_resources),
 129         MFD_CELL_RES("tps6594-pfsm", tps6594_pfsm_resources),
 130         MFD_CELL_RES("tps6594-esm", tps6594_esm_resources),
 131 };
 132
 133 static const struct mfd_cell tps6594_rtc_cells[] = {
 134         MFD_CELL_RES("tps6594-rtc", tps6594_rtc_resources),
 135 };
 136
 137 static const struct regmap_irq tps6594_irqs[] = {
 138         /* INT_BUCK1_2 register */
 139         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_OV, 0, TPS6594_BIT_BUCKX_OV_INT(0)),
 140         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_UV, 0, TPS6594_BIT_BUCKX_UV_INT(0)),
 141         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_SC, 0, TPS6594_BIT_BUCKX_SC_INT(0)),
 142         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK1_ILIM, 0, TPS6594_BIT_BUCKX_ILIM_INT(0)),
 143         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_OV, 0, TPS6594_BIT_BUCKX_OV_INT(1)),
 144         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_UV, 0, TPS6594_BIT_BUCKX_UV_INT(1)),
 145         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_SC, 0, TPS6594_BIT_BUCKX_SC_INT(1)),
 146         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK2_ILIM, 0, TPS6594_BIT_BUCKX_ILIM_INT(1)),
 147
 148         /* INT_BUCK3_4 register */
 149         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_OV, 1, TPS6594_BIT_BUCKX_OV_INT(2)),
 150         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_UV, 1, TPS6594_BIT_BUCKX_UV_INT(2)),
 151         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_SC, 1, TPS6594_BIT_BUCKX_SC_INT(2)),
 152         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK3_ILIM, 1, TPS6594_BIT_BUCKX_ILIM_INT(2)),
 153         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_OV, 1, TPS6594_BIT_BUCKX_OV_INT(3)),
 154         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_UV, 1, TPS6594_BIT_BUCKX_UV_INT(3)),
 155         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_SC, 1, TPS6594_BIT_BUCKX_SC_INT(3)),
 156         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK4_ILIM, 1, TPS6594_BIT_BUCKX_ILIM_INT(3)),
 157
 158         /* INT_BUCK5 register */
 159         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_OV, 2, TPS6594_BIT_BUCKX_OV_INT(4)),
 160         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_UV, 2, TPS6594_BIT_BUCKX_UV_INT(4)),
 161         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_SC, 2, TPS6594_BIT_BUCKX_SC_INT(4)),
 162         REGMAP_IRQ_REG(TPS6594_IRQ_BUCK5_ILIM, 2, TPS6594_BIT_BUCKX_ILIM_INT(4)),
 163
 164         /* INT_LDO1_2 register */
 165         REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_OV, 3, TPS6594_BIT_LDOX_OV_INT(0)),
 166         REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_UV, 3, TPS6594_BIT_LDOX_UV_INT(0)),
 167         REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_SC, 3, TPS6594_BIT_LDOX_SC_INT(0)),
 168         REGMAP_IRQ_REG(TPS6594_IRQ_LDO1_ILIM, 3, TPS6594_BIT_LDOX_ILIM_INT(0)),
 169         REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_OV, 3, TPS6594_BIT_LDOX_OV_INT(1)),
 170         REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_UV, 3, TPS6594_BIT_LDOX_UV_INT(1)),
 171         REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_SC, 3, TPS6594_BIT_LDOX_SC_INT(1)),
 172         REGMAP_IRQ_REG(TPS6594_IRQ_LDO2_ILIM, 3, TPS6594_BIT_LDOX_ILIM_INT(1)),
 173
 174         /* INT_LDO3_4 register */
 175         REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_OV, 4, TPS6594_BIT_LDOX_OV_INT(2)),
 176         REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_UV, 4, TPS6594_BIT_LDOX_UV_INT(2)),
 177         REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_SC, 4, TPS6594_BIT_LDOX_SC_INT(2)),
 178         REGMAP_IRQ_REG(TPS6594_IRQ_LDO3_ILIM, 4, TPS6594_BIT_LDOX_ILIM_INT(2)),
 179         REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_OV, 4, TPS6594_BIT_LDOX_OV_INT(3)),
 180         REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_UV, 4, TPS6594_BIT_LDOX_UV_INT(3)),
 181         REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_SC, 4, TPS6594_BIT_LDOX_SC_INT(3)),
 182         REGMAP_IRQ_REG(TPS6594_IRQ_LDO4_ILIM, 4, TPS6594_BIT_LDOX_ILIM_INT(3)),
 183
 184         /* INT_VMON register */
 185         REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_OV, 5, TPS6594_BIT_VCCA_OV_INT),
 186         REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_UV, 5, TPS6594_BIT_VCCA_UV_INT),
 187         REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_OV, 5, TPS6594_BIT_VMON1_OV_INT),
 188         REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_UV, 5, TPS6594_BIT_VMON1_UV_INT),
 189         REGMAP_IRQ_REG(TPS6594_IRQ_VMON1_RV, 5, TPS6594_BIT_VMON1_RV_INT),
 190         REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_OV, 5, TPS6594_BIT_VMON2_OV_INT),
 191         REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_UV, 5, TPS6594_BIT_VMON2_UV_INT),
 192         REGMAP_IRQ_REG(TPS6594_IRQ_VMON2_RV, 5, TPS6594_BIT_VMON2_RV_INT),
 193
 194         /* INT_GPIO register */
 195         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO9, 6, TPS6594_BIT_GPIO9_INT),
 196         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO10, 6, TPS6594_BIT_GPIO10_INT),
 197         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO11, 6, TPS6594_BIT_GPIO11_INT),
 198
 199         /* INT_GPIO1_8 register */
 200         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO1, 7, TPS6594_BIT_GPIOX_INT(0)),
 201         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO2, 7, TPS6594_BIT_GPIOX_INT(1)),
 202         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO3, 7, TPS6594_BIT_GPIOX_INT(2)),
 203         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO4, 7, TPS6594_BIT_GPIOX_INT(3)),
 204         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO5, 7, TPS6594_BIT_GPIOX_INT(4)),
 205         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO6, 7, TPS6594_BIT_GPIOX_INT(5)),
 206         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO7, 7, TPS6594_BIT_GPIOX_INT(6)),
 207         REGMAP_IRQ_REG(TPS6594_IRQ_GPIO8, 7, TPS6594_BIT_GPIOX_INT(7)),
 208
 209         /* INT_STARTUP register */
 210         REGMAP_IRQ_REG(TPS6594_IRQ_NPWRON_START, 8, TPS6594_BIT_NPWRON_START_INT),
 211         REGMAP_IRQ_REG(TPS6594_IRQ_ENABLE, 8, TPS6594_BIT_ENABLE_INT),
 212         REGMAP_IRQ_REG(TPS6594_IRQ_FSD, 8, TPS6594_BIT_FSD_INT),
 213         REGMAP_IRQ_REG(TPS6594_IRQ_SOFT_REBOOT, 8, TPS6594_BIT_SOFT_REBOOT_INT),
 214
 215         /* INT_MISC register */
 216         REGMAP_IRQ_REG(TPS6594_IRQ_BIST_PASS, 9, TPS6594_BIT_BIST_PASS_INT),
 217         REGMAP_IRQ_REG(TPS6594_IRQ_EXT_CLK, 9, TPS6594_BIT_EXT_CLK_INT),
 218         REGMAP_IRQ_REG(TPS6594_IRQ_TWARN, 9, TPS6594_BIT_TWARN_INT),
 219
 220         /* INT_MODERATE_ERR register */
 221         REGMAP_IRQ_REG(TPS6594_IRQ_TSD_ORD, 10, TPS6594_BIT_TSD_ORD_INT),
 222         REGMAP_IRQ_REG(TPS6594_IRQ_BIST_FAIL, 10, TPS6594_BIT_BIST_FAIL_INT),
 223         REGMAP_IRQ_REG(TPS6594_IRQ_REG_CRC_ERR, 10, TPS6594_BIT_REG_CRC_ERR_INT),
 224         REGMAP_IRQ_REG(TPS6594_IRQ_RECOV_CNT, 10, TPS6594_BIT_RECOV_CNT_INT),
 225         REGMAP_IRQ_REG(TPS6594_IRQ_SPMI_ERR, 10, TPS6594_BIT_SPMI_ERR_INT),
 226         REGMAP_IRQ_REG(TPS6594_IRQ_NPWRON_LONG, 10, TPS6594_BIT_NPWRON_LONG_INT),
 227         REGMAP_IRQ_REG(TPS6594_IRQ_NINT_READBACK, 10, TPS6594_BIT_NINT_READBACK_INT),
 228         REGMAP_IRQ_REG(TPS6594_IRQ_NRSTOUT_READBACK, 10, TPS6594_BIT_NRSTOUT_READBACK_INT),
 229
 230         /* INT_SEVERE_ERR register */
 231         REGMAP_IRQ_REG(TPS6594_IRQ_TSD_IMM, 11, TPS6594_BIT_TSD_IMM_INT),
 232         REGMAP_IRQ_REG(TPS6594_IRQ_VCCA_OVP, 11, TPS6594_BIT_VCCA_OVP_INT),
 233         REGMAP_IRQ_REG(TPS6594_IRQ_PFSM_ERR, 11, TPS6594_BIT_PFSM_ERR_INT),
 234
 235         /* INT_FSM_ERR register */
 236         REGMAP_IRQ_REG(TPS6594_IRQ_IMM_SHUTDOWN, 12, TPS6594_BIT_IMM_SHUTDOWN_INT),
 237         REGMAP_IRQ_REG(TPS6594_IRQ_ORD_SHUTDOWN, 12, TPS6594_BIT_ORD_SHUTDOWN_INT),
 238         REGMAP_IRQ_REG(TPS6594_IRQ_MCU_PWR_ERR, 12, TPS6594_BIT_MCU_PWR_ERR_INT),
 239         REGMAP_IRQ_REG(TPS6594_IRQ_SOC_PWR_ERR, 12, TPS6594_BIT_SOC_PWR_ERR_INT),
 240
 241         /* INT_COMM_ERR register */
 242         REGMAP_IRQ_REG(TPS6594_IRQ_COMM_FRM_ERR, 13, TPS6594_BIT_COMM_FRM_ERR_INT),
 243         REGMAP_IRQ_REG(TPS6594_IRQ_COMM_CRC_ERR, 13, TPS6594_BIT_COMM_CRC_ERR_INT),
 244         REGMAP_IRQ_REG(TPS6594_IRQ_COMM_ADR_ERR, 13, TPS6594_BIT_COMM_ADR_ERR_INT),
 245
 246         /* INT_READBACK_ERR register */
 247         REGMAP_IRQ_REG(TPS6594_IRQ_EN_DRV_READBACK, 14, TPS6594_BIT_EN_DRV_READBACK_INT),
 248         REGMAP_IRQ_REG(TPS6594_IRQ_NRSTOUT_SOC_READBACK, 14, TPS6594_BIT_NRSTOUT_SOC_READBACK_INT),
 249
 250         /* INT_ESM register */
 251         REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_PIN, 15, TPS6594_BIT_ESM_SOC_PIN_INT),
 252         REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_FAIL, 15, TPS6594_BIT_ESM_SOC_FAIL_INT),
 253         REGMAP_IRQ_REG(TPS6594_IRQ_ESM_SOC_RST, 15, TPS6594_BIT_ESM_SOC_RST_INT),
 254
 255         /* RTC_STATUS register */
 256         REGMAP_IRQ_REG(TPS6594_IRQ_TIMER, 16, TPS6594_BIT_TIMER),
 257         REGMAP_IRQ_REG(TPS6594_IRQ_ALARM, 16, TPS6594_BIT_ALARM),
 258         REGMAP_IRQ_REG(TPS6594_IRQ_POWER_UP, 16, TPS6594_BIT_POWER_UP),
 259 };
 260
 261 static const unsigned int tps6594_irq_reg[] = {
 262         TPS6594_REG_INT_BUCK1_2,
 263         TPS6594_REG_INT_BUCK3_4,
 264         TPS6594_REG_INT_BUCK5,
 265         TPS6594_REG_INT_LDO1_2,
 266         TPS6594_REG_INT_LDO3_4,
 267         TPS6594_REG_INT_VMON,
 268         TPS6594_REG_INT_GPIO,
 269         TPS6594_REG_INT_GPIO1_8,
 270         TPS6594_REG_INT_STARTUP,
 271         TPS6594_REG_INT_MISC,
 272         TPS6594_REG_INT_MODERATE_ERR,
 273         TPS6594_REG_INT_SEVERE_ERR,
 274         TPS6594_REG_INT_FSM_ERR,
 275         TPS6594_REG_INT_COMM_ERR,
 276         TPS6594_REG_INT_READBACK_ERR,
 277         TPS6594_REG_INT_ESM,
 278         TPS6594_REG_RTC_STATUS,
 279 };
 280
 281 /* TPS65224 Resources */
 282
 283 static const struct resource tps65224_regulator_resources[] = {
 284         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BUCK1_UVOV, TPS65224_IRQ_NAME_BUCK1_UVOV),
 285         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BUCK2_UVOV, TPS65224_IRQ_NAME_BUCK2_UVOV),
 286         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BUCK3_UVOV, TPS65224_IRQ_NAME_BUCK3_UVOV),
 287         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BUCK4_UVOV, TPS65224_IRQ_NAME_BUCK4_UVOV),
 288         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_LDO1_UVOV, TPS65224_IRQ_NAME_LDO1_UVOV),
 289         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_LDO2_UVOV, TPS65224_IRQ_NAME_LDO2_UVOV),
 290         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_LDO3_UVOV, TPS65224_IRQ_NAME_LDO3_UVOV),
 291         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_VCCA_UVOV, TPS65224_IRQ_NAME_VCCA_UVOV),
 292         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_VMON1_UVOV, TPS65224_IRQ_NAME_VMON1_UVOV),
 293         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_VMON2_UVOV, TPS65224_IRQ_NAME_VMON2_UVOV),
 294 };
 295
 296 static const struct resource tps65224_pinctrl_resources[] = {
 297         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO1, TPS65224_IRQ_NAME_GPIO1),
 298         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO2, TPS65224_IRQ_NAME_GPIO2),
 299         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO3, TPS65224_IRQ_NAME_GPIO3),
 300         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO4, TPS65224_IRQ_NAME_GPIO4),
 301         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO5, TPS65224_IRQ_NAME_GPIO5),
 302         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_GPIO6, TPS65224_IRQ_NAME_GPIO6),
 303 };
 304
 305 static const struct resource tps65224_pfsm_resources[] = {
 306         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_VSENSE, TPS65224_IRQ_NAME_VSENSE),
 307         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_ENABLE, TPS65224_IRQ_NAME_ENABLE),
 308         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PB_SHORT, TPS65224_IRQ_NAME_PB_SHORT),
 309         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_FSD, TPS65224_IRQ_NAME_FSD),
 310         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_SOFT_REBOOT, TPS65224_IRQ_NAME_SOFT_REBOOT),
 311         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BIST_PASS, TPS65224_IRQ_NAME_BIST_PASS),
 312         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_EXT_CLK, TPS65224_IRQ_NAME_EXT_CLK),
 313         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_REG_UNLOCK, TPS65224_IRQ_NAME_REG_UNLOCK),
 314         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_TWARN, TPS65224_IRQ_NAME_TWARN),
 315         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PB_LONG, TPS65224_IRQ_NAME_PB_LONG),
 316         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PB_FALL, TPS65224_IRQ_NAME_PB_FALL),
 317         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PB_RISE, TPS65224_IRQ_NAME_PB_RISE),
 318         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_TSD_ORD, TPS65224_IRQ_NAME_TSD_ORD),
 319         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BIST_FAIL, TPS65224_IRQ_NAME_BIST_FAIL),
 320         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_REG_CRC_ERR, TPS65224_IRQ_NAME_REG_CRC_ERR),
 321         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_RECOV_CNT, TPS65224_IRQ_NAME_RECOV_CNT),
 322         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_TSD_IMM, TPS65224_IRQ_NAME_TSD_IMM),
 323         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_VCCA_OVP, TPS65224_IRQ_NAME_VCCA_OVP),
 324         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_PFSM_ERR, TPS65224_IRQ_NAME_PFSM_ERR),
 325         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_BG_XMON, TPS65224_IRQ_NAME_BG_XMON),
 326         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_IMM_SHUTDOWN, TPS65224_IRQ_NAME_IMM_SHUTDOWN),
 327         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_ORD_SHUTDOWN, TPS65224_IRQ_NAME_ORD_SHUTDOWN),
 328         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_MCU_PWR_ERR, TPS65224_IRQ_NAME_MCU_PWR_ERR),
 329         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_SOC_PWR_ERR, TPS65224_IRQ_NAME_SOC_PWR_ERR),
 330         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_COMM_ERR, TPS65224_IRQ_NAME_COMM_ERR),
 331         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_I2C2_ERR, TPS65224_IRQ_NAME_I2C2_ERR),
 332 };
 333
 334 static const struct resource tps65224_adc_resources[] = {
 335         DEFINE_RES_IRQ_NAMED(TPS65224_IRQ_ADC_CONV_READY, TPS65224_IRQ_NAME_ADC_CONV_READY),
 336 };
 337
 338 static const struct mfd_cell tps65224_common_cells[] = {
 339         MFD_CELL_RES("tps65224-adc", tps65224_adc_resources),
 340         MFD_CELL_RES("tps6594-pfsm", tps65224_pfsm_resources),
 341         MFD_CELL_RES("tps6594-pinctrl", tps65224_pinctrl_resources),
 342         MFD_CELL_RES("tps6594-regulator", tps65224_regulator_resources),
 343 };
 344
 345 static const struct regmap_irq tps65224_irqs[] = {
 346         /* INT_BUCK register */
 347         REGMAP_IRQ_REG(TPS65224_IRQ_BUCK1_UVOV, 0, TPS65224_BIT_BUCK1_UVOV_INT),
 348         REGMAP_IRQ_REG(TPS65224_IRQ_BUCK2_UVOV, 0, TPS65224_BIT_BUCK2_UVOV_INT),
 349         REGMAP_IRQ_REG(TPS65224_IRQ_BUCK3_UVOV, 0, TPS65224_BIT_BUCK3_UVOV_INT),
 350         REGMAP_IRQ_REG(TPS65224_IRQ_BUCK4_UVOV, 0, TPS65224_BIT_BUCK4_UVOV_INT),
 351
 352         /* INT_VMON_LDO register */
 353         REGMAP_IRQ_REG(TPS65224_IRQ_LDO1_UVOV, 1, TPS65224_BIT_LDO1_UVOV_INT),
 354         REGMAP_IRQ_REG(TPS65224_IRQ_LDO2_UVOV, 1, TPS65224_BIT_LDO2_UVOV_INT),
 355         REGMAP_IRQ_REG(TPS65224_IRQ_LDO3_UVOV, 1, TPS65224_BIT_LDO3_UVOV_INT),
 356         REGMAP_IRQ_REG(TPS65224_IRQ_VCCA_UVOV, 1, TPS65224_BIT_VCCA_UVOV_INT),
 357         REGMAP_IRQ_REG(TPS65224_IRQ_VMON1_UVOV, 1, TPS65224_BIT_VMON1_UVOV_INT),
 358         REGMAP_IRQ_REG(TPS65224_IRQ_VMON2_UVOV, 1, TPS65224_BIT_VMON2_UVOV_INT),
 359
 360         /* INT_GPIO register */
 361         REGMAP_IRQ_REG(TPS65224_IRQ_GPIO1, 2, TPS65224_BIT_GPIO1_INT),
 362         REGMAP_IRQ_REG(TPS65224_IRQ_GPIO2, 2, TPS65224_BIT_GPIO2_INT),
 363         REGMAP_IRQ_REG(TPS65224_IRQ_GPIO3, 2, TPS65224_BIT_GPIO3_INT),
 364         REGMAP_IRQ_REG(TPS65224_IRQ_GPIO4, 2, TPS65224_BIT_GPIO4_INT),
 365         REGMAP_IRQ_REG(TPS65224_IRQ_GPIO5, 2, TPS65224_BIT_GPIO5_INT),
 366         REGMAP_IRQ_REG(TPS65224_IRQ_GPIO6, 2, TPS65224_BIT_GPIO6_INT),
 367
 368         /* INT_STARTUP register */
 369         REGMAP_IRQ_REG(TPS65224_IRQ_VSENSE, 3, TPS65224_BIT_VSENSE_INT),
 370         REGMAP_IRQ_REG(TPS65224_IRQ_ENABLE, 3, TPS6594_BIT_ENABLE_INT),
 371         REGMAP_IRQ_REG(TPS65224_IRQ_PB_SHORT, 3, TPS65224_BIT_PB_SHORT_INT),
 372         REGMAP_IRQ_REG(TPS65224_IRQ_FSD, 3, TPS6594_BIT_FSD_INT),
 373         REGMAP_IRQ_REG(TPS65224_IRQ_SOFT_REBOOT, 3, TPS6594_BIT_SOFT_REBOOT_INT),
 374
 375         /* INT_MISC register */
 376         REGMAP_IRQ_REG(TPS65224_IRQ_BIST_PASS, 4, TPS6594_BIT_BIST_PASS_INT),
 377         REGMAP_IRQ_REG(TPS65224_IRQ_EXT_CLK, 4, TPS6594_BIT_EXT_CLK_INT),
 378         REGMAP_IRQ_REG(TPS65224_IRQ_REG_UNLOCK, 4, TPS65224_BIT_REG_UNLOCK_INT),
 379         REGMAP_IRQ_REG(TPS65224_IRQ_TWARN, 4, TPS6594_BIT_TWARN_INT),
 380         REGMAP_IRQ_REG(TPS65224_IRQ_PB_LONG, 4, TPS65224_BIT_PB_LONG_INT),
 381         REGMAP_IRQ_REG(TPS65224_IRQ_PB_FALL, 4, TPS65224_BIT_PB_FALL_INT),
 382         REGMAP_IRQ_REG(TPS65224_IRQ_PB_RISE, 4, TPS65224_BIT_PB_RISE_INT),
 383         REGMAP_IRQ_REG(TPS65224_IRQ_ADC_CONV_READY, 4, TPS65224_BIT_ADC_CONV_READY_INT),
 384
 385         /* INT_MODERATE_ERR register */
 386         REGMAP_IRQ_REG(TPS65224_IRQ_TSD_ORD, 5, TPS6594_BIT_TSD_ORD_INT),
 387         REGMAP_IRQ_REG(TPS65224_IRQ_BIST_FAIL, 5, TPS6594_BIT_BIST_FAIL_INT),
 388         REGMAP_IRQ_REG(TPS65224_IRQ_REG_CRC_ERR, 5, TPS6594_BIT_REG_CRC_ERR_INT),
 389         REGMAP_IRQ_REG(TPS65224_IRQ_RECOV_CNT, 5, TPS6594_BIT_RECOV_CNT_INT),
 390
 391         /* INT_SEVERE_ERR register */
 392         REGMAP_IRQ_REG(TPS65224_IRQ_TSD_IMM, 6, TPS6594_BIT_TSD_IMM_INT),
 393         REGMAP_IRQ_REG(TPS65224_IRQ_VCCA_OVP, 6, TPS6594_BIT_VCCA_OVP_INT),
 394         REGMAP_IRQ_REG(TPS65224_IRQ_PFSM_ERR, 6, TPS6594_BIT_PFSM_ERR_INT),
 395         REGMAP_IRQ_REG(TPS65224_IRQ_BG_XMON, 6, TPS65224_BIT_BG_XMON_INT),
 396
 397         /* INT_FSM_ERR register */
 398         REGMAP_IRQ_REG(TPS65224_IRQ_IMM_SHUTDOWN, 7, TPS6594_BIT_IMM_SHUTDOWN_INT),
 399         REGMAP_IRQ_REG(TPS65224_IRQ_ORD_SHUTDOWN, 7, TPS6594_BIT_ORD_SHUTDOWN_INT),
 400         REGMAP_IRQ_REG(TPS65224_IRQ_MCU_PWR_ERR, 7, TPS6594_BIT_MCU_PWR_ERR_INT),
 401         REGMAP_IRQ_REG(TPS65224_IRQ_SOC_PWR_ERR, 7, TPS6594_BIT_SOC_PWR_ERR_INT),
 402         REGMAP_IRQ_REG(TPS65224_IRQ_COMM_ERR, 7, TPS6594_BIT_COMM_ERR_INT),
 403         REGMAP_IRQ_REG(TPS65224_IRQ_I2C2_ERR, 7, TPS65224_BIT_I2C2_ERR_INT),
 404 };
 405
 406 static const unsigned int tps65224_irq_reg[] = {
 407         TPS6594_REG_INT_BUCK,
 408         TPS6594_REG_INT_LDO_VMON,
 409         TPS6594_REG_INT_GPIO,
 410         TPS6594_REG_INT_STARTUP,
 411         TPS6594_REG_INT_MISC,
 412         TPS6594_REG_INT_MODERATE_ERR,
 413         TPS6594_REG_INT_SEVERE_ERR,
 414         TPS6594_REG_INT_FSM_ERR,
 415 };
 416
 417 static inline unsigned int tps6594_get_irq_reg(struct regmap_irq_chip_data *data,
 418                                                unsigned int base, int index)
 419 {
 420         return tps6594_irq_reg[index];
 421 };
 422
 423 static inline unsigned int tps65224_get_irq_reg(struct regmap_irq_chip_data *data,
 424                                                 unsigned int base, int index)
 425 {
 426         return tps65224_irq_reg[index];
 427 };
 428
 429 static int tps6594_handle_post_irq(void *irq_drv_data)
 430 {
 431         struct tps6594 *tps = irq_drv_data;
 432         int ret = 0;
 433         unsigned int regmap_reg, mask_val;
 434
 435         /*
 436          * When CRC is enabled, writing to a read-only bit triggers an error,
 437          * and COMM_ADR_ERR_INT bit is set. Besides, bits indicating interrupts
 438          * (that must be cleared) and read-only bits are sometimes grouped in
 439          * the same register.
 440          * Since regmap clears interrupts by doing a write per register, clearing
 441          * an interrupt bit in a register containing also a read-only bit makes
 442          * COMM_ADR_ERR_INT bit set. Clear immediately this bit to avoid raising
 443          * a new interrupt.
 444          */
 445         if (tps->use_crc) {
 446                 if (tps->chip_id == TPS65224) {
 447                         regmap_reg = TPS6594_REG_INT_FSM_ERR;
 448                         mask_val = TPS6594_BIT_COMM_ERR_INT;
 449                 } else {
 450                         regmap_reg = TPS6594_REG_INT_COMM_ERR;
 451                         mask_val = TPS6594_BIT_COMM_ADR_ERR_INT;
 452                 }
 453
 454                 ret = regmap_write_bits(tps->regmap, regmap_reg, mask_val, mask_val);
 455         }
 456
 457         return ret;
 458 };
 459
 460 static struct regmap_irq_chip tps6594_irq_chip = {
 461         .ack_base = TPS6594_REG_INT_BUCK1_2,
 462         .ack_invert = 1,
 463         .clear_ack = 1,
 464         .init_ack_masked = 1,
 465         .num_regs = ARRAY_SIZE(tps6594_irq_reg),
 466         .irqs = tps6594_irqs,
 467         .num_irqs = ARRAY_SIZE(tps6594_irqs),
 468         .get_irq_reg = tps6594_get_irq_reg,
 469         .handle_post_irq = tps6594_handle_post_irq,
 470 };
 471
 472 static struct regmap_irq_chip tps65224_irq_chip = {
 473         .ack_base = TPS6594_REG_INT_BUCK,
 474         .ack_invert = 1,
 475         .clear_ack = 1,
 476         .init_ack_masked = 1,
 477         .num_regs = ARRAY_SIZE(tps65224_irq_reg),
 478         .irqs = tps65224_irqs,
 479         .num_irqs = ARRAY_SIZE(tps65224_irqs),
 480         .get_irq_reg = tps65224_get_irq_reg,
 481         .handle_post_irq = tps6594_handle_post_irq,
 482 };
 483
 484 static const struct regmap_range tps6594_volatile_ranges[] = {
 485         regmap_reg_range(TPS6594_REG_INT_TOP, TPS6594_REG_STAT_READBACK_ERR),
 486         regmap_reg_range(TPS6594_REG_RTC_STATUS, TPS6594_REG_RTC_STATUS),
 487 };
 488
 489 const struct regmap_access_table tps6594_volatile_table = {
 490         .yes_ranges = tps6594_volatile_ranges,
 491         .n_yes_ranges = ARRAY_SIZE(tps6594_volatile_ranges),
 492 };
 493 EXPORT_SYMBOL_GPL(tps6594_volatile_table);
 494
 495 static const struct regmap_range tps65224_volatile_ranges[] = {
 496         regmap_reg_range(TPS6594_REG_INT_TOP, TPS6594_REG_STAT_SEVERE_ERR),
 497 };
 498
 499 const struct regmap_access_table tps65224_volatile_table = {
 500         .yes_ranges = tps65224_volatile_ranges,
 501         .n_yes_ranges = ARRAY_SIZE(tps65224_volatile_ranges),
 502 };
 503 EXPORT_SYMBOL_GPL(tps65224_volatile_table);
 504
 505 static int tps6594_check_crc_mode(struct tps6594 *tps, bool primary_pmic)
 506 {
 507         int ret;
 508         unsigned int regmap_reg, mask_val;
 509
 510         if (tps->chip_id == TPS65224) {
 511                 regmap_reg = TPS6594_REG_CONFIG_2;
 512                 mask_val = TPS65224_BIT_I2C1_SPI_CRC_EN;
 513         } else {
 514                 regmap_reg = TPS6594_REG_SERIAL_IF_CONFIG;
 515                 mask_val = TPS6594_BIT_I2C1_SPI_CRC_EN;
 516         }
 517
 518         /*
 519          * Check if CRC is enabled.
 520          * Once CRC is enabled, it can't be disabled until next power cycle.
 521          */
 522         tps->use_crc = true;
 523         ret = regmap_test_bits(tps->regmap, regmap_reg, mask_val);
 524         if (ret == 0) {
 525                 ret = -EIO;
 526         } else if (ret > 0) {
 527                 dev_info(tps->dev, "CRC feature enabled on %s PMIC",
 528                          primary_pmic ? "primary" : "secondary");
 529                 ret = 0;
 530         }
 531
 532         return ret;
 533 }
 534
 535 static int tps6594_set_crc_feature(struct tps6594 *tps)
 536 {
 537         int ret;
 538         unsigned int regmap_reg, mask_val;
 539
 540         if (tps->chip_id == TPS65224) {
 541                 regmap_reg = TPS6594_REG_CONFIG_2;
 542                 mask_val = TPS65224_BIT_I2C1_SPI_CRC_EN;
 543         } else {
 544                 regmap_reg = TPS6594_REG_FSM_I2C_TRIGGERS;
 545                 mask_val = TPS6594_BIT_TRIGGER_I2C(2);
 546         }
 547
 548         ret = tps6594_check_crc_mode(tps, true);
 549         if (ret) {
 550                 /*
 551                  * If CRC is not already enabled, force PFSM I2C_2 trigger to enable it
 552                  * on primary PMIC.
 553                  */
 554                 tps->use_crc = false;
 555                 ret = regmap_write_bits(tps->regmap, regmap_reg, mask_val, mask_val);
 556                 if (ret)
 557                         return ret;
 558
 559                 /*
 560                  * Wait for PFSM to process trigger.
 561                  * The datasheet indicates 2 ms, and clock specification is +/-5%.
 562                  * 4 ms should provide sufficient margin.
 563                  */
 564                 usleep_range(4000, 5000);
 565
 566                 ret = tps6594_check_crc_mode(tps, true);
 567         }
 568
 569         return ret;
 570 }
 571
 572 static int tps6594_enable_crc(struct tps6594 *tps)
 573 {
 574         struct device *dev = tps->dev;
 575         unsigned int is_primary;
 576         unsigned long timeout = msecs_to_jiffies(TPS6594_CRC_SYNC_TIMEOUT_MS);
 577         int ret;
 578
 579         /*
 580          * CRC mode can be used with I2C or SPI protocols.
 581          * If this mode is specified for primary PMIC, it will also be applied to secondary PMICs
 582          * through SPMI serial interface.
 583          * In this multi-PMIC synchronization scheme, the primary PMIC is the controller device
 584          * on the SPMI bus, and the secondary PMICs are the target devices on the SPMI bus.
 585          */
 586         is_primary = of_property_read_bool(dev->of_node, "ti,primary-pmic");
 587         if (is_primary) {
 588                 /* Enable CRC feature on primary PMIC */
 589                 ret = tps6594_set_crc_feature(tps);
 590                 if (ret)
 591                         return ret;
 592
 593                 /* Notify secondary PMICs that CRC feature is enabled */
 594                 complete_all(&tps6594_crc_comp);
 595         } else {
 596                 /* Wait for CRC feature enabling event from primary PMIC */
 597                 ret = wait_for_completion_interruptible_timeout(&tps6594_crc_comp, timeout);
 598                 if (ret == 0)
 599                         ret = -ETIMEDOUT;
 600                 else if (ret > 0)
 601                         ret = tps6594_check_crc_mode(tps, false);
 602         }
 603
 604         return ret;
 605 }
 606
 607 int tps6594_device_init(struct tps6594 *tps, bool enable_crc)
 608 {
 609         struct device *dev = tps->dev;
 610         int ret;
 611         struct regmap_irq_chip *irq_chip;
 612         const struct mfd_cell *cells;
 613         int n_cells;
 614
 615         if (enable_crc) {
 616                 ret = tps6594_enable_crc(tps);
 617                 if (ret)
 618                         return dev_err_probe(dev, ret, "Failed to enable CRC\n");
 619         }
 620
 621         /* Keep PMIC in ACTIVE state */
 622         ret = regmap_set_bits(tps->regmap, TPS6594_REG_FSM_NSLEEP_TRIGGERS,
 623                               TPS6594_BIT_NSLEEP1B | TPS6594_BIT_NSLEEP2B);
 624         if (ret)
 625                 return dev_err_probe(dev, ret, "Failed to set PMIC state\n");
 626
 627         if (tps->chip_id == TPS65224) {
 628                 irq_chip = &tps65224_irq_chip;
 629                 n_cells = ARRAY_SIZE(tps65224_common_cells);
 630                 cells = tps65224_common_cells;
 631         } else {
 632                 irq_chip = &tps6594_irq_chip;
 633                 n_cells = ARRAY_SIZE(tps6594_common_cells);
 634                 cells = tps6594_common_cells;
 635         }
 636
 637         irq_chip->irq_drv_data = tps;
 638         irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%ld-0x%02x",
 639                                         dev->driver->name, tps->chip_id, tps->reg);
 640
 641         if (!irq_chip->name)
 642                 return -ENOMEM;
 643
 644         ret = devm_regmap_add_irq_chip(dev, tps->regmap, tps->irq, IRQF_SHARED | IRQF_ONESHOT,
 645                                        0, irq_chip, &tps->irq_data);
 646         if (ret)
 647                 return dev_err_probe(dev, ret, "Failed to add regmap IRQ\n");
 648
 649         ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, cells, n_cells, NULL, 0,
 650                                    regmap_irq_get_domain(tps->irq_data));
 651         if (ret)
 652                 return dev_err_probe(dev, ret, "Failed to add common child devices\n");
 653
 654         /* No RTC for LP8764 and TPS65224 */
 655         if (tps->chip_id != LP8764 && tps->chip_id != TPS65224) {
 656                 ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, tps6594_rtc_cells,
 657                                            ARRAY_SIZE(tps6594_rtc_cells), NULL, 0,
 658                                            regmap_irq_get_domain(tps->irq_data));
 659                 if (ret)
 660                         return dev_err_probe(dev, ret, "Failed to add RTC child device\n");
 661         }
 662
 663         return 0;
 664 }
 665 EXPORT_SYMBOL_GPL(tps6594_device_init);
 666
 667 MODULE_AUTHOR("Julien Panis <jpanis@baylibre.com>");
 668 MODULE_AUTHOR("Bhargav Raviprakash <bhargav.r@ltts.com");
 669 MODULE_DESCRIPTION("TPS6594 Driver");
 670 MODULE_LICENSE("GPL");