Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt

   1 NVIDIA Tegra Memory Controller device tree bindings
   2 ===================================================
   3
   4 memory-controller node
   5 ----------------------
   6
   7 Required properties:
   8 - compatible: Should be "nvidia,tegra<chip>-mc"
   9 - reg: Physical base address and length of the controller's registers.
  10 - clocks: Must contain an entry for each entry in clock-names.
  11   See ../clocks/clock-bindings.txt for details.
  12 - clock-names: Must include the following entries:
  13   - mc: the module's clock input
  14 - interrupts: The interrupt outputs from the controller.
  15 - #reset-cells : Should be 1. This cell represents memory client module ID.
  16   The assignments may be found in header file <dt-bindings/memory/tegra30-mc.h>
  17   or in the TRM documentation.
  18
  19 Required properties for Tegra30, Tegra114, Tegra124, Tegra132 and Tegra210:
  20 - #iommu-cells: Should be 1. The single cell of the IOMMU specifier defines
  21   the SWGROUP of the master.
  22
  23 This device implements an IOMMU that complies with the generic IOMMU binding.
  24 See ../iommu/iommu.txt for details.
  25
  26 emc-timings subnode
  27 -------------------
  28
  29 The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in
  30 register PMC_STRAPPING_OPT_A).
  31
  32 Required properties for "emc-timings" nodes :
  33 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for.
  34
  35 timing subnode
  36 --------------
  37
  38 Each "emc-timings" node should contain a subnode for every supported EMC clock rate.
  39
  40 Required properties for timing nodes :
  41 - clock-frequency : Should contain the memory clock rate in Hz.
  42 - nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC
  43 (see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be
  44 specified, according to the board documentation:
  45
  46         MC_EMEM_ARB_CFG
  47         MC_EMEM_ARB_OUTSTANDING_REQ
  48         MC_EMEM_ARB_TIMING_RCD
  49         MC_EMEM_ARB_TIMING_RP
  50         MC_EMEM_ARB_TIMING_RC
  51         MC_EMEM_ARB_TIMING_RAS
  52         MC_EMEM_ARB_TIMING_FAW
  53         MC_EMEM_ARB_TIMING_RRD
  54         MC_EMEM_ARB_TIMING_RAP2PRE
  55         MC_EMEM_ARB_TIMING_WAP2PRE
  56         MC_EMEM_ARB_TIMING_R2R
  57         MC_EMEM_ARB_TIMING_W2W
  58         MC_EMEM_ARB_TIMING_R2W
  59         MC_EMEM_ARB_TIMING_W2R
  60         MC_EMEM_ARB_DA_TURNS
  61         MC_EMEM_ARB_DA_COVERS
  62         MC_EMEM_ARB_MISC0
  63         MC_EMEM_ARB_MISC1
  64         MC_EMEM_ARB_RING1_THROTTLE
  65
  66 Example SoC include file:
  67
  68 / {
  69         mc: memory-controller@70019000 {
  70                 compatible = "nvidia,tegra124-mc";
  71                 reg = <0x0 0x70019000 0x0 0x1000>;
  72                 clocks = <&tegra_car TEGRA124_CLK_MC>;
  73                 clock-names = "mc";
  74
  75                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
  76
  77                 #iommu-cells = <1>;
  78                 #reset-cells = <1>;
  79         };
  80
  81         sdhci@700b0000 {
  82                 compatible = "nvidia,tegra124-sdhci";
  83                 ...
  84                 iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
  85                 resets = <&mc TEGRA124_MC_RESET_SDMMC1>;
  86         };
  87 };
  88
  89 Example board file:
  90
  91 / {
  92         memory-controller@70019000 {
  93                 emc-timings-3 {
  94                         nvidia,ram-code = <3>;
  95
  96                         timing-12750000 {
  97                                 clock-frequency = <12750000>;
  98
  99                                 nvidia,emem-configuration = <
 100                                         0x40040001 /* MC_EMEM_ARB_CFG */
 101                                         0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
 102                                         0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
 103                                         0x00000001 /* MC_EMEM_ARB_TIMING_RP */
 104                                         0x00000002 /* MC_EMEM_ARB_TIMING_RC */
 105                                         0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
 106                                         0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
 107                                         0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
 108                                         0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
 109                                         0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
 110                                         0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
 111                                         0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
 112                                         0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
 113                                         0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
 114                                         0x06030203 /* MC_EMEM_ARB_DA_TURNS */
 115                                         0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
 116                                         0x77e30303 /* MC_EMEM_ARB_MISC0 */
 117                                         0x70000f03 /* MC_EMEM_ARB_MISC1 */
 118                                         0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
 119                                 >;
 120                         };
 121                 };
 122         };
 123 };