sound/oss/dmasound/awacs_defs.h

   1 /*********************************************************/
   2 /* This file was written by someone, somewhere, sometime */
   3 /* And is released into the Public Domain                */
   4 /*********************************************************/
   5
   6 #ifndef _AWACS_DEFS_H_
   7 #define _AWACS_DEFS_H_
   8
   9 /*******************************/
  10 /* AWACs Audio Register Layout */
  11 /*******************************/
  12
  13 struct awacs_regs {
  14     unsigned    control;        /* Audio control register */
  15     unsigned    pad0[3];
  16     unsigned    codec_ctrl;     /* Codec control register */
  17     unsigned    pad1[3];
  18     unsigned    codec_stat;     /* Codec status register */
  19     unsigned    pad2[3];
  20     unsigned    clip_count;     /* Clipping count register */
  21     unsigned    pad3[3];
  22     unsigned    byteswap;       /* Data is little-endian if 1 */
  23 };
  24
  25 /*******************/
  26 /* Audio Bit Masks */
  27 /*******************/
  28
  29 /* Audio Control Reg Bit Masks */
  30 /* ----- ------- --- --- ----- */
  31 #define MASK_ISFSEL     (0xf)           /* Input SubFrame Select */
  32 #define MASK_OSFSEL     (0xf << 4)      /* Output SubFrame Select */
  33 #define MASK_RATE       (0x7 << 8)      /* Sound Rate */
  34 #define MASK_CNTLERR    (0x1 << 11)     /* Error */
  35 #define MASK_PORTCHG    (0x1 << 12)     /* Port Change */
  36 #define MASK_IEE        (0x1 << 13)     /* Enable Interrupt on Error */
  37 #define MASK_IEPC       (0x1 << 14)     /* Enable Interrupt on Port Change */
  38 #define MASK_SSFSEL     (0x3 << 15)     /* Status SubFrame Select */
  39
  40 /* Audio Codec Control Reg Bit Masks */
  41 /* ----- ----- ------- --- --- ----- */
  42 #define MASK_NEWECMD    (0x1 << 24)     /* Lock: don't write to reg when 1 */
  43 #define MASK_EMODESEL   (0x3 << 22)     /* Send info out on which frame? */
  44 #define MASK_EXMODEADDR (0x3ff << 12)   /* Extended Mode Address -- 10 bits */
  45 #define MASK_EXMODEDATA (0xfff)         /* Extended Mode Data -- 12 bits */
  46
  47 /* Audio Codec Control Address Values / Masks */
  48 /* ----- ----- ------- ------- ------ - ----- */
  49 #define MASK_ADDR0      (0x0 << 12)     /* Expanded Data Mode Address 0 */
  50 #define MASK_ADDR_MUX   MASK_ADDR0      /* Mux Control */
  51 #define MASK_ADDR_GAIN  MASK_ADDR0
  52
  53 #define MASK_ADDR1      (0x1 << 12)     /* Expanded Data Mode Address 1 */
  54 #define MASK_ADDR_MUTE  MASK_ADDR1
  55 #define MASK_ADDR_RATE  MASK_ADDR1
  56
  57 #define MASK_ADDR2      (0x2 << 12)     /* Expanded Data Mode Address 2 */
  58 #define MASK_ADDR_VOLA  MASK_ADDR2      /* Volume Control A -- Headphones */
  59 #define MASK_ADDR_VOLHD MASK_ADDR2
  60
  61 #define MASK_ADDR4      (0x4 << 12)     /* Expanded Data Mode Address 4 */
  62 #define MASK_ADDR_VOLC  MASK_ADDR4      /* Volume Control C -- Speaker */
  63 #define MASK_ADDR_VOLSPK MASK_ADDR4
  64
  65 /* additional registers of screamer */
  66 #define MASK_ADDR5      (0x5 << 12)     /* Expanded Data Mode Address 5 */
  67 #define MASK_ADDR6      (0x6 << 12)     /* Expanded Data Mode Address 6 */
  68 #define MASK_ADDR7      (0x7 << 12)     /* Expanded Data Mode Address 7 */
  69
  70 /* Address 0 Bit Masks & Macros */
  71 /* ------- - --- ----- - ------ */
  72 #define MASK_GAINRIGHT  (0xf)           /* Gain Right Mask */
  73 #define MASK_GAINLEFT   (0xf << 4)      /* Gain Left Mask */
  74 #define MASK_GAINLINE   (0x1 << 8)      /* Disable Mic preamp */
  75 #define MASK_GAINMIC    (0x0 << 8)      /* Enable Mic preamp */
  76
  77 #define MASK_MUX_CD     (0x1 << 9)      /* Select CD in MUX */
  78 #define MASK_MUX_MIC    (0x1 << 10)     /* Select Mic in MUX */
  79 #define MASK_MUX_AUDIN  (0x1 << 11)     /* Select Audio In in MUX */
  80 #define MASK_MUX_LINE   MASK_MUX_AUDIN
  81
  82 #define GAINRIGHT(x)    ((x) & MASK_GAINRIGHT)
  83 #define GAINLEFT(x)     (((x) << 4) & MASK_GAINLEFT)
  84
  85 #define DEF_CD_GAIN 0x00bb
  86 #define DEF_MIC_GAIN 0x00cc
  87
  88 /* Address 1 Bit Masks */
  89 /* ------- - --- ----- */
  90 #define MASK_ADDR1RES1  (0x3)           /* Reserved */
  91 #define MASK_RECALIBRATE (0x1 << 2)     /* Recalibrate */
  92 #define MASK_SAMPLERATE (0x7 << 3)      /* Sample Rate: */
  93 #define MASK_LOOPTHRU   (0x1 << 6)      /* Loopthrough Enable */
  94 #define MASK_CMUTE      (0x1 << 7)      /* Output C (Speaker) Mute when 1 */
  95 #define MASK_SPKMUTE    MASK_CMUTE
  96 #define MASK_ADDR1RES2  (0x1 << 8)      /* Reserved */
  97 #define MASK_AMUTE      (0x1 << 9)      /* Output A (Headphone) Mute when 1 */
  98 #define MASK_HDMUTE     MASK_AMUTE
  99 #define MASK_PAROUT0    (0x1 << 10)     /* Parallel Output 0 */
 100 #define MASK_PAROUT1    (0x2 << 10)     /* Parallel Output 1 */
 101
 102 #define MASK_MIC_BOOST  (0x4)           /* screamer mic boost */
 103
 104 #define SAMPLERATE_48000        (0x0 << 3)      /* 48 or 44.1 kHz */
 105 #define SAMPLERATE_32000        (0x1 << 3)      /* 32 or 29.4 kHz */
 106 #define SAMPLERATE_24000        (0x2 << 3)      /* 24 or 22.05 kHz */
 107 #define SAMPLERATE_19200        (0x3 << 3)      /* 19.2 or 17.64 kHz */
 108 #define SAMPLERATE_16000        (0x4 << 3)      /* 16 or 14.7 kHz */
 109 #define SAMPLERATE_12000        (0x5 << 3)      /* 12 or 11.025 kHz */
 110 #define SAMPLERATE_9600         (0x6 << 3)      /* 9.6 or 8.82 kHz */
 111 #define SAMPLERATE_8000         (0x7 << 3)      /* 8 or 7.35 kHz */
 112
 113 /* Address 2 & 4 Bit Masks & Macros */
 114 /* ------- - - - --- ----- - ------ */
 115 #define MASK_OUTVOLRIGHT (0xf)          /* Output Right Volume */
 116 #define MASK_ADDR2RES1  (0x2 << 4)      /* Reserved */
 117 #define MASK_ADDR4RES1  MASK_ADDR2RES1
 118 #define MASK_OUTVOLLEFT (0xf << 6)      /* Output Left Volume */
 119 #define MASK_ADDR2RES2  (0x2 << 10)     /* Reserved */
 120 #define MASK_ADDR4RES2  MASK_ADDR2RES2
 121
 122 #define VOLRIGHT(x)     (((~(x)) & MASK_OUTVOLRIGHT))
 123 #define VOLLEFT(x)      (((~(x)) << 6) & MASK_OUTVOLLEFT)
 124
 125 /* Audio Codec Status Reg Bit Masks */
 126 /* ----- ----- ------ --- --- ----- */
 127 #define MASK_EXTEND     (0x1 << 23)     /* Extend */
 128 #define MASK_VALID      (0x1 << 22)     /* Valid Data? */
 129 #define MASK_OFLEFT     (0x1 << 21)     /* Overflow Left */
 130 #define MASK_OFRIGHT    (0x1 << 20)     /* Overflow Right */
 131 #define MASK_ERRCODE    (0xf << 16)     /* Error Code */
 132 #define MASK_REVISION   (0xf << 12)     /* Revision Number */
 133 #define MASK_MFGID      (0xf << 8)      /* Mfg. ID */
 134 #define MASK_CODSTATRES (0xf << 4)      /* bits 4 - 7 reserved */
 135 #define MASK_INPPORT    (0xf)           /* Input Port */
 136 #define MASK_HDPCONN    8               /* headphone plugged in */
 137
 138 /* Clipping Count Reg Bit Masks */
 139 /* -------- ----- --- --- ----- */
 140 #define MASK_CLIPLEFT   (0xff << 7)     /* Clipping Count, Left Channel */
 141 #define MASK_CLIPRIGHT  (0xff)          /* Clipping Count, Right Channel */
 142
 143 /* DBDMA ChannelStatus Bit Masks */
 144 /* ----- ------------- --- ----- */
 145 #define MASK_CSERR      (0x1 << 7)      /* Error */
 146 #define MASK_EOI        (0x1 << 6)      /* End of Input -- only for Input Channel */
 147 #define MASK_CSUNUSED   (0x1f << 1)     /* bits 1-5 not used */
 148 #define MASK_WAIT       (0x1)           /* Wait */
 149
 150 /* Various Rates */
 151 /* ------- ----- */
 152 #define RATE_48000      (0x0 << 8)      /* 48 kHz */
 153 #define RATE_44100      (0x0 << 8)      /* 44.1 kHz */
 154 #define RATE_32000      (0x1 << 8)      /* 32 kHz */
 155 #define RATE_29400      (0x1 << 8)      /* 29.4 kHz */
 156 #define RATE_24000      (0x2 << 8)      /* 24 kHz */
 157 #define RATE_22050      (0x2 << 8)      /* 22.05 kHz */
 158 #define RATE_19200      (0x3 << 8)      /* 19.2 kHz */
 159 #define RATE_17640      (0x3 << 8)      /* 17.64 kHz */
 160 #define RATE_16000      (0x4 << 8)      /* 16 kHz */
 161 #define RATE_14700      (0x4 << 8)      /* 14.7 kHz */
 162 #define RATE_12000      (0x5 << 8)      /* 12 kHz */
 163 #define RATE_11025      (0x5 << 8)      /* 11.025 kHz */
 164 #define RATE_9600       (0x6 << 8)      /* 9.6 kHz */
 165 #define RATE_8820       (0x6 << 8)      /* 8.82 kHz */
 166 #define RATE_8000       (0x7 << 8)      /* 8 kHz */
 167 #define RATE_7350       (0x7 << 8)      /* 7.35 kHz */
 168
 169 #define RATE_LOW        1       /* HIGH = 48kHz, etc;  LOW = 44.1kHz, etc. */
 170
 171 /*******************/
 172 /* Burgundy values */
 173 /*******************/
 174
 175 #define MASK_ADDR_BURGUNDY_INPSEL21 (0x11 << 12)
 176 #define MASK_ADDR_BURGUNDY_INPSEL3 (0x12 << 12)
 177
 178 #define MASK_ADDR_BURGUNDY_GAINCH1 (0x13 << 12)
 179 #define MASK_ADDR_BURGUNDY_GAINCH2 (0x14 << 12)
 180 #define MASK_ADDR_BURGUNDY_GAINCH3 (0x15 << 12)
 181 #define MASK_ADDR_BURGUNDY_GAINCH4 (0x16 << 12)
 182
 183 #define MASK_ADDR_BURGUNDY_VOLCH1 (0x20 << 12)
 184 #define MASK_ADDR_BURGUNDY_VOLCH2 (0x21 << 12)
 185 #define MASK_ADDR_BURGUNDY_VOLCH3 (0x22 << 12)
 186 #define MASK_ADDR_BURGUNDY_VOLCH4 (0x23 << 12)
 187
 188 #define MASK_ADDR_BURGUNDY_OUTPUTSELECTS (0x2B << 12)
 189 #define MASK_ADDR_BURGUNDY_OUTPUTENABLES (0x2F << 12)
 190
 191 #define MASK_ADDR_BURGUNDY_MASTER_VOLUME (0x30 << 12)
 192
 193 #define MASK_ADDR_BURGUNDY_MORE_OUTPUTENABLES (0x60 << 12)
 194
 195 #define MASK_ADDR_BURGUNDY_ATTENSPEAKER (0x62 << 12)
 196 #define MASK_ADDR_BURGUNDY_ATTENLINEOUT (0x63 << 12)
 197 #define MASK_ADDR_BURGUNDY_ATTENHP (0x64 << 12)
 198
 199 #define MASK_ADDR_BURGUNDY_VOLCD (MASK_ADDR_BURGUNDY_VOLCH1)
 200 #define MASK_ADDR_BURGUNDY_VOLLINE (MASK_ADDR_BURGUNDY_VOLCH2)
 201 #define MASK_ADDR_BURGUNDY_VOLMIC (MASK_ADDR_BURGUNDY_VOLCH3)
 202 #define MASK_ADDR_BURGUNDY_VOLMODEM (MASK_ADDR_BURGUNDY_VOLCH4)
 203
 204 #define MASK_ADDR_BURGUNDY_GAINCD (MASK_ADDR_BURGUNDY_GAINCH1)
 205 #define MASK_ADDR_BURGUNDY_GAINLINE (MASK_ADDR_BURGUNDY_GAINCH2)
 206 #define MASK_ADDR_BURGUNDY_GAINMIC (MASK_ADDR_BURGUNDY_GAINCH3)
 207 #define MASK_ADDR_BURGUNDY_GAINMODEM (MASK_ADDR_BURGUNDY_VOLCH4)
 208
 209
 210 /* These are all default values for the burgundy */
 211 #define DEF_BURGUNDY_INPSEL21 (0xAA)
 212 #define DEF_BURGUNDY_INPSEL3 (0x0A)
 213
 214 #define DEF_BURGUNDY_GAINCD (0x33)
 215 #define DEF_BURGUNDY_GAINLINE (0x44)
 216 #define DEF_BURGUNDY_GAINMIC (0x44)
 217 #define DEF_BURGUNDY_GAINMODEM (0x06)
 218
 219 /* Remember: lowest volume here is 0x9b */
 220 #define DEF_BURGUNDY_VOLCD (0xCCCCCCCC)
 221 #define DEF_BURGUNDY_VOLLINE (0x00000000)
 222 #define DEF_BURGUNDY_VOLMIC (0x00000000)
 223 #define DEF_BURGUNDY_VOLMODEM (0xCCCCCCCC)
 224
 225 #define DEF_BURGUNDY_OUTPUTSELECTS (0x010f010f)
 226 #define DEF_BURGUNDY_OUTPUTENABLES (0x0A)
 227
 228 #define DEF_BURGUNDY_MASTER_VOLUME (0xFFFFFFFF)
 229
 230 #define DEF_BURGUNDY_MORE_OUTPUTENABLES (0x7E)
 231
 232 #define DEF_BURGUNDY_ATTENSPEAKER (0x44)
 233 #define DEF_BURGUNDY_ATTENLINEOUT (0xCC)
 234 #define DEF_BURGUNDY_ATTENHP (0xCC)
 235
 236 /*********************/
 237 /* i2s layout values */
 238 /*********************/
 239
 240 #define I2S_REG_INT_CTL                 0x00
 241 #define I2S_REG_SERIAL_FORMAT           0x10
 242 #define I2S_REG_CODEC_MSG_OUT           0x20
 243 #define I2S_REG_CODEC_MSG_IN            0x30
 244 #define I2S_REG_FRAME_COUNT             0x40
 245 #define I2S_REG_FRAME_MATCH             0x50
 246 #define I2S_REG_DATAWORD_SIZES          0x60
 247 #define I2S_REG_PEAKLEVEL_SEL           0x70
 248 #define I2S_REG_PEAKLEVEL_IN0           0x80
 249 #define I2S_REG_PEAKLEVEL_IN1           0x90
 250
 251 #endif /* _AWACS_DEFS_H_ */